1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sparc64/mm/init.c 4 * 5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #include <linux/extable.h> 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <linux/string.h> 13 #include <linux/init.h> 14 #include <linux/memblock.h> 15 #include <linux/mm.h> 16 #include <linux/hugetlb.h> 17 #include <linux/initrd.h> 18 #include <linux/swap.h> 19 #include <linux/pagemap.h> 20 #include <linux/poison.h> 21 #include <linux/fs.h> 22 #include <linux/seq_file.h> 23 #include <linux/kprobes.h> 24 #include <linux/cache.h> 25 #include <linux/sort.h> 26 #include <linux/ioport.h> 27 #include <linux/percpu.h> 28 #include <linux/mmzone.h> 29 #include <linux/gfp.h> 30 31 #include <asm/head.h> 32 #include <asm/page.h> 33 #include <asm/pgalloc.h> 34 #include <asm/pgtable.h> 35 #include <asm/oplib.h> 36 #include <asm/iommu.h> 37 #include <asm/io.h> 38 #include <linux/uaccess.h> 39 #include <asm/mmu_context.h> 40 #include <asm/tlbflush.h> 41 #include <asm/dma.h> 42 #include <asm/starfire.h> 43 #include <asm/tlb.h> 44 #include <asm/spitfire.h> 45 #include <asm/sections.h> 46 #include <asm/tsb.h> 47 #include <asm/hypervisor.h> 48 #include <asm/prom.h> 49 #include <asm/mdesc.h> 50 #include <asm/cpudata.h> 51 #include <asm/setup.h> 52 #include <asm/irq.h> 53 54 #include "init_64.h" 55 56 unsigned long kern_linear_pte_xor[4] __read_mostly; 57 static unsigned long page_cache4v_flag; 58 59 /* A bitmap, two bits for every 256MB of physical memory. These two 60 * bits determine what page size we use for kernel linear 61 * translations. They form an index into kern_linear_pte_xor[]. The 62 * value in the indexed slot is XOR'd with the TLB miss virtual 63 * address to form the resulting TTE. The mapping is: 64 * 65 * 0 ==> 4MB 66 * 1 ==> 256MB 67 * 2 ==> 2GB 68 * 3 ==> 16GB 69 * 70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later 71 * support 2GB pages, and hopefully future cpus will support the 16GB 72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there 73 * if these larger page sizes are not supported by the cpu. 74 * 75 * It would be nice to determine this from the machine description 76 * 'cpu' properties, but we need to have this table setup before the 77 * MDESC is initialized. 78 */ 79 80 #ifndef CONFIG_DEBUG_PAGEALLOC 81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. 82 * Space is allocated for this right after the trap table in 83 * arch/sparc64/kernel/head.S 84 */ 85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; 86 #endif 87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; 88 89 static unsigned long cpu_pgsz_mask; 90 91 #define MAX_BANKS 1024 92 93 static struct linux_prom64_registers pavail[MAX_BANKS]; 94 static int pavail_ents; 95 96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; 97 98 static int cmp_p64(const void *a, const void *b) 99 { 100 const struct linux_prom64_registers *x = a, *y = b; 101 102 if (x->phys_addr > y->phys_addr) 103 return 1; 104 if (x->phys_addr < y->phys_addr) 105 return -1; 106 return 0; 107 } 108 109 static void __init read_obp_memory(const char *property, 110 struct linux_prom64_registers *regs, 111 int *num_ents) 112 { 113 phandle node = prom_finddevice("/memory"); 114 int prop_size = prom_getproplen(node, property); 115 int ents, ret, i; 116 117 ents = prop_size / sizeof(struct linux_prom64_registers); 118 if (ents > MAX_BANKS) { 119 prom_printf("The machine has more %s property entries than " 120 "this kernel can support (%d).\n", 121 property, MAX_BANKS); 122 prom_halt(); 123 } 124 125 ret = prom_getproperty(node, property, (char *) regs, prop_size); 126 if (ret == -1) { 127 prom_printf("Couldn't get %s property from /memory.\n", 128 property); 129 prom_halt(); 130 } 131 132 /* Sanitize what we got from the firmware, by page aligning 133 * everything. 134 */ 135 for (i = 0; i < ents; i++) { 136 unsigned long base, size; 137 138 base = regs[i].phys_addr; 139 size = regs[i].reg_size; 140 141 size &= PAGE_MASK; 142 if (base & ~PAGE_MASK) { 143 unsigned long new_base = PAGE_ALIGN(base); 144 145 size -= new_base - base; 146 if ((long) size < 0L) 147 size = 0UL; 148 base = new_base; 149 } 150 if (size == 0UL) { 151 /* If it is empty, simply get rid of it. 152 * This simplifies the logic of the other 153 * functions that process these arrays. 154 */ 155 memmove(®s[i], ®s[i + 1], 156 (ents - i - 1) * sizeof(regs[0])); 157 i--; 158 ents--; 159 continue; 160 } 161 regs[i].phys_addr = base; 162 regs[i].reg_size = size; 163 } 164 165 *num_ents = ents; 166 167 sort(regs, ents, sizeof(struct linux_prom64_registers), 168 cmp_p64, NULL); 169 } 170 171 /* Kernel physical address base and size in bytes. */ 172 unsigned long kern_base __read_mostly; 173 unsigned long kern_size __read_mostly; 174 175 /* Initial ramdisk setup */ 176 extern unsigned long sparc_ramdisk_image64; 177 extern unsigned int sparc_ramdisk_image; 178 extern unsigned int sparc_ramdisk_size; 179 180 struct page *mem_map_zero __read_mostly; 181 EXPORT_SYMBOL(mem_map_zero); 182 183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 184 185 unsigned long sparc64_kern_pri_context __read_mostly; 186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 187 unsigned long sparc64_kern_sec_context __read_mostly; 188 189 int num_kernel_image_mappings; 190 191 #ifdef CONFIG_DEBUG_DCFLUSH 192 atomic_t dcpage_flushes = ATOMIC_INIT(0); 193 #ifdef CONFIG_SMP 194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); 195 #endif 196 #endif 197 198 inline void flush_dcache_page_impl(struct page *page) 199 { 200 BUG_ON(tlb_type == hypervisor); 201 #ifdef CONFIG_DEBUG_DCFLUSH 202 atomic_inc(&dcpage_flushes); 203 #endif 204 205 #ifdef DCACHE_ALIASING_POSSIBLE 206 __flush_dcache_page(page_address(page), 207 ((tlb_type == spitfire) && 208 page_mapping_file(page) != NULL)); 209 #else 210 if (page_mapping_file(page) != NULL && 211 tlb_type == spitfire) 212 __flush_icache_page(__pa(page_address(page))); 213 #endif 214 } 215 216 #define PG_dcache_dirty PG_arch_1 217 #define PG_dcache_cpu_shift 32UL 218 #define PG_dcache_cpu_mask \ 219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) 220 221 #define dcache_dirty_cpu(page) \ 222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) 223 224 static inline void set_dcache_dirty(struct page *page, int this_cpu) 225 { 226 unsigned long mask = this_cpu; 227 unsigned long non_cpu_bits; 228 229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); 230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); 231 232 __asm__ __volatile__("1:\n\t" 233 "ldx [%2], %%g7\n\t" 234 "and %%g7, %1, %%g1\n\t" 235 "or %%g1, %0, %%g1\n\t" 236 "casx [%2], %%g7, %%g1\n\t" 237 "cmp %%g7, %%g1\n\t" 238 "bne,pn %%xcc, 1b\n\t" 239 " nop" 240 : /* no outputs */ 241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) 242 : "g1", "g7"); 243 } 244 245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) 246 { 247 unsigned long mask = (1UL << PG_dcache_dirty); 248 249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n" 250 "1:\n\t" 251 "ldx [%2], %%g7\n\t" 252 "srlx %%g7, %4, %%g1\n\t" 253 "and %%g1, %3, %%g1\n\t" 254 "cmp %%g1, %0\n\t" 255 "bne,pn %%icc, 2f\n\t" 256 " andn %%g7, %1, %%g1\n\t" 257 "casx [%2], %%g7, %%g1\n\t" 258 "cmp %%g7, %%g1\n\t" 259 "bne,pn %%xcc, 1b\n\t" 260 " nop\n" 261 "2:" 262 : /* no outputs */ 263 : "r" (cpu), "r" (mask), "r" (&page->flags), 264 "i" (PG_dcache_cpu_mask), 265 "i" (PG_dcache_cpu_shift) 266 : "g1", "g7"); 267 } 268 269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) 270 { 271 unsigned long tsb_addr = (unsigned long) ent; 272 273 if (tlb_type == cheetah_plus || tlb_type == hypervisor) 274 tsb_addr = __pa(tsb_addr); 275 276 __tsb_insert(tsb_addr, tag, pte); 277 } 278 279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly; 280 281 static void flush_dcache(unsigned long pfn) 282 { 283 struct page *page; 284 285 page = pfn_to_page(pfn); 286 if (page) { 287 unsigned long pg_flags; 288 289 pg_flags = page->flags; 290 if (pg_flags & (1UL << PG_dcache_dirty)) { 291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 292 PG_dcache_cpu_mask); 293 int this_cpu = get_cpu(); 294 295 /* This is just to optimize away some function calls 296 * in the SMP case. 297 */ 298 if (cpu == this_cpu) 299 flush_dcache_page_impl(page); 300 else 301 smp_flush_dcache_page_impl(page, cpu); 302 303 clear_dcache_dirty_cpu(page, cpu); 304 305 put_cpu(); 306 } 307 } 308 } 309 310 /* mm->context.lock must be held */ 311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, 312 unsigned long tsb_hash_shift, unsigned long address, 313 unsigned long tte) 314 { 315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; 316 unsigned long tag; 317 318 if (unlikely(!tsb)) 319 return; 320 321 tsb += ((address >> tsb_hash_shift) & 322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); 323 tag = (address >> 22UL); 324 tsb_insert(tsb, tag, tte); 325 } 326 327 #ifdef CONFIG_HUGETLB_PAGE 328 static void __init add_huge_page_size(unsigned long size) 329 { 330 unsigned int order; 331 332 if (size_to_hstate(size)) 333 return; 334 335 order = ilog2(size) - PAGE_SHIFT; 336 hugetlb_add_hstate(order); 337 } 338 339 static int __init hugetlbpage_init(void) 340 { 341 add_huge_page_size(1UL << HPAGE_64K_SHIFT); 342 add_huge_page_size(1UL << HPAGE_SHIFT); 343 add_huge_page_size(1UL << HPAGE_256MB_SHIFT); 344 add_huge_page_size(1UL << HPAGE_2GB_SHIFT); 345 346 return 0; 347 } 348 349 arch_initcall(hugetlbpage_init); 350 351 static void __init pud_huge_patch(void) 352 { 353 struct pud_huge_patch_entry *p; 354 unsigned long addr; 355 356 p = &__pud_huge_patch; 357 addr = p->addr; 358 *(unsigned int *)addr = p->insn; 359 360 __asm__ __volatile__("flush %0" : : "r" (addr)); 361 } 362 363 static int __init setup_hugepagesz(char *string) 364 { 365 unsigned long long hugepage_size; 366 unsigned int hugepage_shift; 367 unsigned short hv_pgsz_idx; 368 unsigned int hv_pgsz_mask; 369 int rc = 0; 370 371 hugepage_size = memparse(string, &string); 372 hugepage_shift = ilog2(hugepage_size); 373 374 switch (hugepage_shift) { 375 case HPAGE_16GB_SHIFT: 376 hv_pgsz_mask = HV_PGSZ_MASK_16GB; 377 hv_pgsz_idx = HV_PGSZ_IDX_16GB; 378 pud_huge_patch(); 379 break; 380 case HPAGE_2GB_SHIFT: 381 hv_pgsz_mask = HV_PGSZ_MASK_2GB; 382 hv_pgsz_idx = HV_PGSZ_IDX_2GB; 383 break; 384 case HPAGE_256MB_SHIFT: 385 hv_pgsz_mask = HV_PGSZ_MASK_256MB; 386 hv_pgsz_idx = HV_PGSZ_IDX_256MB; 387 break; 388 case HPAGE_SHIFT: 389 hv_pgsz_mask = HV_PGSZ_MASK_4MB; 390 hv_pgsz_idx = HV_PGSZ_IDX_4MB; 391 break; 392 case HPAGE_64K_SHIFT: 393 hv_pgsz_mask = HV_PGSZ_MASK_64K; 394 hv_pgsz_idx = HV_PGSZ_IDX_64K; 395 break; 396 default: 397 hv_pgsz_mask = 0; 398 } 399 400 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) { 401 hugetlb_bad_size(); 402 pr_err("hugepagesz=%llu not supported by MMU.\n", 403 hugepage_size); 404 goto out; 405 } 406 407 add_huge_page_size(hugepage_size); 408 rc = 1; 409 410 out: 411 return rc; 412 } 413 __setup("hugepagesz=", setup_hugepagesz); 414 #endif /* CONFIG_HUGETLB_PAGE */ 415 416 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) 417 { 418 struct mm_struct *mm; 419 unsigned long flags; 420 bool is_huge_tsb; 421 pte_t pte = *ptep; 422 423 if (tlb_type != hypervisor) { 424 unsigned long pfn = pte_pfn(pte); 425 426 if (pfn_valid(pfn)) 427 flush_dcache(pfn); 428 } 429 430 mm = vma->vm_mm; 431 432 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ 433 if (!pte_accessible(mm, pte)) 434 return; 435 436 spin_lock_irqsave(&mm->context.lock, flags); 437 438 is_huge_tsb = false; 439 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 440 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) { 441 unsigned long hugepage_size = PAGE_SIZE; 442 443 if (is_vm_hugetlb_page(vma)) 444 hugepage_size = huge_page_size(hstate_vma(vma)); 445 446 if (hugepage_size >= PUD_SIZE) { 447 unsigned long mask = 0x1ffc00000UL; 448 449 /* Transfer bits [32:22] from address to resolve 450 * at 4M granularity. 451 */ 452 pte_val(pte) &= ~mask; 453 pte_val(pte) |= (address & mask); 454 } else if (hugepage_size >= PMD_SIZE) { 455 /* We are fabricating 8MB pages using 4MB 456 * real hw pages. 457 */ 458 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); 459 } 460 461 if (hugepage_size >= PMD_SIZE) { 462 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, 463 REAL_HPAGE_SHIFT, address, pte_val(pte)); 464 is_huge_tsb = true; 465 } 466 } 467 #endif 468 if (!is_huge_tsb) 469 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, 470 address, pte_val(pte)); 471 472 spin_unlock_irqrestore(&mm->context.lock, flags); 473 } 474 475 void flush_dcache_page(struct page *page) 476 { 477 struct address_space *mapping; 478 int this_cpu; 479 480 if (tlb_type == hypervisor) 481 return; 482 483 /* Do not bother with the expensive D-cache flush if it 484 * is merely the zero page. The 'bigcore' testcase in GDB 485 * causes this case to run millions of times. 486 */ 487 if (page == ZERO_PAGE(0)) 488 return; 489 490 this_cpu = get_cpu(); 491 492 mapping = page_mapping_file(page); 493 if (mapping && !mapping_mapped(mapping)) { 494 int dirty = test_bit(PG_dcache_dirty, &page->flags); 495 if (dirty) { 496 int dirty_cpu = dcache_dirty_cpu(page); 497 498 if (dirty_cpu == this_cpu) 499 goto out; 500 smp_flush_dcache_page_impl(page, dirty_cpu); 501 } 502 set_dcache_dirty(page, this_cpu); 503 } else { 504 /* We could delay the flush for the !page_mapping 505 * case too. But that case is for exec env/arg 506 * pages and those are %99 certainly going to get 507 * faulted into the tlb (and thus flushed) anyways. 508 */ 509 flush_dcache_page_impl(page); 510 } 511 512 out: 513 put_cpu(); 514 } 515 EXPORT_SYMBOL(flush_dcache_page); 516 517 void __kprobes flush_icache_range(unsigned long start, unsigned long end) 518 { 519 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ 520 if (tlb_type == spitfire) { 521 unsigned long kaddr; 522 523 /* This code only runs on Spitfire cpus so this is 524 * why we can assume _PAGE_PADDR_4U. 525 */ 526 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { 527 unsigned long paddr, mask = _PAGE_PADDR_4U; 528 529 if (kaddr >= PAGE_OFFSET) 530 paddr = kaddr & mask; 531 else { 532 pgd_t *pgdp = pgd_offset_k(kaddr); 533 pud_t *pudp = pud_offset(pgdp, kaddr); 534 pmd_t *pmdp = pmd_offset(pudp, kaddr); 535 pte_t *ptep = pte_offset_kernel(pmdp, kaddr); 536 537 paddr = pte_val(*ptep) & mask; 538 } 539 __flush_icache_page(paddr); 540 } 541 } 542 } 543 EXPORT_SYMBOL(flush_icache_range); 544 545 void mmu_info(struct seq_file *m) 546 { 547 static const char *pgsz_strings[] = { 548 "8K", "64K", "512K", "4MB", "32MB", 549 "256MB", "2GB", "16GB", 550 }; 551 int i, printed; 552 553 if (tlb_type == cheetah) 554 seq_printf(m, "MMU Type\t: Cheetah\n"); 555 else if (tlb_type == cheetah_plus) 556 seq_printf(m, "MMU Type\t: Cheetah+\n"); 557 else if (tlb_type == spitfire) 558 seq_printf(m, "MMU Type\t: Spitfire\n"); 559 else if (tlb_type == hypervisor) 560 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); 561 else 562 seq_printf(m, "MMU Type\t: ???\n"); 563 564 seq_printf(m, "MMU PGSZs\t: "); 565 printed = 0; 566 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { 567 if (cpu_pgsz_mask & (1UL << i)) { 568 seq_printf(m, "%s%s", 569 printed ? "," : "", pgsz_strings[i]); 570 printed++; 571 } 572 } 573 seq_putc(m, '\n'); 574 575 #ifdef CONFIG_DEBUG_DCFLUSH 576 seq_printf(m, "DCPageFlushes\t: %d\n", 577 atomic_read(&dcpage_flushes)); 578 #ifdef CONFIG_SMP 579 seq_printf(m, "DCPageFlushesXC\t: %d\n", 580 atomic_read(&dcpage_flushes_xcall)); 581 #endif /* CONFIG_SMP */ 582 #endif /* CONFIG_DEBUG_DCFLUSH */ 583 } 584 585 struct linux_prom_translation prom_trans[512] __read_mostly; 586 unsigned int prom_trans_ents __read_mostly; 587 588 unsigned long kern_locked_tte_data; 589 590 /* The obp translations are saved based on 8k pagesize, since obp can 591 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 592 * HI_OBP_ADDRESS range are handled in ktlb.S. 593 */ 594 static inline int in_obp_range(unsigned long vaddr) 595 { 596 return (vaddr >= LOW_OBP_ADDRESS && 597 vaddr < HI_OBP_ADDRESS); 598 } 599 600 static int cmp_ptrans(const void *a, const void *b) 601 { 602 const struct linux_prom_translation *x = a, *y = b; 603 604 if (x->virt > y->virt) 605 return 1; 606 if (x->virt < y->virt) 607 return -1; 608 return 0; 609 } 610 611 /* Read OBP translations property into 'prom_trans[]'. */ 612 static void __init read_obp_translations(void) 613 { 614 int n, node, ents, first, last, i; 615 616 node = prom_finddevice("/virtual-memory"); 617 n = prom_getproplen(node, "translations"); 618 if (unlikely(n == 0 || n == -1)) { 619 prom_printf("prom_mappings: Couldn't get size.\n"); 620 prom_halt(); 621 } 622 if (unlikely(n > sizeof(prom_trans))) { 623 prom_printf("prom_mappings: Size %d is too big.\n", n); 624 prom_halt(); 625 } 626 627 if ((n = prom_getproperty(node, "translations", 628 (char *)&prom_trans[0], 629 sizeof(prom_trans))) == -1) { 630 prom_printf("prom_mappings: Couldn't get property.\n"); 631 prom_halt(); 632 } 633 634 n = n / sizeof(struct linux_prom_translation); 635 636 ents = n; 637 638 sort(prom_trans, ents, sizeof(struct linux_prom_translation), 639 cmp_ptrans, NULL); 640 641 /* Now kick out all the non-OBP entries. */ 642 for (i = 0; i < ents; i++) { 643 if (in_obp_range(prom_trans[i].virt)) 644 break; 645 } 646 first = i; 647 for (; i < ents; i++) { 648 if (!in_obp_range(prom_trans[i].virt)) 649 break; 650 } 651 last = i; 652 653 for (i = 0; i < (last - first); i++) { 654 struct linux_prom_translation *src = &prom_trans[i + first]; 655 struct linux_prom_translation *dest = &prom_trans[i]; 656 657 *dest = *src; 658 } 659 for (; i < ents; i++) { 660 struct linux_prom_translation *dest = &prom_trans[i]; 661 dest->virt = dest->size = dest->data = 0x0UL; 662 } 663 664 prom_trans_ents = last - first; 665 666 if (tlb_type == spitfire) { 667 /* Clear diag TTE bits. */ 668 for (i = 0; i < prom_trans_ents; i++) 669 prom_trans[i].data &= ~0x0003fe0000000000UL; 670 } 671 672 /* Force execute bit on. */ 673 for (i = 0; i < prom_trans_ents; i++) 674 prom_trans[i].data |= (tlb_type == hypervisor ? 675 _PAGE_EXEC_4V : _PAGE_EXEC_4U); 676 } 677 678 static void __init hypervisor_tlb_lock(unsigned long vaddr, 679 unsigned long pte, 680 unsigned long mmu) 681 { 682 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); 683 684 if (ret != 0) { 685 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " 686 "errors with %lx\n", vaddr, 0, pte, mmu, ret); 687 prom_halt(); 688 } 689 } 690 691 static unsigned long kern_large_tte(unsigned long paddr); 692 693 static void __init remap_kernel(void) 694 { 695 unsigned long phys_page, tte_vaddr, tte_data; 696 int i, tlb_ent = sparc64_highest_locked_tlbent(); 697 698 tte_vaddr = (unsigned long) KERNBASE; 699 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 700 tte_data = kern_large_tte(phys_page); 701 702 kern_locked_tte_data = tte_data; 703 704 /* Now lock us into the TLBs via Hypervisor or OBP. */ 705 if (tlb_type == hypervisor) { 706 for (i = 0; i < num_kernel_image_mappings; i++) { 707 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); 708 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); 709 tte_vaddr += 0x400000; 710 tte_data += 0x400000; 711 } 712 } else { 713 for (i = 0; i < num_kernel_image_mappings; i++) { 714 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); 715 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); 716 tte_vaddr += 0x400000; 717 tte_data += 0x400000; 718 } 719 sparc64_highest_unlocked_tlb_ent = tlb_ent - i; 720 } 721 if (tlb_type == cheetah_plus) { 722 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 723 CTX_CHEETAH_PLUS_NUC); 724 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 725 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 726 } 727 } 728 729 730 static void __init inherit_prom_mappings(void) 731 { 732 /* Now fixup OBP's idea about where we really are mapped. */ 733 printk("Remapping the kernel... "); 734 remap_kernel(); 735 printk("done.\n"); 736 } 737 738 void prom_world(int enter) 739 { 740 if (!enter) 741 set_fs(get_fs()); 742 743 __asm__ __volatile__("flushw"); 744 } 745 746 void __flush_dcache_range(unsigned long start, unsigned long end) 747 { 748 unsigned long va; 749 750 if (tlb_type == spitfire) { 751 int n = 0; 752 753 for (va = start; va < end; va += 32) { 754 spitfire_put_dcache_tag(va & 0x3fe0, 0x0); 755 if (++n >= 512) 756 break; 757 } 758 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 759 start = __pa(start); 760 end = __pa(end); 761 for (va = start; va < end; va += 32) 762 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 763 "membar #Sync" 764 : /* no outputs */ 765 : "r" (va), 766 "i" (ASI_DCACHE_INVALIDATE)); 767 } 768 } 769 EXPORT_SYMBOL(__flush_dcache_range); 770 771 /* get_new_mmu_context() uses "cache + 1". */ 772 DEFINE_SPINLOCK(ctx_alloc_lock); 773 unsigned long tlb_context_cache = CTX_FIRST_VERSION; 774 #define MAX_CTX_NR (1UL << CTX_NR_BITS) 775 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) 776 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); 777 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0}; 778 779 static void mmu_context_wrap(void) 780 { 781 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK; 782 unsigned long new_ver, new_ctx, old_ctx; 783 struct mm_struct *mm; 784 int cpu; 785 786 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS); 787 788 /* Reserve kernel context */ 789 set_bit(0, mmu_context_bmap); 790 791 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION; 792 if (unlikely(new_ver == 0)) 793 new_ver = CTX_FIRST_VERSION; 794 tlb_context_cache = new_ver; 795 796 /* 797 * Make sure that any new mm that are added into per_cpu_secondary_mm, 798 * are going to go through get_new_mmu_context() path. 799 */ 800 mb(); 801 802 /* 803 * Updated versions to current on those CPUs that had valid secondary 804 * contexts 805 */ 806 for_each_online_cpu(cpu) { 807 /* 808 * If a new mm is stored after we took this mm from the array, 809 * it will go into get_new_mmu_context() path, because we 810 * already bumped the version in tlb_context_cache. 811 */ 812 mm = per_cpu(per_cpu_secondary_mm, cpu); 813 814 if (unlikely(!mm || mm == &init_mm)) 815 continue; 816 817 old_ctx = mm->context.sparc64_ctx_val; 818 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) { 819 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver; 820 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap); 821 mm->context.sparc64_ctx_val = new_ctx; 822 } 823 } 824 } 825 826 /* Caller does TLB context flushing on local CPU if necessary. 827 * The caller also ensures that CTX_VALID(mm->context) is false. 828 * 829 * We must be careful about boundary cases so that we never 830 * let the user have CTX 0 (nucleus) or we ever use a CTX 831 * version of zero (and thus NO_CONTEXT would not be caught 832 * by version mis-match tests in mmu_context.h). 833 * 834 * Always invoked with interrupts disabled. 835 */ 836 void get_new_mmu_context(struct mm_struct *mm) 837 { 838 unsigned long ctx, new_ctx; 839 unsigned long orig_pgsz_bits; 840 841 spin_lock(&ctx_alloc_lock); 842 retry: 843 /* wrap might have happened, test again if our context became valid */ 844 if (unlikely(CTX_VALID(mm->context))) 845 goto out; 846 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 847 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 848 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 849 if (new_ctx >= (1 << CTX_NR_BITS)) { 850 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 851 if (new_ctx >= ctx) { 852 mmu_context_wrap(); 853 goto retry; 854 } 855 } 856 if (mm->context.sparc64_ctx_val) 857 cpumask_clear(mm_cpumask(mm)); 858 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); 859 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); 860 tlb_context_cache = new_ctx; 861 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 862 out: 863 spin_unlock(&ctx_alloc_lock); 864 } 865 866 static int numa_enabled = 1; 867 static int numa_debug; 868 869 static int __init early_numa(char *p) 870 { 871 if (!p) 872 return 0; 873 874 if (strstr(p, "off")) 875 numa_enabled = 0; 876 877 if (strstr(p, "debug")) 878 numa_debug = 1; 879 880 return 0; 881 } 882 early_param("numa", early_numa); 883 884 #define numadbg(f, a...) \ 885 do { if (numa_debug) \ 886 printk(KERN_INFO f, ## a); \ 887 } while (0) 888 889 static void __init find_ramdisk(unsigned long phys_base) 890 { 891 #ifdef CONFIG_BLK_DEV_INITRD 892 if (sparc_ramdisk_image || sparc_ramdisk_image64) { 893 unsigned long ramdisk_image; 894 895 /* Older versions of the bootloader only supported a 896 * 32-bit physical address for the ramdisk image 897 * location, stored at sparc_ramdisk_image. Newer 898 * SILO versions set sparc_ramdisk_image to zero and 899 * provide a full 64-bit physical address at 900 * sparc_ramdisk_image64. 901 */ 902 ramdisk_image = sparc_ramdisk_image; 903 if (!ramdisk_image) 904 ramdisk_image = sparc_ramdisk_image64; 905 906 /* Another bootloader quirk. The bootloader normalizes 907 * the physical address to KERNBASE, so we have to 908 * factor that back out and add in the lowest valid 909 * physical page address to get the true physical address. 910 */ 911 ramdisk_image -= KERNBASE; 912 ramdisk_image += phys_base; 913 914 numadbg("Found ramdisk at physical address 0x%lx, size %u\n", 915 ramdisk_image, sparc_ramdisk_size); 916 917 initrd_start = ramdisk_image; 918 initrd_end = ramdisk_image + sparc_ramdisk_size; 919 920 memblock_reserve(initrd_start, sparc_ramdisk_size); 921 922 initrd_start += PAGE_OFFSET; 923 initrd_end += PAGE_OFFSET; 924 } 925 #endif 926 } 927 928 struct node_mem_mask { 929 unsigned long mask; 930 unsigned long match; 931 }; 932 static struct node_mem_mask node_masks[MAX_NUMNODES]; 933 static int num_node_masks; 934 935 #ifdef CONFIG_NEED_MULTIPLE_NODES 936 937 struct mdesc_mlgroup { 938 u64 node; 939 u64 latency; 940 u64 match; 941 u64 mask; 942 }; 943 944 static struct mdesc_mlgroup *mlgroups; 945 static int num_mlgroups; 946 947 int numa_cpu_lookup_table[NR_CPUS]; 948 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; 949 950 struct mdesc_mblock { 951 u64 base; 952 u64 size; 953 u64 offset; /* RA-to-PA */ 954 }; 955 static struct mdesc_mblock *mblocks; 956 static int num_mblocks; 957 958 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr) 959 { 960 struct mdesc_mblock *m = NULL; 961 int i; 962 963 for (i = 0; i < num_mblocks; i++) { 964 m = &mblocks[i]; 965 966 if (addr >= m->base && 967 addr < (m->base + m->size)) { 968 break; 969 } 970 } 971 972 return m; 973 } 974 975 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid) 976 { 977 int prev_nid, new_nid; 978 979 prev_nid = -1; 980 for ( ; start < end; start += PAGE_SIZE) { 981 for (new_nid = 0; new_nid < num_node_masks; new_nid++) { 982 struct node_mem_mask *p = &node_masks[new_nid]; 983 984 if ((start & p->mask) == p->match) { 985 if (prev_nid == -1) 986 prev_nid = new_nid; 987 break; 988 } 989 } 990 991 if (new_nid == num_node_masks) { 992 prev_nid = 0; 993 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.", 994 start); 995 break; 996 } 997 998 if (prev_nid != new_nid) 999 break; 1000 } 1001 *nid = prev_nid; 1002 1003 return start > end ? end : start; 1004 } 1005 1006 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid) 1007 { 1008 u64 ret_end, pa_start, m_mask, m_match, m_end; 1009 struct mdesc_mblock *mblock; 1010 int _nid, i; 1011 1012 if (tlb_type != hypervisor) 1013 return memblock_nid_range_sun4u(start, end, nid); 1014 1015 mblock = addr_to_mblock(start); 1016 if (!mblock) { 1017 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]", 1018 start); 1019 1020 _nid = 0; 1021 ret_end = end; 1022 goto done; 1023 } 1024 1025 pa_start = start + mblock->offset; 1026 m_match = 0; 1027 m_mask = 0; 1028 1029 for (_nid = 0; _nid < num_node_masks; _nid++) { 1030 struct node_mem_mask *const m = &node_masks[_nid]; 1031 1032 if ((pa_start & m->mask) == m->match) { 1033 m_match = m->match; 1034 m_mask = m->mask; 1035 break; 1036 } 1037 } 1038 1039 if (num_node_masks == _nid) { 1040 /* We could not find NUMA group, so default to 0, but lets 1041 * search for latency group, so we could calculate the correct 1042 * end address that we return 1043 */ 1044 _nid = 0; 1045 1046 for (i = 0; i < num_mlgroups; i++) { 1047 struct mdesc_mlgroup *const m = &mlgroups[i]; 1048 1049 if ((pa_start & m->mask) == m->match) { 1050 m_match = m->match; 1051 m_mask = m->mask; 1052 break; 1053 } 1054 } 1055 1056 if (i == num_mlgroups) { 1057 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]", 1058 start); 1059 1060 ret_end = end; 1061 goto done; 1062 } 1063 } 1064 1065 /* 1066 * Each latency group has match and mask, and each memory block has an 1067 * offset. An address belongs to a latency group if its address matches 1068 * the following formula: ((addr + offset) & mask) == match 1069 * It is, however, slow to check every single page if it matches a 1070 * particular latency group. As optimization we calculate end value by 1071 * using bit arithmetics. 1072 */ 1073 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset; 1074 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1); 1075 ret_end = m_end > end ? end : m_end; 1076 1077 done: 1078 *nid = _nid; 1079 return ret_end; 1080 } 1081 #endif 1082 1083 /* This must be invoked after performing all of the necessary 1084 * memblock_set_node() calls for 'nid'. We need to be able to get 1085 * correct data from get_pfn_range_for_nid(). 1086 */ 1087 static void __init allocate_node_data(int nid) 1088 { 1089 struct pglist_data *p; 1090 unsigned long start_pfn, end_pfn; 1091 #ifdef CONFIG_NEED_MULTIPLE_NODES 1092 unsigned long paddr; 1093 1094 paddr = memblock_phys_alloc_try_nid(sizeof(struct pglist_data), 1095 SMP_CACHE_BYTES, nid); 1096 if (!paddr) { 1097 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); 1098 prom_halt(); 1099 } 1100 NODE_DATA(nid) = __va(paddr); 1101 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); 1102 1103 NODE_DATA(nid)->node_id = nid; 1104 #endif 1105 1106 p = NODE_DATA(nid); 1107 1108 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); 1109 p->node_start_pfn = start_pfn; 1110 p->node_spanned_pages = end_pfn - start_pfn; 1111 } 1112 1113 static void init_node_masks_nonnuma(void) 1114 { 1115 #ifdef CONFIG_NEED_MULTIPLE_NODES 1116 int i; 1117 #endif 1118 1119 numadbg("Initializing tables for non-numa.\n"); 1120 1121 node_masks[0].mask = 0; 1122 node_masks[0].match = 0; 1123 num_node_masks = 1; 1124 1125 #ifdef CONFIG_NEED_MULTIPLE_NODES 1126 for (i = 0; i < NR_CPUS; i++) 1127 numa_cpu_lookup_table[i] = 0; 1128 1129 cpumask_setall(&numa_cpumask_lookup_table[0]); 1130 #endif 1131 } 1132 1133 #ifdef CONFIG_NEED_MULTIPLE_NODES 1134 struct pglist_data *node_data[MAX_NUMNODES]; 1135 1136 EXPORT_SYMBOL(numa_cpu_lookup_table); 1137 EXPORT_SYMBOL(numa_cpumask_lookup_table); 1138 EXPORT_SYMBOL(node_data); 1139 1140 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, 1141 u32 cfg_handle) 1142 { 1143 u64 arc; 1144 1145 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { 1146 u64 target = mdesc_arc_target(md, arc); 1147 const u64 *val; 1148 1149 val = mdesc_get_property(md, target, 1150 "cfg-handle", NULL); 1151 if (val && *val == cfg_handle) 1152 return 0; 1153 } 1154 return -ENODEV; 1155 } 1156 1157 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, 1158 u32 cfg_handle) 1159 { 1160 u64 arc, candidate, best_latency = ~(u64)0; 1161 1162 candidate = MDESC_NODE_NULL; 1163 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1164 u64 target = mdesc_arc_target(md, arc); 1165 const char *name = mdesc_node_name(md, target); 1166 const u64 *val; 1167 1168 if (strcmp(name, "pio-latency-group")) 1169 continue; 1170 1171 val = mdesc_get_property(md, target, "latency", NULL); 1172 if (!val) 1173 continue; 1174 1175 if (*val < best_latency) { 1176 candidate = target; 1177 best_latency = *val; 1178 } 1179 } 1180 1181 if (candidate == MDESC_NODE_NULL) 1182 return -ENODEV; 1183 1184 return scan_pio_for_cfg_handle(md, candidate, cfg_handle); 1185 } 1186 1187 int of_node_to_nid(struct device_node *dp) 1188 { 1189 const struct linux_prom64_registers *regs; 1190 struct mdesc_handle *md; 1191 u32 cfg_handle; 1192 int count, nid; 1193 u64 grp; 1194 1195 /* This is the right thing to do on currently supported 1196 * SUN4U NUMA platforms as well, as the PCI controller does 1197 * not sit behind any particular memory controller. 1198 */ 1199 if (!mlgroups) 1200 return -1; 1201 1202 regs = of_get_property(dp, "reg", NULL); 1203 if (!regs) 1204 return -1; 1205 1206 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; 1207 1208 md = mdesc_grab(); 1209 1210 count = 0; 1211 nid = -1; 1212 mdesc_for_each_node_by_name(md, grp, "group") { 1213 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { 1214 nid = count; 1215 break; 1216 } 1217 count++; 1218 } 1219 1220 mdesc_release(md); 1221 1222 return nid; 1223 } 1224 1225 static void __init add_node_ranges(void) 1226 { 1227 struct memblock_region *reg; 1228 unsigned long prev_max; 1229 1230 memblock_resized: 1231 prev_max = memblock.memory.max; 1232 1233 for_each_memblock(memory, reg) { 1234 unsigned long size = reg->size; 1235 unsigned long start, end; 1236 1237 start = reg->base; 1238 end = start + size; 1239 while (start < end) { 1240 unsigned long this_end; 1241 int nid; 1242 1243 this_end = memblock_nid_range(start, end, &nid); 1244 1245 numadbg("Setting memblock NUMA node nid[%d] " 1246 "start[%lx] end[%lx]\n", 1247 nid, start, this_end); 1248 1249 memblock_set_node(start, this_end - start, 1250 &memblock.memory, nid); 1251 if (memblock.memory.max != prev_max) 1252 goto memblock_resized; 1253 start = this_end; 1254 } 1255 } 1256 } 1257 1258 static int __init grab_mlgroups(struct mdesc_handle *md) 1259 { 1260 unsigned long paddr; 1261 int count = 0; 1262 u64 node; 1263 1264 mdesc_for_each_node_by_name(md, node, "memory-latency-group") 1265 count++; 1266 if (!count) 1267 return -ENOENT; 1268 1269 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup), 1270 SMP_CACHE_BYTES); 1271 if (!paddr) 1272 return -ENOMEM; 1273 1274 mlgroups = __va(paddr); 1275 num_mlgroups = count; 1276 1277 count = 0; 1278 mdesc_for_each_node_by_name(md, node, "memory-latency-group") { 1279 struct mdesc_mlgroup *m = &mlgroups[count++]; 1280 const u64 *val; 1281 1282 m->node = node; 1283 1284 val = mdesc_get_property(md, node, "latency", NULL); 1285 m->latency = *val; 1286 val = mdesc_get_property(md, node, "address-match", NULL); 1287 m->match = *val; 1288 val = mdesc_get_property(md, node, "address-mask", NULL); 1289 m->mask = *val; 1290 1291 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " 1292 "match[%llx] mask[%llx]\n", 1293 count - 1, m->node, m->latency, m->match, m->mask); 1294 } 1295 1296 return 0; 1297 } 1298 1299 static int __init grab_mblocks(struct mdesc_handle *md) 1300 { 1301 unsigned long paddr; 1302 int count = 0; 1303 u64 node; 1304 1305 mdesc_for_each_node_by_name(md, node, "mblock") 1306 count++; 1307 if (!count) 1308 return -ENOENT; 1309 1310 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock), 1311 SMP_CACHE_BYTES); 1312 if (!paddr) 1313 return -ENOMEM; 1314 1315 mblocks = __va(paddr); 1316 num_mblocks = count; 1317 1318 count = 0; 1319 mdesc_for_each_node_by_name(md, node, "mblock") { 1320 struct mdesc_mblock *m = &mblocks[count++]; 1321 const u64 *val; 1322 1323 val = mdesc_get_property(md, node, "base", NULL); 1324 m->base = *val; 1325 val = mdesc_get_property(md, node, "size", NULL); 1326 m->size = *val; 1327 val = mdesc_get_property(md, node, 1328 "address-congruence-offset", NULL); 1329 1330 /* The address-congruence-offset property is optional. 1331 * Explicity zero it be identifty this. 1332 */ 1333 if (val) 1334 m->offset = *val; 1335 else 1336 m->offset = 0UL; 1337 1338 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", 1339 count - 1, m->base, m->size, m->offset); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, 1346 u64 grp, cpumask_t *mask) 1347 { 1348 u64 arc; 1349 1350 cpumask_clear(mask); 1351 1352 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { 1353 u64 target = mdesc_arc_target(md, arc); 1354 const char *name = mdesc_node_name(md, target); 1355 const u64 *id; 1356 1357 if (strcmp(name, "cpu")) 1358 continue; 1359 id = mdesc_get_property(md, target, "id", NULL); 1360 if (*id < nr_cpu_ids) 1361 cpumask_set_cpu(*id, mask); 1362 } 1363 } 1364 1365 static struct mdesc_mlgroup * __init find_mlgroup(u64 node) 1366 { 1367 int i; 1368 1369 for (i = 0; i < num_mlgroups; i++) { 1370 struct mdesc_mlgroup *m = &mlgroups[i]; 1371 if (m->node == node) 1372 return m; 1373 } 1374 return NULL; 1375 } 1376 1377 int __node_distance(int from, int to) 1378 { 1379 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { 1380 pr_warn("Returning default NUMA distance value for %d->%d\n", 1381 from, to); 1382 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; 1383 } 1384 return numa_latency[from][to]; 1385 } 1386 EXPORT_SYMBOL(__node_distance); 1387 1388 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) 1389 { 1390 int i; 1391 1392 for (i = 0; i < MAX_NUMNODES; i++) { 1393 struct node_mem_mask *n = &node_masks[i]; 1394 1395 if ((grp->mask == n->mask) && (grp->match == n->match)) 1396 break; 1397 } 1398 return i; 1399 } 1400 1401 static void __init find_numa_latencies_for_group(struct mdesc_handle *md, 1402 u64 grp, int index) 1403 { 1404 u64 arc; 1405 1406 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1407 int tnode; 1408 u64 target = mdesc_arc_target(md, arc); 1409 struct mdesc_mlgroup *m = find_mlgroup(target); 1410 1411 if (!m) 1412 continue; 1413 tnode = find_best_numa_node_for_mlgroup(m); 1414 if (tnode == MAX_NUMNODES) 1415 continue; 1416 numa_latency[index][tnode] = m->latency; 1417 } 1418 } 1419 1420 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, 1421 int index) 1422 { 1423 struct mdesc_mlgroup *candidate = NULL; 1424 u64 arc, best_latency = ~(u64)0; 1425 struct node_mem_mask *n; 1426 1427 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1428 u64 target = mdesc_arc_target(md, arc); 1429 struct mdesc_mlgroup *m = find_mlgroup(target); 1430 if (!m) 1431 continue; 1432 if (m->latency < best_latency) { 1433 candidate = m; 1434 best_latency = m->latency; 1435 } 1436 } 1437 if (!candidate) 1438 return -ENOENT; 1439 1440 if (num_node_masks != index) { 1441 printk(KERN_ERR "Inconsistent NUMA state, " 1442 "index[%d] != num_node_masks[%d]\n", 1443 index, num_node_masks); 1444 return -EINVAL; 1445 } 1446 1447 n = &node_masks[num_node_masks++]; 1448 1449 n->mask = candidate->mask; 1450 n->match = candidate->match; 1451 1452 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n", 1453 index, n->mask, n->match, candidate->latency); 1454 1455 return 0; 1456 } 1457 1458 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, 1459 int index) 1460 { 1461 cpumask_t mask; 1462 int cpu; 1463 1464 numa_parse_mdesc_group_cpus(md, grp, &mask); 1465 1466 for_each_cpu(cpu, &mask) 1467 numa_cpu_lookup_table[cpu] = index; 1468 cpumask_copy(&numa_cpumask_lookup_table[index], &mask); 1469 1470 if (numa_debug) { 1471 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); 1472 for_each_cpu(cpu, &mask) 1473 printk("%d ", cpu); 1474 printk("]\n"); 1475 } 1476 1477 return numa_attach_mlgroup(md, grp, index); 1478 } 1479 1480 static int __init numa_parse_mdesc(void) 1481 { 1482 struct mdesc_handle *md = mdesc_grab(); 1483 int i, j, err, count; 1484 u64 node; 1485 1486 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); 1487 if (node == MDESC_NODE_NULL) { 1488 mdesc_release(md); 1489 return -ENOENT; 1490 } 1491 1492 err = grab_mblocks(md); 1493 if (err < 0) 1494 goto out; 1495 1496 err = grab_mlgroups(md); 1497 if (err < 0) 1498 goto out; 1499 1500 count = 0; 1501 mdesc_for_each_node_by_name(md, node, "group") { 1502 err = numa_parse_mdesc_group(md, node, count); 1503 if (err < 0) 1504 break; 1505 count++; 1506 } 1507 1508 count = 0; 1509 mdesc_for_each_node_by_name(md, node, "group") { 1510 find_numa_latencies_for_group(md, node, count); 1511 count++; 1512 } 1513 1514 /* Normalize numa latency matrix according to ACPI SLIT spec. */ 1515 for (i = 0; i < MAX_NUMNODES; i++) { 1516 u64 self_latency = numa_latency[i][i]; 1517 1518 for (j = 0; j < MAX_NUMNODES; j++) { 1519 numa_latency[i][j] = 1520 (numa_latency[i][j] * LOCAL_DISTANCE) / 1521 self_latency; 1522 } 1523 } 1524 1525 add_node_ranges(); 1526 1527 for (i = 0; i < num_node_masks; i++) { 1528 allocate_node_data(i); 1529 node_set_online(i); 1530 } 1531 1532 err = 0; 1533 out: 1534 mdesc_release(md); 1535 return err; 1536 } 1537 1538 static int __init numa_parse_jbus(void) 1539 { 1540 unsigned long cpu, index; 1541 1542 /* NUMA node id is encoded in bits 36 and higher, and there is 1543 * a 1-to-1 mapping from CPU ID to NUMA node ID. 1544 */ 1545 index = 0; 1546 for_each_present_cpu(cpu) { 1547 numa_cpu_lookup_table[cpu] = index; 1548 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); 1549 node_masks[index].mask = ~((1UL << 36UL) - 1UL); 1550 node_masks[index].match = cpu << 36UL; 1551 1552 index++; 1553 } 1554 num_node_masks = index; 1555 1556 add_node_ranges(); 1557 1558 for (index = 0; index < num_node_masks; index++) { 1559 allocate_node_data(index); 1560 node_set_online(index); 1561 } 1562 1563 return 0; 1564 } 1565 1566 static int __init numa_parse_sun4u(void) 1567 { 1568 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1569 unsigned long ver; 1570 1571 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 1572 if ((ver >> 32UL) == __JALAPENO_ID || 1573 (ver >> 32UL) == __SERRANO_ID) 1574 return numa_parse_jbus(); 1575 } 1576 return -1; 1577 } 1578 1579 static int __init bootmem_init_numa(void) 1580 { 1581 int i, j; 1582 int err = -1; 1583 1584 numadbg("bootmem_init_numa()\n"); 1585 1586 /* Some sane defaults for numa latency values */ 1587 for (i = 0; i < MAX_NUMNODES; i++) { 1588 for (j = 0; j < MAX_NUMNODES; j++) 1589 numa_latency[i][j] = (i == j) ? 1590 LOCAL_DISTANCE : REMOTE_DISTANCE; 1591 } 1592 1593 if (numa_enabled) { 1594 if (tlb_type == hypervisor) 1595 err = numa_parse_mdesc(); 1596 else 1597 err = numa_parse_sun4u(); 1598 } 1599 return err; 1600 } 1601 1602 #else 1603 1604 static int bootmem_init_numa(void) 1605 { 1606 return -1; 1607 } 1608 1609 #endif 1610 1611 static void __init bootmem_init_nonnuma(void) 1612 { 1613 unsigned long top_of_ram = memblock_end_of_DRAM(); 1614 unsigned long total_ram = memblock_phys_mem_size(); 1615 1616 numadbg("bootmem_init_nonnuma()\n"); 1617 1618 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", 1619 top_of_ram, total_ram); 1620 printk(KERN_INFO "Memory hole size: %ldMB\n", 1621 (top_of_ram - total_ram) >> 20); 1622 1623 init_node_masks_nonnuma(); 1624 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0); 1625 allocate_node_data(0); 1626 node_set_online(0); 1627 } 1628 1629 static unsigned long __init bootmem_init(unsigned long phys_base) 1630 { 1631 unsigned long end_pfn; 1632 1633 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1634 max_pfn = max_low_pfn = end_pfn; 1635 min_low_pfn = (phys_base >> PAGE_SHIFT); 1636 1637 if (bootmem_init_numa() < 0) 1638 bootmem_init_nonnuma(); 1639 1640 /* Dump memblock with node info. */ 1641 memblock_dump_all(); 1642 1643 /* XXX cpu notifier XXX */ 1644 1645 sparse_memory_present_with_active_regions(MAX_NUMNODES); 1646 sparse_init(); 1647 1648 return end_pfn; 1649 } 1650 1651 static struct linux_prom64_registers pall[MAX_BANKS] __initdata; 1652 static int pall_ents __initdata; 1653 1654 static unsigned long max_phys_bits = 40; 1655 1656 bool kern_addr_valid(unsigned long addr) 1657 { 1658 pgd_t *pgd; 1659 pud_t *pud; 1660 pmd_t *pmd; 1661 pte_t *pte; 1662 1663 if ((long)addr < 0L) { 1664 unsigned long pa = __pa(addr); 1665 1666 if ((pa >> max_phys_bits) != 0UL) 1667 return false; 1668 1669 return pfn_valid(pa >> PAGE_SHIFT); 1670 } 1671 1672 if (addr >= (unsigned long) KERNBASE && 1673 addr < (unsigned long)&_end) 1674 return true; 1675 1676 pgd = pgd_offset_k(addr); 1677 if (pgd_none(*pgd)) 1678 return 0; 1679 1680 pud = pud_offset(pgd, addr); 1681 if (pud_none(*pud)) 1682 return 0; 1683 1684 if (pud_large(*pud)) 1685 return pfn_valid(pud_pfn(*pud)); 1686 1687 pmd = pmd_offset(pud, addr); 1688 if (pmd_none(*pmd)) 1689 return 0; 1690 1691 if (pmd_large(*pmd)) 1692 return pfn_valid(pmd_pfn(*pmd)); 1693 1694 pte = pte_offset_kernel(pmd, addr); 1695 if (pte_none(*pte)) 1696 return 0; 1697 1698 return pfn_valid(pte_pfn(*pte)); 1699 } 1700 EXPORT_SYMBOL(kern_addr_valid); 1701 1702 static unsigned long __ref kernel_map_hugepud(unsigned long vstart, 1703 unsigned long vend, 1704 pud_t *pud) 1705 { 1706 const unsigned long mask16gb = (1UL << 34) - 1UL; 1707 u64 pte_val = vstart; 1708 1709 /* Each PUD is 8GB */ 1710 if ((vstart & mask16gb) || 1711 (vend - vstart <= mask16gb)) { 1712 pte_val ^= kern_linear_pte_xor[2]; 1713 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; 1714 1715 return vstart + PUD_SIZE; 1716 } 1717 1718 pte_val ^= kern_linear_pte_xor[3]; 1719 pte_val |= _PAGE_PUD_HUGE; 1720 1721 vend = vstart + mask16gb + 1UL; 1722 while (vstart < vend) { 1723 pud_val(*pud) = pte_val; 1724 1725 pte_val += PUD_SIZE; 1726 vstart += PUD_SIZE; 1727 pud++; 1728 } 1729 return vstart; 1730 } 1731 1732 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, 1733 bool guard) 1734 { 1735 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) 1736 return true; 1737 1738 return false; 1739 } 1740 1741 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, 1742 unsigned long vend, 1743 pmd_t *pmd) 1744 { 1745 const unsigned long mask256mb = (1UL << 28) - 1UL; 1746 const unsigned long mask2gb = (1UL << 31) - 1UL; 1747 u64 pte_val = vstart; 1748 1749 /* Each PMD is 8MB */ 1750 if ((vstart & mask256mb) || 1751 (vend - vstart <= mask256mb)) { 1752 pte_val ^= kern_linear_pte_xor[0]; 1753 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; 1754 1755 return vstart + PMD_SIZE; 1756 } 1757 1758 if ((vstart & mask2gb) || 1759 (vend - vstart <= mask2gb)) { 1760 pte_val ^= kern_linear_pte_xor[1]; 1761 pte_val |= _PAGE_PMD_HUGE; 1762 vend = vstart + mask256mb + 1UL; 1763 } else { 1764 pte_val ^= kern_linear_pte_xor[2]; 1765 pte_val |= _PAGE_PMD_HUGE; 1766 vend = vstart + mask2gb + 1UL; 1767 } 1768 1769 while (vstart < vend) { 1770 pmd_val(*pmd) = pte_val; 1771 1772 pte_val += PMD_SIZE; 1773 vstart += PMD_SIZE; 1774 pmd++; 1775 } 1776 1777 return vstart; 1778 } 1779 1780 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, 1781 bool guard) 1782 { 1783 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) 1784 return true; 1785 1786 return false; 1787 } 1788 1789 static unsigned long __ref kernel_map_range(unsigned long pstart, 1790 unsigned long pend, pgprot_t prot, 1791 bool use_huge) 1792 { 1793 unsigned long vstart = PAGE_OFFSET + pstart; 1794 unsigned long vend = PAGE_OFFSET + pend; 1795 unsigned long alloc_bytes = 0UL; 1796 1797 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { 1798 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", 1799 vstart, vend); 1800 prom_halt(); 1801 } 1802 1803 while (vstart < vend) { 1804 unsigned long this_end, paddr = __pa(vstart); 1805 pgd_t *pgd = pgd_offset_k(vstart); 1806 pud_t *pud; 1807 pmd_t *pmd; 1808 pte_t *pte; 1809 1810 if (pgd_none(*pgd)) { 1811 pud_t *new; 1812 1813 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1814 PAGE_SIZE); 1815 alloc_bytes += PAGE_SIZE; 1816 pgd_populate(&init_mm, pgd, new); 1817 } 1818 pud = pud_offset(pgd, vstart); 1819 if (pud_none(*pud)) { 1820 pmd_t *new; 1821 1822 if (kernel_can_map_hugepud(vstart, vend, use_huge)) { 1823 vstart = kernel_map_hugepud(vstart, vend, pud); 1824 continue; 1825 } 1826 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1827 PAGE_SIZE); 1828 alloc_bytes += PAGE_SIZE; 1829 pud_populate(&init_mm, pud, new); 1830 } 1831 1832 pmd = pmd_offset(pud, vstart); 1833 if (pmd_none(*pmd)) { 1834 pte_t *new; 1835 1836 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { 1837 vstart = kernel_map_hugepmd(vstart, vend, pmd); 1838 continue; 1839 } 1840 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1841 PAGE_SIZE); 1842 alloc_bytes += PAGE_SIZE; 1843 pmd_populate_kernel(&init_mm, pmd, new); 1844 } 1845 1846 pte = pte_offset_kernel(pmd, vstart); 1847 this_end = (vstart + PMD_SIZE) & PMD_MASK; 1848 if (this_end > vend) 1849 this_end = vend; 1850 1851 while (vstart < this_end) { 1852 pte_val(*pte) = (paddr | pgprot_val(prot)); 1853 1854 vstart += PAGE_SIZE; 1855 paddr += PAGE_SIZE; 1856 pte++; 1857 } 1858 } 1859 1860 return alloc_bytes; 1861 } 1862 1863 static void __init flush_all_kernel_tsbs(void) 1864 { 1865 int i; 1866 1867 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { 1868 struct tsb *ent = &swapper_tsb[i]; 1869 1870 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1871 } 1872 #ifndef CONFIG_DEBUG_PAGEALLOC 1873 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { 1874 struct tsb *ent = &swapper_4m_tsb[i]; 1875 1876 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1877 } 1878 #endif 1879 } 1880 1881 extern unsigned int kvmap_linear_patch[1]; 1882 1883 static void __init kernel_physical_mapping_init(void) 1884 { 1885 unsigned long i, mem_alloced = 0UL; 1886 bool use_huge = true; 1887 1888 #ifdef CONFIG_DEBUG_PAGEALLOC 1889 use_huge = false; 1890 #endif 1891 for (i = 0; i < pall_ents; i++) { 1892 unsigned long phys_start, phys_end; 1893 1894 phys_start = pall[i].phys_addr; 1895 phys_end = phys_start + pall[i].reg_size; 1896 1897 mem_alloced += kernel_map_range(phys_start, phys_end, 1898 PAGE_KERNEL, use_huge); 1899 } 1900 1901 printk("Allocated %ld bytes for kernel page tables.\n", 1902 mem_alloced); 1903 1904 kvmap_linear_patch[0] = 0x01000000; /* nop */ 1905 flushi(&kvmap_linear_patch[0]); 1906 1907 flush_all_kernel_tsbs(); 1908 1909 __flush_tlb_all(); 1910 } 1911 1912 #ifdef CONFIG_DEBUG_PAGEALLOC 1913 void __kernel_map_pages(struct page *page, int numpages, int enable) 1914 { 1915 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1916 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); 1917 1918 kernel_map_range(phys_start, phys_end, 1919 (enable ? PAGE_KERNEL : __pgprot(0)), false); 1920 1921 flush_tsb_kernel_range(PAGE_OFFSET + phys_start, 1922 PAGE_OFFSET + phys_end); 1923 1924 /* we should perform an IPI and flush all tlbs, 1925 * but that can deadlock->flush only current cpu. 1926 */ 1927 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, 1928 PAGE_OFFSET + phys_end); 1929 } 1930 #endif 1931 1932 unsigned long __init find_ecache_flush_span(unsigned long size) 1933 { 1934 int i; 1935 1936 for (i = 0; i < pavail_ents; i++) { 1937 if (pavail[i].reg_size >= size) 1938 return pavail[i].phys_addr; 1939 } 1940 1941 return ~0UL; 1942 } 1943 1944 unsigned long PAGE_OFFSET; 1945 EXPORT_SYMBOL(PAGE_OFFSET); 1946 1947 unsigned long VMALLOC_END = 0x0000010000000000UL; 1948 EXPORT_SYMBOL(VMALLOC_END); 1949 1950 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; 1951 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; 1952 1953 static void __init setup_page_offset(void) 1954 { 1955 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1956 /* Cheetah/Panther support a full 64-bit virtual 1957 * address, so we can use all that our page tables 1958 * support. 1959 */ 1960 sparc64_va_hole_top = 0xfff0000000000000UL; 1961 sparc64_va_hole_bottom = 0x0010000000000000UL; 1962 1963 max_phys_bits = 42; 1964 } else if (tlb_type == hypervisor) { 1965 switch (sun4v_chip_type) { 1966 case SUN4V_CHIP_NIAGARA1: 1967 case SUN4V_CHIP_NIAGARA2: 1968 /* T1 and T2 support 48-bit virtual addresses. */ 1969 sparc64_va_hole_top = 0xffff800000000000UL; 1970 sparc64_va_hole_bottom = 0x0000800000000000UL; 1971 1972 max_phys_bits = 39; 1973 break; 1974 case SUN4V_CHIP_NIAGARA3: 1975 /* T3 supports 48-bit virtual addresses. */ 1976 sparc64_va_hole_top = 0xffff800000000000UL; 1977 sparc64_va_hole_bottom = 0x0000800000000000UL; 1978 1979 max_phys_bits = 43; 1980 break; 1981 case SUN4V_CHIP_NIAGARA4: 1982 case SUN4V_CHIP_NIAGARA5: 1983 case SUN4V_CHIP_SPARC64X: 1984 case SUN4V_CHIP_SPARC_M6: 1985 /* T4 and later support 52-bit virtual addresses. */ 1986 sparc64_va_hole_top = 0xfff8000000000000UL; 1987 sparc64_va_hole_bottom = 0x0008000000000000UL; 1988 max_phys_bits = 47; 1989 break; 1990 case SUN4V_CHIP_SPARC_M7: 1991 case SUN4V_CHIP_SPARC_SN: 1992 /* M7 and later support 52-bit virtual addresses. */ 1993 sparc64_va_hole_top = 0xfff8000000000000UL; 1994 sparc64_va_hole_bottom = 0x0008000000000000UL; 1995 max_phys_bits = 49; 1996 break; 1997 case SUN4V_CHIP_SPARC_M8: 1998 default: 1999 /* M8 and later support 54-bit virtual addresses. 2000 * However, restricting M8 and above VA bits to 53 2001 * as 4-level page table cannot support more than 2002 * 53 VA bits. 2003 */ 2004 sparc64_va_hole_top = 0xfff0000000000000UL; 2005 sparc64_va_hole_bottom = 0x0010000000000000UL; 2006 max_phys_bits = 51; 2007 break; 2008 } 2009 } 2010 2011 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { 2012 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", 2013 max_phys_bits); 2014 prom_halt(); 2015 } 2016 2017 PAGE_OFFSET = sparc64_va_hole_top; 2018 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + 2019 (sparc64_va_hole_bottom >> 2)); 2020 2021 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", 2022 PAGE_OFFSET, max_phys_bits); 2023 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", 2024 VMALLOC_START, VMALLOC_END); 2025 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", 2026 VMEMMAP_BASE, VMEMMAP_BASE << 1); 2027 } 2028 2029 static void __init tsb_phys_patch(void) 2030 { 2031 struct tsb_ldquad_phys_patch_entry *pquad; 2032 struct tsb_phys_patch_entry *p; 2033 2034 pquad = &__tsb_ldquad_phys_patch; 2035 while (pquad < &__tsb_ldquad_phys_patch_end) { 2036 unsigned long addr = pquad->addr; 2037 2038 if (tlb_type == hypervisor) 2039 *(unsigned int *) addr = pquad->sun4v_insn; 2040 else 2041 *(unsigned int *) addr = pquad->sun4u_insn; 2042 wmb(); 2043 __asm__ __volatile__("flush %0" 2044 : /* no outputs */ 2045 : "r" (addr)); 2046 2047 pquad++; 2048 } 2049 2050 p = &__tsb_phys_patch; 2051 while (p < &__tsb_phys_patch_end) { 2052 unsigned long addr = p->addr; 2053 2054 *(unsigned int *) addr = p->insn; 2055 wmb(); 2056 __asm__ __volatile__("flush %0" 2057 : /* no outputs */ 2058 : "r" (addr)); 2059 2060 p++; 2061 } 2062 } 2063 2064 /* Don't mark as init, we give this to the Hypervisor. */ 2065 #ifndef CONFIG_DEBUG_PAGEALLOC 2066 #define NUM_KTSB_DESCR 2 2067 #else 2068 #define NUM_KTSB_DESCR 1 2069 #endif 2070 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; 2071 2072 /* The swapper TSBs are loaded with a base sequence of: 2073 * 2074 * sethi %uhi(SYMBOL), REG1 2075 * sethi %hi(SYMBOL), REG2 2076 * or REG1, %ulo(SYMBOL), REG1 2077 * or REG2, %lo(SYMBOL), REG2 2078 * sllx REG1, 32, REG1 2079 * or REG1, REG2, REG1 2080 * 2081 * When we use physical addressing for the TSB accesses, we patch the 2082 * first four instructions in the above sequence. 2083 */ 2084 2085 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) 2086 { 2087 unsigned long high_bits, low_bits; 2088 2089 high_bits = (pa >> 32) & 0xffffffff; 2090 low_bits = (pa >> 0) & 0xffffffff; 2091 2092 while (start < end) { 2093 unsigned int *ia = (unsigned int *)(unsigned long)*start; 2094 2095 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); 2096 __asm__ __volatile__("flush %0" : : "r" (ia)); 2097 2098 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); 2099 __asm__ __volatile__("flush %0" : : "r" (ia + 1)); 2100 2101 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); 2102 __asm__ __volatile__("flush %0" : : "r" (ia + 2)); 2103 2104 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); 2105 __asm__ __volatile__("flush %0" : : "r" (ia + 3)); 2106 2107 start++; 2108 } 2109 } 2110 2111 static void ktsb_phys_patch(void) 2112 { 2113 extern unsigned int __swapper_tsb_phys_patch; 2114 extern unsigned int __swapper_tsb_phys_patch_end; 2115 unsigned long ktsb_pa; 2116 2117 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2118 patch_one_ktsb_phys(&__swapper_tsb_phys_patch, 2119 &__swapper_tsb_phys_patch_end, ktsb_pa); 2120 #ifndef CONFIG_DEBUG_PAGEALLOC 2121 { 2122 extern unsigned int __swapper_4m_tsb_phys_patch; 2123 extern unsigned int __swapper_4m_tsb_phys_patch_end; 2124 ktsb_pa = (kern_base + 2125 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2126 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, 2127 &__swapper_4m_tsb_phys_patch_end, ktsb_pa); 2128 } 2129 #endif 2130 } 2131 2132 static void __init sun4v_ktsb_init(void) 2133 { 2134 unsigned long ktsb_pa; 2135 2136 /* First KTSB for PAGE_SIZE mappings. */ 2137 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2138 2139 switch (PAGE_SIZE) { 2140 case 8 * 1024: 2141 default: 2142 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; 2143 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; 2144 break; 2145 2146 case 64 * 1024: 2147 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; 2148 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; 2149 break; 2150 2151 case 512 * 1024: 2152 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; 2153 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; 2154 break; 2155 2156 case 4 * 1024 * 1024: 2157 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; 2158 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; 2159 break; 2160 } 2161 2162 ktsb_descr[0].assoc = 1; 2163 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; 2164 ktsb_descr[0].ctx_idx = 0; 2165 ktsb_descr[0].tsb_base = ktsb_pa; 2166 ktsb_descr[0].resv = 0; 2167 2168 #ifndef CONFIG_DEBUG_PAGEALLOC 2169 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ 2170 ktsb_pa = (kern_base + 2171 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2172 2173 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; 2174 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | 2175 HV_PGSZ_MASK_256MB | 2176 HV_PGSZ_MASK_2GB | 2177 HV_PGSZ_MASK_16GB) & 2178 cpu_pgsz_mask); 2179 ktsb_descr[1].assoc = 1; 2180 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; 2181 ktsb_descr[1].ctx_idx = 0; 2182 ktsb_descr[1].tsb_base = ktsb_pa; 2183 ktsb_descr[1].resv = 0; 2184 #endif 2185 } 2186 2187 void sun4v_ktsb_register(void) 2188 { 2189 unsigned long pa, ret; 2190 2191 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); 2192 2193 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); 2194 if (ret != 0) { 2195 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " 2196 "errors with %lx\n", pa, ret); 2197 prom_halt(); 2198 } 2199 } 2200 2201 static void __init sun4u_linear_pte_xor_finalize(void) 2202 { 2203 #ifndef CONFIG_DEBUG_PAGEALLOC 2204 /* This is where we would add Panther support for 2205 * 32MB and 256MB pages. 2206 */ 2207 #endif 2208 } 2209 2210 static void __init sun4v_linear_pte_xor_finalize(void) 2211 { 2212 unsigned long pagecv_flag; 2213 2214 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead 2215 * enables MCD error. Do not set bit 9 on M7 processor. 2216 */ 2217 switch (sun4v_chip_type) { 2218 case SUN4V_CHIP_SPARC_M7: 2219 case SUN4V_CHIP_SPARC_M8: 2220 case SUN4V_CHIP_SPARC_SN: 2221 pagecv_flag = 0x00; 2222 break; 2223 default: 2224 pagecv_flag = _PAGE_CV_4V; 2225 break; 2226 } 2227 #ifndef CONFIG_DEBUG_PAGEALLOC 2228 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { 2229 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2230 PAGE_OFFSET; 2231 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | 2232 _PAGE_P_4V | _PAGE_W_4V); 2233 } else { 2234 kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; 2235 } 2236 2237 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { 2238 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ 2239 PAGE_OFFSET; 2240 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | 2241 _PAGE_P_4V | _PAGE_W_4V); 2242 } else { 2243 kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; 2244 } 2245 2246 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { 2247 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ 2248 PAGE_OFFSET; 2249 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | 2250 _PAGE_P_4V | _PAGE_W_4V); 2251 } else { 2252 kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; 2253 } 2254 #endif 2255 } 2256 2257 /* paging_init() sets up the page tables */ 2258 2259 static unsigned long last_valid_pfn; 2260 2261 static void sun4u_pgprot_init(void); 2262 static void sun4v_pgprot_init(void); 2263 2264 static phys_addr_t __init available_memory(void) 2265 { 2266 phys_addr_t available = 0ULL; 2267 phys_addr_t pa_start, pa_end; 2268 u64 i; 2269 2270 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, 2271 &pa_end, NULL) 2272 available = available + (pa_end - pa_start); 2273 2274 return available; 2275 } 2276 2277 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) 2278 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) 2279 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) 2280 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) 2281 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) 2282 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) 2283 2284 /* We need to exclude reserved regions. This exclusion will include 2285 * vmlinux and initrd. To be more precise the initrd size could be used to 2286 * compute a new lower limit because it is freed later during initialization. 2287 */ 2288 static void __init reduce_memory(phys_addr_t limit_ram) 2289 { 2290 phys_addr_t avail_ram = available_memory(); 2291 phys_addr_t pa_start, pa_end; 2292 u64 i; 2293 2294 if (limit_ram >= avail_ram) 2295 return; 2296 2297 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, 2298 &pa_end, NULL) { 2299 phys_addr_t region_size = pa_end - pa_start; 2300 phys_addr_t clip_start = pa_start; 2301 2302 avail_ram = avail_ram - region_size; 2303 /* Are we consuming too much? */ 2304 if (avail_ram < limit_ram) { 2305 phys_addr_t give_back = limit_ram - avail_ram; 2306 2307 region_size = region_size - give_back; 2308 clip_start = clip_start + give_back; 2309 } 2310 2311 memblock_remove(clip_start, region_size); 2312 2313 if (avail_ram <= limit_ram) 2314 break; 2315 i = 0UL; 2316 } 2317 } 2318 2319 void __init paging_init(void) 2320 { 2321 unsigned long end_pfn, shift, phys_base; 2322 unsigned long real_end, i; 2323 2324 setup_page_offset(); 2325 2326 /* These build time checkes make sure that the dcache_dirty_cpu() 2327 * page->flags usage will work. 2328 * 2329 * When a page gets marked as dcache-dirty, we store the 2330 * cpu number starting at bit 32 in the page->flags. Also, 2331 * functions like clear_dcache_dirty_cpu use the cpu mask 2332 * in 13-bit signed-immediate instruction fields. 2333 */ 2334 2335 /* 2336 * Page flags must not reach into upper 32 bits that are used 2337 * for the cpu number 2338 */ 2339 BUILD_BUG_ON(NR_PAGEFLAGS > 32); 2340 2341 /* 2342 * The bit fields placed in the high range must not reach below 2343 * the 32 bit boundary. Otherwise we cannot place the cpu field 2344 * at the 32 bit boundary. 2345 */ 2346 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + 2347 ilog2(roundup_pow_of_two(NR_CPUS)) > 32); 2348 2349 BUILD_BUG_ON(NR_CPUS > 4096); 2350 2351 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 2352 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 2353 2354 /* Invalidate both kernel TSBs. */ 2355 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 2356 #ifndef CONFIG_DEBUG_PAGEALLOC 2357 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2358 #endif 2359 2360 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde 2361 * bit on M7 processor. This is a conflicting usage of the same 2362 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption 2363 * Detection error on all pages and this will lead to problems 2364 * later. Kernel does not run with MCD enabled and hence rest 2365 * of the required steps to fully configure memory corruption 2366 * detection are not taken. We need to ensure TTE.mcde is not 2367 * set on M7 processor. Compute the value of cacheability 2368 * flag for use later taking this into consideration. 2369 */ 2370 switch (sun4v_chip_type) { 2371 case SUN4V_CHIP_SPARC_M7: 2372 case SUN4V_CHIP_SPARC_M8: 2373 case SUN4V_CHIP_SPARC_SN: 2374 page_cache4v_flag = _PAGE_CP_4V; 2375 break; 2376 default: 2377 page_cache4v_flag = _PAGE_CACHE_4V; 2378 break; 2379 } 2380 2381 if (tlb_type == hypervisor) 2382 sun4v_pgprot_init(); 2383 else 2384 sun4u_pgprot_init(); 2385 2386 if (tlb_type == cheetah_plus || 2387 tlb_type == hypervisor) { 2388 tsb_phys_patch(); 2389 ktsb_phys_patch(); 2390 } 2391 2392 if (tlb_type == hypervisor) 2393 sun4v_patch_tlb_handlers(); 2394 2395 /* Find available physical memory... 2396 * 2397 * Read it twice in order to work around a bug in openfirmware. 2398 * The call to grab this table itself can cause openfirmware to 2399 * allocate memory, which in turn can take away some space from 2400 * the list of available memory. Reading it twice makes sure 2401 * we really do get the final value. 2402 */ 2403 read_obp_translations(); 2404 read_obp_memory("reg", &pall[0], &pall_ents); 2405 read_obp_memory("available", &pavail[0], &pavail_ents); 2406 read_obp_memory("available", &pavail[0], &pavail_ents); 2407 2408 phys_base = 0xffffffffffffffffUL; 2409 for (i = 0; i < pavail_ents; i++) { 2410 phys_base = min(phys_base, pavail[i].phys_addr); 2411 memblock_add(pavail[i].phys_addr, pavail[i].reg_size); 2412 } 2413 2414 memblock_reserve(kern_base, kern_size); 2415 2416 find_ramdisk(phys_base); 2417 2418 if (cmdline_memory_size) 2419 reduce_memory(cmdline_memory_size); 2420 2421 memblock_allow_resize(); 2422 memblock_dump_all(); 2423 2424 set_bit(0, mmu_context_bmap); 2425 2426 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 2427 2428 real_end = (unsigned long)_end; 2429 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); 2430 printk("Kernel: Using %d locked TLB entries for main kernel image.\n", 2431 num_kernel_image_mappings); 2432 2433 /* Set kernel pgd to upper alias so physical page computations 2434 * work. 2435 */ 2436 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 2437 2438 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); 2439 2440 inherit_prom_mappings(); 2441 2442 /* Ok, we can use our TLB miss and window trap handlers safely. */ 2443 setup_tba(); 2444 2445 __flush_tlb_all(); 2446 2447 prom_build_devicetree(); 2448 of_populate_present_mask(); 2449 #ifndef CONFIG_SMP 2450 of_fill_in_cpu_data(); 2451 #endif 2452 2453 if (tlb_type == hypervisor) { 2454 sun4v_mdesc_init(); 2455 mdesc_populate_present_mask(cpu_all_mask); 2456 #ifndef CONFIG_SMP 2457 mdesc_fill_in_cpu_data(cpu_all_mask); 2458 #endif 2459 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); 2460 2461 sun4v_linear_pte_xor_finalize(); 2462 2463 sun4v_ktsb_init(); 2464 sun4v_ktsb_register(); 2465 } else { 2466 unsigned long impl, ver; 2467 2468 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | 2469 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); 2470 2471 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 2472 impl = ((ver >> 32) & 0xffff); 2473 if (impl == PANTHER_IMPL) 2474 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | 2475 HV_PGSZ_MASK_256MB); 2476 2477 sun4u_linear_pte_xor_finalize(); 2478 } 2479 2480 /* Flush the TLBs and the 4M TSB so that the updated linear 2481 * pte XOR settings are realized for all mappings. 2482 */ 2483 __flush_tlb_all(); 2484 #ifndef CONFIG_DEBUG_PAGEALLOC 2485 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2486 #endif 2487 __flush_tlb_all(); 2488 2489 /* Setup bootmem... */ 2490 last_valid_pfn = end_pfn = bootmem_init(phys_base); 2491 2492 kernel_physical_mapping_init(); 2493 2494 { 2495 unsigned long max_zone_pfns[MAX_NR_ZONES]; 2496 2497 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 2498 2499 max_zone_pfns[ZONE_NORMAL] = end_pfn; 2500 2501 free_area_init_nodes(max_zone_pfns); 2502 } 2503 2504 printk("Booting Linux...\n"); 2505 } 2506 2507 int page_in_phys_avail(unsigned long paddr) 2508 { 2509 int i; 2510 2511 paddr &= PAGE_MASK; 2512 2513 for (i = 0; i < pavail_ents; i++) { 2514 unsigned long start, end; 2515 2516 start = pavail[i].phys_addr; 2517 end = start + pavail[i].reg_size; 2518 2519 if (paddr >= start && paddr < end) 2520 return 1; 2521 } 2522 if (paddr >= kern_base && paddr < (kern_base + kern_size)) 2523 return 1; 2524 #ifdef CONFIG_BLK_DEV_INITRD 2525 if (paddr >= __pa(initrd_start) && 2526 paddr < __pa(PAGE_ALIGN(initrd_end))) 2527 return 1; 2528 #endif 2529 2530 return 0; 2531 } 2532 2533 static void __init register_page_bootmem_info(void) 2534 { 2535 #ifdef CONFIG_NEED_MULTIPLE_NODES 2536 int i; 2537 2538 for_each_online_node(i) 2539 if (NODE_DATA(i)->node_spanned_pages) 2540 register_page_bootmem_info_node(NODE_DATA(i)); 2541 #endif 2542 } 2543 void __init mem_init(void) 2544 { 2545 high_memory = __va(last_valid_pfn << PAGE_SHIFT); 2546 2547 memblock_free_all(); 2548 2549 /* 2550 * Must be done after boot memory is put on freelist, because here we 2551 * might set fields in deferred struct pages that have not yet been 2552 * initialized, and memblock_free_all() initializes all the reserved 2553 * deferred pages for us. 2554 */ 2555 register_page_bootmem_info(); 2556 2557 /* 2558 * Set up the zero page, mark it reserved, so that page count 2559 * is not manipulated when freeing the page from user ptes. 2560 */ 2561 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); 2562 if (mem_map_zero == NULL) { 2563 prom_printf("paging_init: Cannot alloc zero page.\n"); 2564 prom_halt(); 2565 } 2566 mark_page_reserved(mem_map_zero); 2567 2568 mem_init_print_info(NULL); 2569 2570 if (tlb_type == cheetah || tlb_type == cheetah_plus) 2571 cheetah_ecache_flush_init(); 2572 } 2573 2574 void free_initmem(void) 2575 { 2576 unsigned long addr, initend; 2577 int do_free = 1; 2578 2579 /* If the physical memory maps were trimmed by kernel command 2580 * line options, don't even try freeing this initmem stuff up. 2581 * The kernel image could have been in the trimmed out region 2582 * and if so the freeing below will free invalid page structs. 2583 */ 2584 if (cmdline_memory_size) 2585 do_free = 0; 2586 2587 /* 2588 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. 2589 */ 2590 addr = PAGE_ALIGN((unsigned long)(__init_begin)); 2591 initend = (unsigned long)(__init_end) & PAGE_MASK; 2592 for (; addr < initend; addr += PAGE_SIZE) { 2593 unsigned long page; 2594 2595 page = (addr + 2596 ((unsigned long) __va(kern_base)) - 2597 ((unsigned long) KERNBASE)); 2598 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 2599 2600 if (do_free) 2601 free_reserved_page(virt_to_page(page)); 2602 } 2603 } 2604 2605 #ifdef CONFIG_BLK_DEV_INITRD 2606 void free_initrd_mem(unsigned long start, unsigned long end) 2607 { 2608 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM, 2609 "initrd"); 2610 } 2611 #endif 2612 2613 pgprot_t PAGE_KERNEL __read_mostly; 2614 EXPORT_SYMBOL(PAGE_KERNEL); 2615 2616 pgprot_t PAGE_KERNEL_LOCKED __read_mostly; 2617 pgprot_t PAGE_COPY __read_mostly; 2618 2619 pgprot_t PAGE_SHARED __read_mostly; 2620 EXPORT_SYMBOL(PAGE_SHARED); 2621 2622 unsigned long pg_iobits __read_mostly; 2623 2624 unsigned long _PAGE_IE __read_mostly; 2625 EXPORT_SYMBOL(_PAGE_IE); 2626 2627 unsigned long _PAGE_E __read_mostly; 2628 EXPORT_SYMBOL(_PAGE_E); 2629 2630 unsigned long _PAGE_CACHE __read_mostly; 2631 EXPORT_SYMBOL(_PAGE_CACHE); 2632 2633 #ifdef CONFIG_SPARSEMEM_VMEMMAP 2634 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, 2635 int node, struct vmem_altmap *altmap) 2636 { 2637 unsigned long pte_base; 2638 2639 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2640 _PAGE_CP_4U | _PAGE_CV_4U | 2641 _PAGE_P_4U | _PAGE_W_4U); 2642 if (tlb_type == hypervisor) 2643 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2644 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); 2645 2646 pte_base |= _PAGE_PMD_HUGE; 2647 2648 vstart = vstart & PMD_MASK; 2649 vend = ALIGN(vend, PMD_SIZE); 2650 for (; vstart < vend; vstart += PMD_SIZE) { 2651 pgd_t *pgd = vmemmap_pgd_populate(vstart, node); 2652 unsigned long pte; 2653 pud_t *pud; 2654 pmd_t *pmd; 2655 2656 if (!pgd) 2657 return -ENOMEM; 2658 2659 pud = vmemmap_pud_populate(pgd, vstart, node); 2660 if (!pud) 2661 return -ENOMEM; 2662 2663 pmd = pmd_offset(pud, vstart); 2664 pte = pmd_val(*pmd); 2665 if (!(pte & _PAGE_VALID)) { 2666 void *block = vmemmap_alloc_block(PMD_SIZE, node); 2667 2668 if (!block) 2669 return -ENOMEM; 2670 2671 pmd_val(*pmd) = pte_base | __pa(block); 2672 } 2673 } 2674 2675 return 0; 2676 } 2677 2678 void vmemmap_free(unsigned long start, unsigned long end, 2679 struct vmem_altmap *altmap) 2680 { 2681 } 2682 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 2683 2684 static void prot_init_common(unsigned long page_none, 2685 unsigned long page_shared, 2686 unsigned long page_copy, 2687 unsigned long page_readonly, 2688 unsigned long page_exec_bit) 2689 { 2690 PAGE_COPY = __pgprot(page_copy); 2691 PAGE_SHARED = __pgprot(page_shared); 2692 2693 protection_map[0x0] = __pgprot(page_none); 2694 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); 2695 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); 2696 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); 2697 protection_map[0x4] = __pgprot(page_readonly); 2698 protection_map[0x5] = __pgprot(page_readonly); 2699 protection_map[0x6] = __pgprot(page_copy); 2700 protection_map[0x7] = __pgprot(page_copy); 2701 protection_map[0x8] = __pgprot(page_none); 2702 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); 2703 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); 2704 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); 2705 protection_map[0xc] = __pgprot(page_readonly); 2706 protection_map[0xd] = __pgprot(page_readonly); 2707 protection_map[0xe] = __pgprot(page_shared); 2708 protection_map[0xf] = __pgprot(page_shared); 2709 } 2710 2711 static void __init sun4u_pgprot_init(void) 2712 { 2713 unsigned long page_none, page_shared, page_copy, page_readonly; 2714 unsigned long page_exec_bit; 2715 int i; 2716 2717 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2718 _PAGE_CACHE_4U | _PAGE_P_4U | 2719 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2720 _PAGE_EXEC_4U); 2721 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2722 _PAGE_CACHE_4U | _PAGE_P_4U | 2723 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2724 _PAGE_EXEC_4U | _PAGE_L_4U); 2725 2726 _PAGE_IE = _PAGE_IE_4U; 2727 _PAGE_E = _PAGE_E_4U; 2728 _PAGE_CACHE = _PAGE_CACHE_4U; 2729 2730 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | 2731 __ACCESS_BITS_4U | _PAGE_E_4U); 2732 2733 #ifdef CONFIG_DEBUG_PAGEALLOC 2734 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2735 #else 2736 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2737 PAGE_OFFSET; 2738 #endif 2739 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2740 _PAGE_P_4U | _PAGE_W_4U); 2741 2742 for (i = 1; i < 4; i++) 2743 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2744 2745 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | 2746 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | 2747 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); 2748 2749 2750 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; 2751 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2752 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); 2753 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2754 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2755 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2756 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2757 2758 page_exec_bit = _PAGE_EXEC_4U; 2759 2760 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2761 page_exec_bit); 2762 } 2763 2764 static void __init sun4v_pgprot_init(void) 2765 { 2766 unsigned long page_none, page_shared, page_copy, page_readonly; 2767 unsigned long page_exec_bit; 2768 int i; 2769 2770 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | 2771 page_cache4v_flag | _PAGE_P_4V | 2772 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2773 _PAGE_EXEC_4V); 2774 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2775 2776 _PAGE_IE = _PAGE_IE_4V; 2777 _PAGE_E = _PAGE_E_4V; 2778 _PAGE_CACHE = page_cache4v_flag; 2779 2780 #ifdef CONFIG_DEBUG_PAGEALLOC 2781 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2782 #else 2783 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2784 PAGE_OFFSET; 2785 #endif 2786 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | 2787 _PAGE_W_4V); 2788 2789 for (i = 1; i < 4; i++) 2790 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2791 2792 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | 2793 __ACCESS_BITS_4V | _PAGE_E_4V); 2794 2795 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | 2796 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | 2797 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | 2798 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); 2799 2800 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; 2801 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2802 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); 2803 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2804 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2805 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2806 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2807 2808 page_exec_bit = _PAGE_EXEC_4V; 2809 2810 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2811 page_exec_bit); 2812 } 2813 2814 unsigned long pte_sz_bits(unsigned long sz) 2815 { 2816 if (tlb_type == hypervisor) { 2817 switch (sz) { 2818 case 8 * 1024: 2819 default: 2820 return _PAGE_SZ8K_4V; 2821 case 64 * 1024: 2822 return _PAGE_SZ64K_4V; 2823 case 512 * 1024: 2824 return _PAGE_SZ512K_4V; 2825 case 4 * 1024 * 1024: 2826 return _PAGE_SZ4MB_4V; 2827 } 2828 } else { 2829 switch (sz) { 2830 case 8 * 1024: 2831 default: 2832 return _PAGE_SZ8K_4U; 2833 case 64 * 1024: 2834 return _PAGE_SZ64K_4U; 2835 case 512 * 1024: 2836 return _PAGE_SZ512K_4U; 2837 case 4 * 1024 * 1024: 2838 return _PAGE_SZ4MB_4U; 2839 } 2840 } 2841 } 2842 2843 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) 2844 { 2845 pte_t pte; 2846 2847 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); 2848 pte_val(pte) |= (((unsigned long)space) << 32); 2849 pte_val(pte) |= pte_sz_bits(page_size); 2850 2851 return pte; 2852 } 2853 2854 static unsigned long kern_large_tte(unsigned long paddr) 2855 { 2856 unsigned long val; 2857 2858 val = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2859 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | 2860 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); 2861 if (tlb_type == hypervisor) 2862 val = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2863 page_cache4v_flag | _PAGE_P_4V | 2864 _PAGE_EXEC_4V | _PAGE_W_4V); 2865 2866 return val | paddr; 2867 } 2868 2869 /* If not locked, zap it. */ 2870 void __flush_tlb_all(void) 2871 { 2872 unsigned long pstate; 2873 int i; 2874 2875 __asm__ __volatile__("flushw\n\t" 2876 "rdpr %%pstate, %0\n\t" 2877 "wrpr %0, %1, %%pstate" 2878 : "=r" (pstate) 2879 : "i" (PSTATE_IE)); 2880 if (tlb_type == hypervisor) { 2881 sun4v_mmu_demap_all(); 2882 } else if (tlb_type == spitfire) { 2883 for (i = 0; i < 64; i++) { 2884 /* Spitfire Errata #32 workaround */ 2885 /* NOTE: Always runs on spitfire, so no 2886 * cheetah+ page size encodings. 2887 */ 2888 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2889 "flush %%g6" 2890 : /* No outputs */ 2891 : "r" (0), 2892 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2893 2894 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { 2895 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2896 "membar #Sync" 2897 : /* no outputs */ 2898 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); 2899 spitfire_put_dtlb_data(i, 0x0UL); 2900 } 2901 2902 /* Spitfire Errata #32 workaround */ 2903 /* NOTE: Always runs on spitfire, so no 2904 * cheetah+ page size encodings. 2905 */ 2906 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2907 "flush %%g6" 2908 : /* No outputs */ 2909 : "r" (0), 2910 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2911 2912 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { 2913 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2914 "membar #Sync" 2915 : /* no outputs */ 2916 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); 2917 spitfire_put_itlb_data(i, 0x0UL); 2918 } 2919 } 2920 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 2921 cheetah_flush_dtlb_all(); 2922 cheetah_flush_itlb_all(); 2923 } 2924 __asm__ __volatile__("wrpr %0, 0, %%pstate" 2925 : : "r" (pstate)); 2926 } 2927 2928 pte_t *pte_alloc_one_kernel(struct mm_struct *mm) 2929 { 2930 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO); 2931 pte_t *pte = NULL; 2932 2933 if (page) 2934 pte = (pte_t *) page_address(page); 2935 2936 return pte; 2937 } 2938 2939 pgtable_t pte_alloc_one(struct mm_struct *mm) 2940 { 2941 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO); 2942 if (!page) 2943 return NULL; 2944 if (!pgtable_page_ctor(page)) { 2945 free_unref_page(page); 2946 return NULL; 2947 } 2948 return (pte_t *) page_address(page); 2949 } 2950 2951 void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 2952 { 2953 free_page((unsigned long)pte); 2954 } 2955 2956 static void __pte_free(pgtable_t pte) 2957 { 2958 struct page *page = virt_to_page(pte); 2959 2960 pgtable_page_dtor(page); 2961 __free_page(page); 2962 } 2963 2964 void pte_free(struct mm_struct *mm, pgtable_t pte) 2965 { 2966 __pte_free(pte); 2967 } 2968 2969 void pgtable_free(void *table, bool is_page) 2970 { 2971 if (is_page) 2972 __pte_free(table); 2973 else 2974 kmem_cache_free(pgtable_cache, table); 2975 } 2976 2977 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 2978 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 2979 pmd_t *pmd) 2980 { 2981 unsigned long pte, flags; 2982 struct mm_struct *mm; 2983 pmd_t entry = *pmd; 2984 2985 if (!pmd_large(entry) || !pmd_young(entry)) 2986 return; 2987 2988 pte = pmd_val(entry); 2989 2990 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ 2991 if (!(pte & _PAGE_VALID)) 2992 return; 2993 2994 /* We are fabricating 8MB pages using 4MB real hw pages. */ 2995 pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); 2996 2997 mm = vma->vm_mm; 2998 2999 spin_lock_irqsave(&mm->context.lock, flags); 3000 3001 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) 3002 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 3003 addr, pte); 3004 3005 spin_unlock_irqrestore(&mm->context.lock, flags); 3006 } 3007 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 3008 3009 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 3010 static void context_reload(void *__data) 3011 { 3012 struct mm_struct *mm = __data; 3013 3014 if (mm == current->mm) 3015 load_secondary_context(mm); 3016 } 3017 3018 void hugetlb_setup(struct pt_regs *regs) 3019 { 3020 struct mm_struct *mm = current->mm; 3021 struct tsb_config *tp; 3022 3023 if (faulthandler_disabled() || !mm) { 3024 const struct exception_table_entry *entry; 3025 3026 entry = search_exception_tables(regs->tpc); 3027 if (entry) { 3028 regs->tpc = entry->fixup; 3029 regs->tnpc = regs->tpc + 4; 3030 return; 3031 } 3032 pr_alert("Unexpected HugeTLB setup in atomic context.\n"); 3033 die_if_kernel("HugeTSB in atomic", regs); 3034 } 3035 3036 tp = &mm->context.tsb_block[MM_TSB_HUGE]; 3037 if (likely(tp->tsb == NULL)) 3038 tsb_grow(mm, MM_TSB_HUGE, 0); 3039 3040 tsb_context_switch(mm); 3041 smp_tsb_sync(mm); 3042 3043 /* On UltraSPARC-III+ and later, configure the second half of 3044 * the Data-TLB for huge pages. 3045 */ 3046 if (tlb_type == cheetah_plus) { 3047 bool need_context_reload = false; 3048 unsigned long ctx; 3049 3050 spin_lock_irq(&ctx_alloc_lock); 3051 ctx = mm->context.sparc64_ctx_val; 3052 ctx &= ~CTX_PGSZ_MASK; 3053 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; 3054 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; 3055 3056 if (ctx != mm->context.sparc64_ctx_val) { 3057 /* When changing the page size fields, we 3058 * must perform a context flush so that no 3059 * stale entries match. This flush must 3060 * occur with the original context register 3061 * settings. 3062 */ 3063 do_flush_tlb_mm(mm); 3064 3065 /* Reload the context register of all processors 3066 * also executing in this address space. 3067 */ 3068 mm->context.sparc64_ctx_val = ctx; 3069 need_context_reload = true; 3070 } 3071 spin_unlock_irq(&ctx_alloc_lock); 3072 3073 if (need_context_reload) 3074 on_each_cpu(context_reload, mm, 0); 3075 } 3076 } 3077 #endif 3078 3079 static struct resource code_resource = { 3080 .name = "Kernel code", 3081 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3082 }; 3083 3084 static struct resource data_resource = { 3085 .name = "Kernel data", 3086 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3087 }; 3088 3089 static struct resource bss_resource = { 3090 .name = "Kernel bss", 3091 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3092 }; 3093 3094 static inline resource_size_t compute_kern_paddr(void *addr) 3095 { 3096 return (resource_size_t) (addr - KERNBASE + kern_base); 3097 } 3098 3099 static void __init kernel_lds_init(void) 3100 { 3101 code_resource.start = compute_kern_paddr(_text); 3102 code_resource.end = compute_kern_paddr(_etext - 1); 3103 data_resource.start = compute_kern_paddr(_etext); 3104 data_resource.end = compute_kern_paddr(_edata - 1); 3105 bss_resource.start = compute_kern_paddr(__bss_start); 3106 bss_resource.end = compute_kern_paddr(_end - 1); 3107 } 3108 3109 static int __init report_memory(void) 3110 { 3111 int i; 3112 struct resource *res; 3113 3114 kernel_lds_init(); 3115 3116 for (i = 0; i < pavail_ents; i++) { 3117 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 3118 3119 if (!res) { 3120 pr_warn("Failed to allocate source.\n"); 3121 break; 3122 } 3123 3124 res->name = "System RAM"; 3125 res->start = pavail[i].phys_addr; 3126 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; 3127 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; 3128 3129 if (insert_resource(&iomem_resource, res) < 0) { 3130 pr_warn("Resource insertion failed.\n"); 3131 break; 3132 } 3133 3134 insert_resource(res, &code_resource); 3135 insert_resource(res, &data_resource); 3136 insert_resource(res, &bss_resource); 3137 } 3138 3139 return 0; 3140 } 3141 arch_initcall(report_memory); 3142 3143 #ifdef CONFIG_SMP 3144 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range 3145 #else 3146 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range 3147 #endif 3148 3149 void flush_tlb_kernel_range(unsigned long start, unsigned long end) 3150 { 3151 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { 3152 if (start < LOW_OBP_ADDRESS) { 3153 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); 3154 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); 3155 } 3156 if (end > HI_OBP_ADDRESS) { 3157 flush_tsb_kernel_range(HI_OBP_ADDRESS, end); 3158 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); 3159 } 3160 } else { 3161 flush_tsb_kernel_range(start, end); 3162 do_flush_tlb_kernel_range(start, end); 3163 } 3164 } 3165 3166 void copy_user_highpage(struct page *to, struct page *from, 3167 unsigned long vaddr, struct vm_area_struct *vma) 3168 { 3169 char *vfrom, *vto; 3170 3171 vfrom = kmap_atomic(from); 3172 vto = kmap_atomic(to); 3173 copy_user_page(vto, vfrom, vaddr, to); 3174 kunmap_atomic(vto); 3175 kunmap_atomic(vfrom); 3176 3177 /* If this page has ADI enabled, copy over any ADI tags 3178 * as well 3179 */ 3180 if (vma->vm_flags & VM_SPARC_ADI) { 3181 unsigned long pfrom, pto, i, adi_tag; 3182 3183 pfrom = page_to_phys(from); 3184 pto = page_to_phys(to); 3185 3186 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3187 asm volatile("ldxa [%1] %2, %0\n\t" 3188 : "=r" (adi_tag) 3189 : "r" (i), "i" (ASI_MCD_REAL)); 3190 asm volatile("stxa %0, [%1] %2\n\t" 3191 : 3192 : "r" (adi_tag), "r" (pto), 3193 "i" (ASI_MCD_REAL)); 3194 pto += adi_blksize(); 3195 } 3196 asm volatile("membar #Sync\n\t"); 3197 } 3198 } 3199 EXPORT_SYMBOL(copy_user_highpage); 3200 3201 void copy_highpage(struct page *to, struct page *from) 3202 { 3203 char *vfrom, *vto; 3204 3205 vfrom = kmap_atomic(from); 3206 vto = kmap_atomic(to); 3207 copy_page(vto, vfrom); 3208 kunmap_atomic(vto); 3209 kunmap_atomic(vfrom); 3210 3211 /* If this platform is ADI enabled, copy any ADI tags 3212 * as well 3213 */ 3214 if (adi_capable()) { 3215 unsigned long pfrom, pto, i, adi_tag; 3216 3217 pfrom = page_to_phys(from); 3218 pto = page_to_phys(to); 3219 3220 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3221 asm volatile("ldxa [%1] %2, %0\n\t" 3222 : "=r" (adi_tag) 3223 : "r" (i), "i" (ASI_MCD_REAL)); 3224 asm volatile("stxa %0, [%1] %2\n\t" 3225 : 3226 : "r" (adi_tag), "r" (pto), 3227 "i" (ASI_MCD_REAL)); 3228 pto += adi_blksize(); 3229 } 3230 asm volatile("membar #Sync\n\t"); 3231 } 3232 } 3233 EXPORT_SYMBOL(copy_highpage); 3234