1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch/sparc64/mm/init.c 4 * 5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #include <linux/extable.h> 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <linux/string.h> 13 #include <linux/init.h> 14 #include <linux/memblock.h> 15 #include <linux/mm.h> 16 #include <linux/hugetlb.h> 17 #include <linux/initrd.h> 18 #include <linux/swap.h> 19 #include <linux/pagemap.h> 20 #include <linux/poison.h> 21 #include <linux/fs.h> 22 #include <linux/seq_file.h> 23 #include <linux/kprobes.h> 24 #include <linux/cache.h> 25 #include <linux/sort.h> 26 #include <linux/ioport.h> 27 #include <linux/percpu.h> 28 #include <linux/mmzone.h> 29 #include <linux/gfp.h> 30 31 #include <asm/head.h> 32 #include <asm/page.h> 33 #include <asm/pgalloc.h> 34 #include <asm/oplib.h> 35 #include <asm/iommu.h> 36 #include <asm/io.h> 37 #include <linux/uaccess.h> 38 #include <asm/mmu_context.h> 39 #include <asm/tlbflush.h> 40 #include <asm/dma.h> 41 #include <asm/starfire.h> 42 #include <asm/tlb.h> 43 #include <asm/spitfire.h> 44 #include <asm/sections.h> 45 #include <asm/tsb.h> 46 #include <asm/hypervisor.h> 47 #include <asm/prom.h> 48 #include <asm/mdesc.h> 49 #include <asm/cpudata.h> 50 #include <asm/setup.h> 51 #include <asm/irq.h> 52 53 #include "init_64.h" 54 55 unsigned long kern_linear_pte_xor[4] __read_mostly; 56 static unsigned long page_cache4v_flag; 57 58 /* A bitmap, two bits for every 256MB of physical memory. These two 59 * bits determine what page size we use for kernel linear 60 * translations. They form an index into kern_linear_pte_xor[]. The 61 * value in the indexed slot is XOR'd with the TLB miss virtual 62 * address to form the resulting TTE. The mapping is: 63 * 64 * 0 ==> 4MB 65 * 1 ==> 256MB 66 * 2 ==> 2GB 67 * 3 ==> 16GB 68 * 69 * All sun4v chips support 256MB pages. Only SPARC-T4 and later 70 * support 2GB pages, and hopefully future cpus will support the 16GB 71 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there 72 * if these larger page sizes are not supported by the cpu. 73 * 74 * It would be nice to determine this from the machine description 75 * 'cpu' properties, but we need to have this table setup before the 76 * MDESC is initialized. 77 */ 78 79 #ifndef CONFIG_DEBUG_PAGEALLOC 80 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. 81 * Space is allocated for this right after the trap table in 82 * arch/sparc64/kernel/head.S 83 */ 84 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; 85 #endif 86 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; 87 88 static unsigned long cpu_pgsz_mask; 89 90 #define MAX_BANKS 1024 91 92 static struct linux_prom64_registers pavail[MAX_BANKS]; 93 static int pavail_ents; 94 95 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; 96 97 static int cmp_p64(const void *a, const void *b) 98 { 99 const struct linux_prom64_registers *x = a, *y = b; 100 101 if (x->phys_addr > y->phys_addr) 102 return 1; 103 if (x->phys_addr < y->phys_addr) 104 return -1; 105 return 0; 106 } 107 108 static void __init read_obp_memory(const char *property, 109 struct linux_prom64_registers *regs, 110 int *num_ents) 111 { 112 phandle node = prom_finddevice("/memory"); 113 int prop_size = prom_getproplen(node, property); 114 int ents, ret, i; 115 116 ents = prop_size / sizeof(struct linux_prom64_registers); 117 if (ents > MAX_BANKS) { 118 prom_printf("The machine has more %s property entries than " 119 "this kernel can support (%d).\n", 120 property, MAX_BANKS); 121 prom_halt(); 122 } 123 124 ret = prom_getproperty(node, property, (char *) regs, prop_size); 125 if (ret == -1) { 126 prom_printf("Couldn't get %s property from /memory.\n", 127 property); 128 prom_halt(); 129 } 130 131 /* Sanitize what we got from the firmware, by page aligning 132 * everything. 133 */ 134 for (i = 0; i < ents; i++) { 135 unsigned long base, size; 136 137 base = regs[i].phys_addr; 138 size = regs[i].reg_size; 139 140 size &= PAGE_MASK; 141 if (base & ~PAGE_MASK) { 142 unsigned long new_base = PAGE_ALIGN(base); 143 144 size -= new_base - base; 145 if ((long) size < 0L) 146 size = 0UL; 147 base = new_base; 148 } 149 if (size == 0UL) { 150 /* If it is empty, simply get rid of it. 151 * This simplifies the logic of the other 152 * functions that process these arrays. 153 */ 154 memmove(®s[i], ®s[i + 1], 155 (ents - i - 1) * sizeof(regs[0])); 156 i--; 157 ents--; 158 continue; 159 } 160 regs[i].phys_addr = base; 161 regs[i].reg_size = size; 162 } 163 164 *num_ents = ents; 165 166 sort(regs, ents, sizeof(struct linux_prom64_registers), 167 cmp_p64, NULL); 168 } 169 170 /* Kernel physical address base and size in bytes. */ 171 unsigned long kern_base __read_mostly; 172 unsigned long kern_size __read_mostly; 173 174 /* Initial ramdisk setup */ 175 extern unsigned long sparc_ramdisk_image64; 176 extern unsigned int sparc_ramdisk_image; 177 extern unsigned int sparc_ramdisk_size; 178 179 struct page *mem_map_zero __read_mostly; 180 EXPORT_SYMBOL(mem_map_zero); 181 182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; 183 184 unsigned long sparc64_kern_pri_context __read_mostly; 185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly; 186 unsigned long sparc64_kern_sec_context __read_mostly; 187 188 int num_kernel_image_mappings; 189 190 #ifdef CONFIG_DEBUG_DCFLUSH 191 atomic_t dcpage_flushes = ATOMIC_INIT(0); 192 #ifdef CONFIG_SMP 193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); 194 #endif 195 #endif 196 197 inline void flush_dcache_page_impl(struct page *page) 198 { 199 BUG_ON(tlb_type == hypervisor); 200 #ifdef CONFIG_DEBUG_DCFLUSH 201 atomic_inc(&dcpage_flushes); 202 #endif 203 204 #ifdef DCACHE_ALIASING_POSSIBLE 205 __flush_dcache_page(page_address(page), 206 ((tlb_type == spitfire) && 207 page_mapping_file(page) != NULL)); 208 #else 209 if (page_mapping_file(page) != NULL && 210 tlb_type == spitfire) 211 __flush_icache_page(__pa(page_address(page))); 212 #endif 213 } 214 215 #define PG_dcache_dirty PG_arch_1 216 #define PG_dcache_cpu_shift 32UL 217 #define PG_dcache_cpu_mask \ 218 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) 219 220 #define dcache_dirty_cpu(page) \ 221 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) 222 223 static inline void set_dcache_dirty(struct page *page, int this_cpu) 224 { 225 unsigned long mask = this_cpu; 226 unsigned long non_cpu_bits; 227 228 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); 229 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); 230 231 __asm__ __volatile__("1:\n\t" 232 "ldx [%2], %%g7\n\t" 233 "and %%g7, %1, %%g1\n\t" 234 "or %%g1, %0, %%g1\n\t" 235 "casx [%2], %%g7, %%g1\n\t" 236 "cmp %%g7, %%g1\n\t" 237 "bne,pn %%xcc, 1b\n\t" 238 " nop" 239 : /* no outputs */ 240 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) 241 : "g1", "g7"); 242 } 243 244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) 245 { 246 unsigned long mask = (1UL << PG_dcache_dirty); 247 248 __asm__ __volatile__("! test_and_clear_dcache_dirty\n" 249 "1:\n\t" 250 "ldx [%2], %%g7\n\t" 251 "srlx %%g7, %4, %%g1\n\t" 252 "and %%g1, %3, %%g1\n\t" 253 "cmp %%g1, %0\n\t" 254 "bne,pn %%icc, 2f\n\t" 255 " andn %%g7, %1, %%g1\n\t" 256 "casx [%2], %%g7, %%g1\n\t" 257 "cmp %%g7, %%g1\n\t" 258 "bne,pn %%xcc, 1b\n\t" 259 " nop\n" 260 "2:" 261 : /* no outputs */ 262 : "r" (cpu), "r" (mask), "r" (&page->flags), 263 "i" (PG_dcache_cpu_mask), 264 "i" (PG_dcache_cpu_shift) 265 : "g1", "g7"); 266 } 267 268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) 269 { 270 unsigned long tsb_addr = (unsigned long) ent; 271 272 if (tlb_type == cheetah_plus || tlb_type == hypervisor) 273 tsb_addr = __pa(tsb_addr); 274 275 __tsb_insert(tsb_addr, tag, pte); 276 } 277 278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly; 279 280 static void flush_dcache(unsigned long pfn) 281 { 282 struct page *page; 283 284 page = pfn_to_page(pfn); 285 if (page) { 286 unsigned long pg_flags; 287 288 pg_flags = page->flags; 289 if (pg_flags & (1UL << PG_dcache_dirty)) { 290 int cpu = ((pg_flags >> PG_dcache_cpu_shift) & 291 PG_dcache_cpu_mask); 292 int this_cpu = get_cpu(); 293 294 /* This is just to optimize away some function calls 295 * in the SMP case. 296 */ 297 if (cpu == this_cpu) 298 flush_dcache_page_impl(page); 299 else 300 smp_flush_dcache_page_impl(page, cpu); 301 302 clear_dcache_dirty_cpu(page, cpu); 303 304 put_cpu(); 305 } 306 } 307 } 308 309 /* mm->context.lock must be held */ 310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, 311 unsigned long tsb_hash_shift, unsigned long address, 312 unsigned long tte) 313 { 314 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; 315 unsigned long tag; 316 317 if (unlikely(!tsb)) 318 return; 319 320 tsb += ((address >> tsb_hash_shift) & 321 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); 322 tag = (address >> 22UL); 323 tsb_insert(tsb, tag, tte); 324 } 325 326 #ifdef CONFIG_HUGETLB_PAGE 327 static int __init hugetlbpage_init(void) 328 { 329 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT); 330 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT); 331 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT); 332 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT); 333 334 return 0; 335 } 336 337 arch_initcall(hugetlbpage_init); 338 339 static void __init pud_huge_patch(void) 340 { 341 struct pud_huge_patch_entry *p; 342 unsigned long addr; 343 344 p = &__pud_huge_patch; 345 addr = p->addr; 346 *(unsigned int *)addr = p->insn; 347 348 __asm__ __volatile__("flush %0" : : "r" (addr)); 349 } 350 351 bool __init arch_hugetlb_valid_size(unsigned long size) 352 { 353 unsigned int hugepage_shift = ilog2(size); 354 unsigned short hv_pgsz_idx; 355 unsigned int hv_pgsz_mask; 356 357 switch (hugepage_shift) { 358 case HPAGE_16GB_SHIFT: 359 hv_pgsz_mask = HV_PGSZ_MASK_16GB; 360 hv_pgsz_idx = HV_PGSZ_IDX_16GB; 361 pud_huge_patch(); 362 break; 363 case HPAGE_2GB_SHIFT: 364 hv_pgsz_mask = HV_PGSZ_MASK_2GB; 365 hv_pgsz_idx = HV_PGSZ_IDX_2GB; 366 break; 367 case HPAGE_256MB_SHIFT: 368 hv_pgsz_mask = HV_PGSZ_MASK_256MB; 369 hv_pgsz_idx = HV_PGSZ_IDX_256MB; 370 break; 371 case HPAGE_SHIFT: 372 hv_pgsz_mask = HV_PGSZ_MASK_4MB; 373 hv_pgsz_idx = HV_PGSZ_IDX_4MB; 374 break; 375 case HPAGE_64K_SHIFT: 376 hv_pgsz_mask = HV_PGSZ_MASK_64K; 377 hv_pgsz_idx = HV_PGSZ_IDX_64K; 378 break; 379 default: 380 hv_pgsz_mask = 0; 381 } 382 383 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) 384 return false; 385 386 return true; 387 } 388 #endif /* CONFIG_HUGETLB_PAGE */ 389 390 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) 391 { 392 struct mm_struct *mm; 393 unsigned long flags; 394 bool is_huge_tsb; 395 pte_t pte = *ptep; 396 397 if (tlb_type != hypervisor) { 398 unsigned long pfn = pte_pfn(pte); 399 400 if (pfn_valid(pfn)) 401 flush_dcache(pfn); 402 } 403 404 mm = vma->vm_mm; 405 406 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ 407 if (!pte_accessible(mm, pte)) 408 return; 409 410 spin_lock_irqsave(&mm->context.lock, flags); 411 412 is_huge_tsb = false; 413 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 414 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) { 415 unsigned long hugepage_size = PAGE_SIZE; 416 417 if (is_vm_hugetlb_page(vma)) 418 hugepage_size = huge_page_size(hstate_vma(vma)); 419 420 if (hugepage_size >= PUD_SIZE) { 421 unsigned long mask = 0x1ffc00000UL; 422 423 /* Transfer bits [32:22] from address to resolve 424 * at 4M granularity. 425 */ 426 pte_val(pte) &= ~mask; 427 pte_val(pte) |= (address & mask); 428 } else if (hugepage_size >= PMD_SIZE) { 429 /* We are fabricating 8MB pages using 4MB 430 * real hw pages. 431 */ 432 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); 433 } 434 435 if (hugepage_size >= PMD_SIZE) { 436 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, 437 REAL_HPAGE_SHIFT, address, pte_val(pte)); 438 is_huge_tsb = true; 439 } 440 } 441 #endif 442 if (!is_huge_tsb) 443 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, 444 address, pte_val(pte)); 445 446 spin_unlock_irqrestore(&mm->context.lock, flags); 447 } 448 449 void flush_dcache_page(struct page *page) 450 { 451 struct address_space *mapping; 452 int this_cpu; 453 454 if (tlb_type == hypervisor) 455 return; 456 457 /* Do not bother with the expensive D-cache flush if it 458 * is merely the zero page. The 'bigcore' testcase in GDB 459 * causes this case to run millions of times. 460 */ 461 if (page == ZERO_PAGE(0)) 462 return; 463 464 this_cpu = get_cpu(); 465 466 mapping = page_mapping_file(page); 467 if (mapping && !mapping_mapped(mapping)) { 468 int dirty = test_bit(PG_dcache_dirty, &page->flags); 469 if (dirty) { 470 int dirty_cpu = dcache_dirty_cpu(page); 471 472 if (dirty_cpu == this_cpu) 473 goto out; 474 smp_flush_dcache_page_impl(page, dirty_cpu); 475 } 476 set_dcache_dirty(page, this_cpu); 477 } else { 478 /* We could delay the flush for the !page_mapping 479 * case too. But that case is for exec env/arg 480 * pages and those are %99 certainly going to get 481 * faulted into the tlb (and thus flushed) anyways. 482 */ 483 flush_dcache_page_impl(page); 484 } 485 486 out: 487 put_cpu(); 488 } 489 EXPORT_SYMBOL(flush_dcache_page); 490 491 void __kprobes flush_icache_range(unsigned long start, unsigned long end) 492 { 493 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ 494 if (tlb_type == spitfire) { 495 unsigned long kaddr; 496 497 /* This code only runs on Spitfire cpus so this is 498 * why we can assume _PAGE_PADDR_4U. 499 */ 500 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { 501 unsigned long paddr, mask = _PAGE_PADDR_4U; 502 503 if (kaddr >= PAGE_OFFSET) 504 paddr = kaddr & mask; 505 else { 506 pte_t *ptep = virt_to_kpte(kaddr); 507 508 paddr = pte_val(*ptep) & mask; 509 } 510 __flush_icache_page(paddr); 511 } 512 } 513 } 514 EXPORT_SYMBOL(flush_icache_range); 515 516 void mmu_info(struct seq_file *m) 517 { 518 static const char *pgsz_strings[] = { 519 "8K", "64K", "512K", "4MB", "32MB", 520 "256MB", "2GB", "16GB", 521 }; 522 int i, printed; 523 524 if (tlb_type == cheetah) 525 seq_printf(m, "MMU Type\t: Cheetah\n"); 526 else if (tlb_type == cheetah_plus) 527 seq_printf(m, "MMU Type\t: Cheetah+\n"); 528 else if (tlb_type == spitfire) 529 seq_printf(m, "MMU Type\t: Spitfire\n"); 530 else if (tlb_type == hypervisor) 531 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); 532 else 533 seq_printf(m, "MMU Type\t: ???\n"); 534 535 seq_printf(m, "MMU PGSZs\t: "); 536 printed = 0; 537 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { 538 if (cpu_pgsz_mask & (1UL << i)) { 539 seq_printf(m, "%s%s", 540 printed ? "," : "", pgsz_strings[i]); 541 printed++; 542 } 543 } 544 seq_putc(m, '\n'); 545 546 #ifdef CONFIG_DEBUG_DCFLUSH 547 seq_printf(m, "DCPageFlushes\t: %d\n", 548 atomic_read(&dcpage_flushes)); 549 #ifdef CONFIG_SMP 550 seq_printf(m, "DCPageFlushesXC\t: %d\n", 551 atomic_read(&dcpage_flushes_xcall)); 552 #endif /* CONFIG_SMP */ 553 #endif /* CONFIG_DEBUG_DCFLUSH */ 554 } 555 556 struct linux_prom_translation prom_trans[512] __read_mostly; 557 unsigned int prom_trans_ents __read_mostly; 558 559 unsigned long kern_locked_tte_data; 560 561 /* The obp translations are saved based on 8k pagesize, since obp can 562 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> 563 * HI_OBP_ADDRESS range are handled in ktlb.S. 564 */ 565 static inline int in_obp_range(unsigned long vaddr) 566 { 567 return (vaddr >= LOW_OBP_ADDRESS && 568 vaddr < HI_OBP_ADDRESS); 569 } 570 571 static int cmp_ptrans(const void *a, const void *b) 572 { 573 const struct linux_prom_translation *x = a, *y = b; 574 575 if (x->virt > y->virt) 576 return 1; 577 if (x->virt < y->virt) 578 return -1; 579 return 0; 580 } 581 582 /* Read OBP translations property into 'prom_trans[]'. */ 583 static void __init read_obp_translations(void) 584 { 585 int n, node, ents, first, last, i; 586 587 node = prom_finddevice("/virtual-memory"); 588 n = prom_getproplen(node, "translations"); 589 if (unlikely(n == 0 || n == -1)) { 590 prom_printf("prom_mappings: Couldn't get size.\n"); 591 prom_halt(); 592 } 593 if (unlikely(n > sizeof(prom_trans))) { 594 prom_printf("prom_mappings: Size %d is too big.\n", n); 595 prom_halt(); 596 } 597 598 if ((n = prom_getproperty(node, "translations", 599 (char *)&prom_trans[0], 600 sizeof(prom_trans))) == -1) { 601 prom_printf("prom_mappings: Couldn't get property.\n"); 602 prom_halt(); 603 } 604 605 n = n / sizeof(struct linux_prom_translation); 606 607 ents = n; 608 609 sort(prom_trans, ents, sizeof(struct linux_prom_translation), 610 cmp_ptrans, NULL); 611 612 /* Now kick out all the non-OBP entries. */ 613 for (i = 0; i < ents; i++) { 614 if (in_obp_range(prom_trans[i].virt)) 615 break; 616 } 617 first = i; 618 for (; i < ents; i++) { 619 if (!in_obp_range(prom_trans[i].virt)) 620 break; 621 } 622 last = i; 623 624 for (i = 0; i < (last - first); i++) { 625 struct linux_prom_translation *src = &prom_trans[i + first]; 626 struct linux_prom_translation *dest = &prom_trans[i]; 627 628 *dest = *src; 629 } 630 for (; i < ents; i++) { 631 struct linux_prom_translation *dest = &prom_trans[i]; 632 dest->virt = dest->size = dest->data = 0x0UL; 633 } 634 635 prom_trans_ents = last - first; 636 637 if (tlb_type == spitfire) { 638 /* Clear diag TTE bits. */ 639 for (i = 0; i < prom_trans_ents; i++) 640 prom_trans[i].data &= ~0x0003fe0000000000UL; 641 } 642 643 /* Force execute bit on. */ 644 for (i = 0; i < prom_trans_ents; i++) 645 prom_trans[i].data |= (tlb_type == hypervisor ? 646 _PAGE_EXEC_4V : _PAGE_EXEC_4U); 647 } 648 649 static void __init hypervisor_tlb_lock(unsigned long vaddr, 650 unsigned long pte, 651 unsigned long mmu) 652 { 653 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); 654 655 if (ret != 0) { 656 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " 657 "errors with %lx\n", vaddr, 0, pte, mmu, ret); 658 prom_halt(); 659 } 660 } 661 662 static unsigned long kern_large_tte(unsigned long paddr); 663 664 static void __init remap_kernel(void) 665 { 666 unsigned long phys_page, tte_vaddr, tte_data; 667 int i, tlb_ent = sparc64_highest_locked_tlbent(); 668 669 tte_vaddr = (unsigned long) KERNBASE; 670 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 671 tte_data = kern_large_tte(phys_page); 672 673 kern_locked_tte_data = tte_data; 674 675 /* Now lock us into the TLBs via Hypervisor or OBP. */ 676 if (tlb_type == hypervisor) { 677 for (i = 0; i < num_kernel_image_mappings; i++) { 678 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); 679 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); 680 tte_vaddr += 0x400000; 681 tte_data += 0x400000; 682 } 683 } else { 684 for (i = 0; i < num_kernel_image_mappings; i++) { 685 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); 686 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); 687 tte_vaddr += 0x400000; 688 tte_data += 0x400000; 689 } 690 sparc64_highest_unlocked_tlb_ent = tlb_ent - i; 691 } 692 if (tlb_type == cheetah_plus) { 693 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | 694 CTX_CHEETAH_PLUS_NUC); 695 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; 696 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; 697 } 698 } 699 700 701 static void __init inherit_prom_mappings(void) 702 { 703 /* Now fixup OBP's idea about where we really are mapped. */ 704 printk("Remapping the kernel... "); 705 remap_kernel(); 706 printk("done.\n"); 707 } 708 709 void prom_world(int enter) 710 { 711 if (!enter) 712 set_fs(get_fs()); 713 714 __asm__ __volatile__("flushw"); 715 } 716 717 void __flush_dcache_range(unsigned long start, unsigned long end) 718 { 719 unsigned long va; 720 721 if (tlb_type == spitfire) { 722 int n = 0; 723 724 for (va = start; va < end; va += 32) { 725 spitfire_put_dcache_tag(va & 0x3fe0, 0x0); 726 if (++n >= 512) 727 break; 728 } 729 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 730 start = __pa(start); 731 end = __pa(end); 732 for (va = start; va < end; va += 32) 733 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 734 "membar #Sync" 735 : /* no outputs */ 736 : "r" (va), 737 "i" (ASI_DCACHE_INVALIDATE)); 738 } 739 } 740 EXPORT_SYMBOL(__flush_dcache_range); 741 742 /* get_new_mmu_context() uses "cache + 1". */ 743 DEFINE_SPINLOCK(ctx_alloc_lock); 744 unsigned long tlb_context_cache = CTX_FIRST_VERSION; 745 #define MAX_CTX_NR (1UL << CTX_NR_BITS) 746 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) 747 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); 748 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0}; 749 750 static void mmu_context_wrap(void) 751 { 752 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK; 753 unsigned long new_ver, new_ctx, old_ctx; 754 struct mm_struct *mm; 755 int cpu; 756 757 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS); 758 759 /* Reserve kernel context */ 760 set_bit(0, mmu_context_bmap); 761 762 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION; 763 if (unlikely(new_ver == 0)) 764 new_ver = CTX_FIRST_VERSION; 765 tlb_context_cache = new_ver; 766 767 /* 768 * Make sure that any new mm that are added into per_cpu_secondary_mm, 769 * are going to go through get_new_mmu_context() path. 770 */ 771 mb(); 772 773 /* 774 * Updated versions to current on those CPUs that had valid secondary 775 * contexts 776 */ 777 for_each_online_cpu(cpu) { 778 /* 779 * If a new mm is stored after we took this mm from the array, 780 * it will go into get_new_mmu_context() path, because we 781 * already bumped the version in tlb_context_cache. 782 */ 783 mm = per_cpu(per_cpu_secondary_mm, cpu); 784 785 if (unlikely(!mm || mm == &init_mm)) 786 continue; 787 788 old_ctx = mm->context.sparc64_ctx_val; 789 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) { 790 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver; 791 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap); 792 mm->context.sparc64_ctx_val = new_ctx; 793 } 794 } 795 } 796 797 /* Caller does TLB context flushing on local CPU if necessary. 798 * The caller also ensures that CTX_VALID(mm->context) is false. 799 * 800 * We must be careful about boundary cases so that we never 801 * let the user have CTX 0 (nucleus) or we ever use a CTX 802 * version of zero (and thus NO_CONTEXT would not be caught 803 * by version mis-match tests in mmu_context.h). 804 * 805 * Always invoked with interrupts disabled. 806 */ 807 void get_new_mmu_context(struct mm_struct *mm) 808 { 809 unsigned long ctx, new_ctx; 810 unsigned long orig_pgsz_bits; 811 812 spin_lock(&ctx_alloc_lock); 813 retry: 814 /* wrap might have happened, test again if our context became valid */ 815 if (unlikely(CTX_VALID(mm->context))) 816 goto out; 817 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); 818 ctx = (tlb_context_cache + 1) & CTX_NR_MASK; 819 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); 820 if (new_ctx >= (1 << CTX_NR_BITS)) { 821 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); 822 if (new_ctx >= ctx) { 823 mmu_context_wrap(); 824 goto retry; 825 } 826 } 827 if (mm->context.sparc64_ctx_val) 828 cpumask_clear(mm_cpumask(mm)); 829 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); 830 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); 831 tlb_context_cache = new_ctx; 832 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; 833 out: 834 spin_unlock(&ctx_alloc_lock); 835 } 836 837 static int numa_enabled = 1; 838 static int numa_debug; 839 840 static int __init early_numa(char *p) 841 { 842 if (!p) 843 return 0; 844 845 if (strstr(p, "off")) 846 numa_enabled = 0; 847 848 if (strstr(p, "debug")) 849 numa_debug = 1; 850 851 return 0; 852 } 853 early_param("numa", early_numa); 854 855 #define numadbg(f, a...) \ 856 do { if (numa_debug) \ 857 printk(KERN_INFO f, ## a); \ 858 } while (0) 859 860 static void __init find_ramdisk(unsigned long phys_base) 861 { 862 #ifdef CONFIG_BLK_DEV_INITRD 863 if (sparc_ramdisk_image || sparc_ramdisk_image64) { 864 unsigned long ramdisk_image; 865 866 /* Older versions of the bootloader only supported a 867 * 32-bit physical address for the ramdisk image 868 * location, stored at sparc_ramdisk_image. Newer 869 * SILO versions set sparc_ramdisk_image to zero and 870 * provide a full 64-bit physical address at 871 * sparc_ramdisk_image64. 872 */ 873 ramdisk_image = sparc_ramdisk_image; 874 if (!ramdisk_image) 875 ramdisk_image = sparc_ramdisk_image64; 876 877 /* Another bootloader quirk. The bootloader normalizes 878 * the physical address to KERNBASE, so we have to 879 * factor that back out and add in the lowest valid 880 * physical page address to get the true physical address. 881 */ 882 ramdisk_image -= KERNBASE; 883 ramdisk_image += phys_base; 884 885 numadbg("Found ramdisk at physical address 0x%lx, size %u\n", 886 ramdisk_image, sparc_ramdisk_size); 887 888 initrd_start = ramdisk_image; 889 initrd_end = ramdisk_image + sparc_ramdisk_size; 890 891 memblock_reserve(initrd_start, sparc_ramdisk_size); 892 893 initrd_start += PAGE_OFFSET; 894 initrd_end += PAGE_OFFSET; 895 } 896 #endif 897 } 898 899 struct node_mem_mask { 900 unsigned long mask; 901 unsigned long match; 902 }; 903 static struct node_mem_mask node_masks[MAX_NUMNODES]; 904 static int num_node_masks; 905 906 #ifdef CONFIG_NEED_MULTIPLE_NODES 907 908 struct mdesc_mlgroup { 909 u64 node; 910 u64 latency; 911 u64 match; 912 u64 mask; 913 }; 914 915 static struct mdesc_mlgroup *mlgroups; 916 static int num_mlgroups; 917 918 int numa_cpu_lookup_table[NR_CPUS]; 919 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; 920 921 struct mdesc_mblock { 922 u64 base; 923 u64 size; 924 u64 offset; /* RA-to-PA */ 925 }; 926 static struct mdesc_mblock *mblocks; 927 static int num_mblocks; 928 929 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr) 930 { 931 struct mdesc_mblock *m = NULL; 932 int i; 933 934 for (i = 0; i < num_mblocks; i++) { 935 m = &mblocks[i]; 936 937 if (addr >= m->base && 938 addr < (m->base + m->size)) { 939 break; 940 } 941 } 942 943 return m; 944 } 945 946 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid) 947 { 948 int prev_nid, new_nid; 949 950 prev_nid = NUMA_NO_NODE; 951 for ( ; start < end; start += PAGE_SIZE) { 952 for (new_nid = 0; new_nid < num_node_masks; new_nid++) { 953 struct node_mem_mask *p = &node_masks[new_nid]; 954 955 if ((start & p->mask) == p->match) { 956 if (prev_nid == NUMA_NO_NODE) 957 prev_nid = new_nid; 958 break; 959 } 960 } 961 962 if (new_nid == num_node_masks) { 963 prev_nid = 0; 964 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.", 965 start); 966 break; 967 } 968 969 if (prev_nid != new_nid) 970 break; 971 } 972 *nid = prev_nid; 973 974 return start > end ? end : start; 975 } 976 977 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid) 978 { 979 u64 ret_end, pa_start, m_mask, m_match, m_end; 980 struct mdesc_mblock *mblock; 981 int _nid, i; 982 983 if (tlb_type != hypervisor) 984 return memblock_nid_range_sun4u(start, end, nid); 985 986 mblock = addr_to_mblock(start); 987 if (!mblock) { 988 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]", 989 start); 990 991 _nid = 0; 992 ret_end = end; 993 goto done; 994 } 995 996 pa_start = start + mblock->offset; 997 m_match = 0; 998 m_mask = 0; 999 1000 for (_nid = 0; _nid < num_node_masks; _nid++) { 1001 struct node_mem_mask *const m = &node_masks[_nid]; 1002 1003 if ((pa_start & m->mask) == m->match) { 1004 m_match = m->match; 1005 m_mask = m->mask; 1006 break; 1007 } 1008 } 1009 1010 if (num_node_masks == _nid) { 1011 /* We could not find NUMA group, so default to 0, but lets 1012 * search for latency group, so we could calculate the correct 1013 * end address that we return 1014 */ 1015 _nid = 0; 1016 1017 for (i = 0; i < num_mlgroups; i++) { 1018 struct mdesc_mlgroup *const m = &mlgroups[i]; 1019 1020 if ((pa_start & m->mask) == m->match) { 1021 m_match = m->match; 1022 m_mask = m->mask; 1023 break; 1024 } 1025 } 1026 1027 if (i == num_mlgroups) { 1028 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]", 1029 start); 1030 1031 ret_end = end; 1032 goto done; 1033 } 1034 } 1035 1036 /* 1037 * Each latency group has match and mask, and each memory block has an 1038 * offset. An address belongs to a latency group if its address matches 1039 * the following formula: ((addr + offset) & mask) == match 1040 * It is, however, slow to check every single page if it matches a 1041 * particular latency group. As optimization we calculate end value by 1042 * using bit arithmetics. 1043 */ 1044 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset; 1045 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1); 1046 ret_end = m_end > end ? end : m_end; 1047 1048 done: 1049 *nid = _nid; 1050 return ret_end; 1051 } 1052 #endif 1053 1054 /* This must be invoked after performing all of the necessary 1055 * memblock_set_node() calls for 'nid'. We need to be able to get 1056 * correct data from get_pfn_range_for_nid(). 1057 */ 1058 static void __init allocate_node_data(int nid) 1059 { 1060 struct pglist_data *p; 1061 unsigned long start_pfn, end_pfn; 1062 #ifdef CONFIG_NEED_MULTIPLE_NODES 1063 1064 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data), 1065 SMP_CACHE_BYTES, nid); 1066 if (!NODE_DATA(nid)) { 1067 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); 1068 prom_halt(); 1069 } 1070 1071 NODE_DATA(nid)->node_id = nid; 1072 #endif 1073 1074 p = NODE_DATA(nid); 1075 1076 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); 1077 p->node_start_pfn = start_pfn; 1078 p->node_spanned_pages = end_pfn - start_pfn; 1079 } 1080 1081 static void init_node_masks_nonnuma(void) 1082 { 1083 #ifdef CONFIG_NEED_MULTIPLE_NODES 1084 int i; 1085 #endif 1086 1087 numadbg("Initializing tables for non-numa.\n"); 1088 1089 node_masks[0].mask = 0; 1090 node_masks[0].match = 0; 1091 num_node_masks = 1; 1092 1093 #ifdef CONFIG_NEED_MULTIPLE_NODES 1094 for (i = 0; i < NR_CPUS; i++) 1095 numa_cpu_lookup_table[i] = 0; 1096 1097 cpumask_setall(&numa_cpumask_lookup_table[0]); 1098 #endif 1099 } 1100 1101 #ifdef CONFIG_NEED_MULTIPLE_NODES 1102 struct pglist_data *node_data[MAX_NUMNODES]; 1103 1104 EXPORT_SYMBOL(numa_cpu_lookup_table); 1105 EXPORT_SYMBOL(numa_cpumask_lookup_table); 1106 EXPORT_SYMBOL(node_data); 1107 1108 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, 1109 u32 cfg_handle) 1110 { 1111 u64 arc; 1112 1113 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { 1114 u64 target = mdesc_arc_target(md, arc); 1115 const u64 *val; 1116 1117 val = mdesc_get_property(md, target, 1118 "cfg-handle", NULL); 1119 if (val && *val == cfg_handle) 1120 return 0; 1121 } 1122 return -ENODEV; 1123 } 1124 1125 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, 1126 u32 cfg_handle) 1127 { 1128 u64 arc, candidate, best_latency = ~(u64)0; 1129 1130 candidate = MDESC_NODE_NULL; 1131 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1132 u64 target = mdesc_arc_target(md, arc); 1133 const char *name = mdesc_node_name(md, target); 1134 const u64 *val; 1135 1136 if (strcmp(name, "pio-latency-group")) 1137 continue; 1138 1139 val = mdesc_get_property(md, target, "latency", NULL); 1140 if (!val) 1141 continue; 1142 1143 if (*val < best_latency) { 1144 candidate = target; 1145 best_latency = *val; 1146 } 1147 } 1148 1149 if (candidate == MDESC_NODE_NULL) 1150 return -ENODEV; 1151 1152 return scan_pio_for_cfg_handle(md, candidate, cfg_handle); 1153 } 1154 1155 int of_node_to_nid(struct device_node *dp) 1156 { 1157 const struct linux_prom64_registers *regs; 1158 struct mdesc_handle *md; 1159 u32 cfg_handle; 1160 int count, nid; 1161 u64 grp; 1162 1163 /* This is the right thing to do on currently supported 1164 * SUN4U NUMA platforms as well, as the PCI controller does 1165 * not sit behind any particular memory controller. 1166 */ 1167 if (!mlgroups) 1168 return -1; 1169 1170 regs = of_get_property(dp, "reg", NULL); 1171 if (!regs) 1172 return -1; 1173 1174 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; 1175 1176 md = mdesc_grab(); 1177 1178 count = 0; 1179 nid = NUMA_NO_NODE; 1180 mdesc_for_each_node_by_name(md, grp, "group") { 1181 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { 1182 nid = count; 1183 break; 1184 } 1185 count++; 1186 } 1187 1188 mdesc_release(md); 1189 1190 return nid; 1191 } 1192 1193 static void __init add_node_ranges(void) 1194 { 1195 struct memblock_region *reg; 1196 unsigned long prev_max; 1197 1198 memblock_resized: 1199 prev_max = memblock.memory.max; 1200 1201 for_each_memblock(memory, reg) { 1202 unsigned long size = reg->size; 1203 unsigned long start, end; 1204 1205 start = reg->base; 1206 end = start + size; 1207 while (start < end) { 1208 unsigned long this_end; 1209 int nid; 1210 1211 this_end = memblock_nid_range(start, end, &nid); 1212 1213 numadbg("Setting memblock NUMA node nid[%d] " 1214 "start[%lx] end[%lx]\n", 1215 nid, start, this_end); 1216 1217 memblock_set_node(start, this_end - start, 1218 &memblock.memory, nid); 1219 if (memblock.memory.max != prev_max) 1220 goto memblock_resized; 1221 start = this_end; 1222 } 1223 } 1224 } 1225 1226 static int __init grab_mlgroups(struct mdesc_handle *md) 1227 { 1228 unsigned long paddr; 1229 int count = 0; 1230 u64 node; 1231 1232 mdesc_for_each_node_by_name(md, node, "memory-latency-group") 1233 count++; 1234 if (!count) 1235 return -ENOENT; 1236 1237 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup), 1238 SMP_CACHE_BYTES); 1239 if (!paddr) 1240 return -ENOMEM; 1241 1242 mlgroups = __va(paddr); 1243 num_mlgroups = count; 1244 1245 count = 0; 1246 mdesc_for_each_node_by_name(md, node, "memory-latency-group") { 1247 struct mdesc_mlgroup *m = &mlgroups[count++]; 1248 const u64 *val; 1249 1250 m->node = node; 1251 1252 val = mdesc_get_property(md, node, "latency", NULL); 1253 m->latency = *val; 1254 val = mdesc_get_property(md, node, "address-match", NULL); 1255 m->match = *val; 1256 val = mdesc_get_property(md, node, "address-mask", NULL); 1257 m->mask = *val; 1258 1259 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " 1260 "match[%llx] mask[%llx]\n", 1261 count - 1, m->node, m->latency, m->match, m->mask); 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int __init grab_mblocks(struct mdesc_handle *md) 1268 { 1269 unsigned long paddr; 1270 int count = 0; 1271 u64 node; 1272 1273 mdesc_for_each_node_by_name(md, node, "mblock") 1274 count++; 1275 if (!count) 1276 return -ENOENT; 1277 1278 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock), 1279 SMP_CACHE_BYTES); 1280 if (!paddr) 1281 return -ENOMEM; 1282 1283 mblocks = __va(paddr); 1284 num_mblocks = count; 1285 1286 count = 0; 1287 mdesc_for_each_node_by_name(md, node, "mblock") { 1288 struct mdesc_mblock *m = &mblocks[count++]; 1289 const u64 *val; 1290 1291 val = mdesc_get_property(md, node, "base", NULL); 1292 m->base = *val; 1293 val = mdesc_get_property(md, node, "size", NULL); 1294 m->size = *val; 1295 val = mdesc_get_property(md, node, 1296 "address-congruence-offset", NULL); 1297 1298 /* The address-congruence-offset property is optional. 1299 * Explicity zero it be identifty this. 1300 */ 1301 if (val) 1302 m->offset = *val; 1303 else 1304 m->offset = 0UL; 1305 1306 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", 1307 count - 1, m->base, m->size, m->offset); 1308 } 1309 1310 return 0; 1311 } 1312 1313 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, 1314 u64 grp, cpumask_t *mask) 1315 { 1316 u64 arc; 1317 1318 cpumask_clear(mask); 1319 1320 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { 1321 u64 target = mdesc_arc_target(md, arc); 1322 const char *name = mdesc_node_name(md, target); 1323 const u64 *id; 1324 1325 if (strcmp(name, "cpu")) 1326 continue; 1327 id = mdesc_get_property(md, target, "id", NULL); 1328 if (*id < nr_cpu_ids) 1329 cpumask_set_cpu(*id, mask); 1330 } 1331 } 1332 1333 static struct mdesc_mlgroup * __init find_mlgroup(u64 node) 1334 { 1335 int i; 1336 1337 for (i = 0; i < num_mlgroups; i++) { 1338 struct mdesc_mlgroup *m = &mlgroups[i]; 1339 if (m->node == node) 1340 return m; 1341 } 1342 return NULL; 1343 } 1344 1345 int __node_distance(int from, int to) 1346 { 1347 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { 1348 pr_warn("Returning default NUMA distance value for %d->%d\n", 1349 from, to); 1350 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; 1351 } 1352 return numa_latency[from][to]; 1353 } 1354 EXPORT_SYMBOL(__node_distance); 1355 1356 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) 1357 { 1358 int i; 1359 1360 for (i = 0; i < MAX_NUMNODES; i++) { 1361 struct node_mem_mask *n = &node_masks[i]; 1362 1363 if ((grp->mask == n->mask) && (grp->match == n->match)) 1364 break; 1365 } 1366 return i; 1367 } 1368 1369 static void __init find_numa_latencies_for_group(struct mdesc_handle *md, 1370 u64 grp, int index) 1371 { 1372 u64 arc; 1373 1374 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1375 int tnode; 1376 u64 target = mdesc_arc_target(md, arc); 1377 struct mdesc_mlgroup *m = find_mlgroup(target); 1378 1379 if (!m) 1380 continue; 1381 tnode = find_best_numa_node_for_mlgroup(m); 1382 if (tnode == MAX_NUMNODES) 1383 continue; 1384 numa_latency[index][tnode] = m->latency; 1385 } 1386 } 1387 1388 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, 1389 int index) 1390 { 1391 struct mdesc_mlgroup *candidate = NULL; 1392 u64 arc, best_latency = ~(u64)0; 1393 struct node_mem_mask *n; 1394 1395 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { 1396 u64 target = mdesc_arc_target(md, arc); 1397 struct mdesc_mlgroup *m = find_mlgroup(target); 1398 if (!m) 1399 continue; 1400 if (m->latency < best_latency) { 1401 candidate = m; 1402 best_latency = m->latency; 1403 } 1404 } 1405 if (!candidate) 1406 return -ENOENT; 1407 1408 if (num_node_masks != index) { 1409 printk(KERN_ERR "Inconsistent NUMA state, " 1410 "index[%d] != num_node_masks[%d]\n", 1411 index, num_node_masks); 1412 return -EINVAL; 1413 } 1414 1415 n = &node_masks[num_node_masks++]; 1416 1417 n->mask = candidate->mask; 1418 n->match = candidate->match; 1419 1420 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n", 1421 index, n->mask, n->match, candidate->latency); 1422 1423 return 0; 1424 } 1425 1426 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, 1427 int index) 1428 { 1429 cpumask_t mask; 1430 int cpu; 1431 1432 numa_parse_mdesc_group_cpus(md, grp, &mask); 1433 1434 for_each_cpu(cpu, &mask) 1435 numa_cpu_lookup_table[cpu] = index; 1436 cpumask_copy(&numa_cpumask_lookup_table[index], &mask); 1437 1438 if (numa_debug) { 1439 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); 1440 for_each_cpu(cpu, &mask) 1441 printk("%d ", cpu); 1442 printk("]\n"); 1443 } 1444 1445 return numa_attach_mlgroup(md, grp, index); 1446 } 1447 1448 static int __init numa_parse_mdesc(void) 1449 { 1450 struct mdesc_handle *md = mdesc_grab(); 1451 int i, j, err, count; 1452 u64 node; 1453 1454 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); 1455 if (node == MDESC_NODE_NULL) { 1456 mdesc_release(md); 1457 return -ENOENT; 1458 } 1459 1460 err = grab_mblocks(md); 1461 if (err < 0) 1462 goto out; 1463 1464 err = grab_mlgroups(md); 1465 if (err < 0) 1466 goto out; 1467 1468 count = 0; 1469 mdesc_for_each_node_by_name(md, node, "group") { 1470 err = numa_parse_mdesc_group(md, node, count); 1471 if (err < 0) 1472 break; 1473 count++; 1474 } 1475 1476 count = 0; 1477 mdesc_for_each_node_by_name(md, node, "group") { 1478 find_numa_latencies_for_group(md, node, count); 1479 count++; 1480 } 1481 1482 /* Normalize numa latency matrix according to ACPI SLIT spec. */ 1483 for (i = 0; i < MAX_NUMNODES; i++) { 1484 u64 self_latency = numa_latency[i][i]; 1485 1486 for (j = 0; j < MAX_NUMNODES; j++) { 1487 numa_latency[i][j] = 1488 (numa_latency[i][j] * LOCAL_DISTANCE) / 1489 self_latency; 1490 } 1491 } 1492 1493 add_node_ranges(); 1494 1495 for (i = 0; i < num_node_masks; i++) { 1496 allocate_node_data(i); 1497 node_set_online(i); 1498 } 1499 1500 err = 0; 1501 out: 1502 mdesc_release(md); 1503 return err; 1504 } 1505 1506 static int __init numa_parse_jbus(void) 1507 { 1508 unsigned long cpu, index; 1509 1510 /* NUMA node id is encoded in bits 36 and higher, and there is 1511 * a 1-to-1 mapping from CPU ID to NUMA node ID. 1512 */ 1513 index = 0; 1514 for_each_present_cpu(cpu) { 1515 numa_cpu_lookup_table[cpu] = index; 1516 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); 1517 node_masks[index].mask = ~((1UL << 36UL) - 1UL); 1518 node_masks[index].match = cpu << 36UL; 1519 1520 index++; 1521 } 1522 num_node_masks = index; 1523 1524 add_node_ranges(); 1525 1526 for (index = 0; index < num_node_masks; index++) { 1527 allocate_node_data(index); 1528 node_set_online(index); 1529 } 1530 1531 return 0; 1532 } 1533 1534 static int __init numa_parse_sun4u(void) 1535 { 1536 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1537 unsigned long ver; 1538 1539 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 1540 if ((ver >> 32UL) == __JALAPENO_ID || 1541 (ver >> 32UL) == __SERRANO_ID) 1542 return numa_parse_jbus(); 1543 } 1544 return -1; 1545 } 1546 1547 static int __init bootmem_init_numa(void) 1548 { 1549 int i, j; 1550 int err = -1; 1551 1552 numadbg("bootmem_init_numa()\n"); 1553 1554 /* Some sane defaults for numa latency values */ 1555 for (i = 0; i < MAX_NUMNODES; i++) { 1556 for (j = 0; j < MAX_NUMNODES; j++) 1557 numa_latency[i][j] = (i == j) ? 1558 LOCAL_DISTANCE : REMOTE_DISTANCE; 1559 } 1560 1561 if (numa_enabled) { 1562 if (tlb_type == hypervisor) 1563 err = numa_parse_mdesc(); 1564 else 1565 err = numa_parse_sun4u(); 1566 } 1567 return err; 1568 } 1569 1570 #else 1571 1572 static int bootmem_init_numa(void) 1573 { 1574 return -1; 1575 } 1576 1577 #endif 1578 1579 static void __init bootmem_init_nonnuma(void) 1580 { 1581 unsigned long top_of_ram = memblock_end_of_DRAM(); 1582 unsigned long total_ram = memblock_phys_mem_size(); 1583 1584 numadbg("bootmem_init_nonnuma()\n"); 1585 1586 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", 1587 top_of_ram, total_ram); 1588 printk(KERN_INFO "Memory hole size: %ldMB\n", 1589 (top_of_ram - total_ram) >> 20); 1590 1591 init_node_masks_nonnuma(); 1592 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0); 1593 allocate_node_data(0); 1594 node_set_online(0); 1595 } 1596 1597 static unsigned long __init bootmem_init(unsigned long phys_base) 1598 { 1599 unsigned long end_pfn; 1600 1601 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; 1602 max_pfn = max_low_pfn = end_pfn; 1603 min_low_pfn = (phys_base >> PAGE_SHIFT); 1604 1605 if (bootmem_init_numa() < 0) 1606 bootmem_init_nonnuma(); 1607 1608 /* Dump memblock with node info. */ 1609 memblock_dump_all(); 1610 1611 /* XXX cpu notifier XXX */ 1612 1613 sparse_memory_present_with_active_regions(MAX_NUMNODES); 1614 sparse_init(); 1615 1616 return end_pfn; 1617 } 1618 1619 static struct linux_prom64_registers pall[MAX_BANKS] __initdata; 1620 static int pall_ents __initdata; 1621 1622 static unsigned long max_phys_bits = 40; 1623 1624 bool kern_addr_valid(unsigned long addr) 1625 { 1626 pgd_t *pgd; 1627 p4d_t *p4d; 1628 pud_t *pud; 1629 pmd_t *pmd; 1630 pte_t *pte; 1631 1632 if ((long)addr < 0L) { 1633 unsigned long pa = __pa(addr); 1634 1635 if ((pa >> max_phys_bits) != 0UL) 1636 return false; 1637 1638 return pfn_valid(pa >> PAGE_SHIFT); 1639 } 1640 1641 if (addr >= (unsigned long) KERNBASE && 1642 addr < (unsigned long)&_end) 1643 return true; 1644 1645 pgd = pgd_offset_k(addr); 1646 if (pgd_none(*pgd)) 1647 return false; 1648 1649 p4d = p4d_offset(pgd, addr); 1650 if (p4d_none(*p4d)) 1651 return false; 1652 1653 pud = pud_offset(p4d, addr); 1654 if (pud_none(*pud)) 1655 return false; 1656 1657 if (pud_large(*pud)) 1658 return pfn_valid(pud_pfn(*pud)); 1659 1660 pmd = pmd_offset(pud, addr); 1661 if (pmd_none(*pmd)) 1662 return false; 1663 1664 if (pmd_large(*pmd)) 1665 return pfn_valid(pmd_pfn(*pmd)); 1666 1667 pte = pte_offset_kernel(pmd, addr); 1668 if (pte_none(*pte)) 1669 return false; 1670 1671 return pfn_valid(pte_pfn(*pte)); 1672 } 1673 EXPORT_SYMBOL(kern_addr_valid); 1674 1675 static unsigned long __ref kernel_map_hugepud(unsigned long vstart, 1676 unsigned long vend, 1677 pud_t *pud) 1678 { 1679 const unsigned long mask16gb = (1UL << 34) - 1UL; 1680 u64 pte_val = vstart; 1681 1682 /* Each PUD is 8GB */ 1683 if ((vstart & mask16gb) || 1684 (vend - vstart <= mask16gb)) { 1685 pte_val ^= kern_linear_pte_xor[2]; 1686 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; 1687 1688 return vstart + PUD_SIZE; 1689 } 1690 1691 pte_val ^= kern_linear_pte_xor[3]; 1692 pte_val |= _PAGE_PUD_HUGE; 1693 1694 vend = vstart + mask16gb + 1UL; 1695 while (vstart < vend) { 1696 pud_val(*pud) = pte_val; 1697 1698 pte_val += PUD_SIZE; 1699 vstart += PUD_SIZE; 1700 pud++; 1701 } 1702 return vstart; 1703 } 1704 1705 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, 1706 bool guard) 1707 { 1708 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) 1709 return true; 1710 1711 return false; 1712 } 1713 1714 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, 1715 unsigned long vend, 1716 pmd_t *pmd) 1717 { 1718 const unsigned long mask256mb = (1UL << 28) - 1UL; 1719 const unsigned long mask2gb = (1UL << 31) - 1UL; 1720 u64 pte_val = vstart; 1721 1722 /* Each PMD is 8MB */ 1723 if ((vstart & mask256mb) || 1724 (vend - vstart <= mask256mb)) { 1725 pte_val ^= kern_linear_pte_xor[0]; 1726 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; 1727 1728 return vstart + PMD_SIZE; 1729 } 1730 1731 if ((vstart & mask2gb) || 1732 (vend - vstart <= mask2gb)) { 1733 pte_val ^= kern_linear_pte_xor[1]; 1734 pte_val |= _PAGE_PMD_HUGE; 1735 vend = vstart + mask256mb + 1UL; 1736 } else { 1737 pte_val ^= kern_linear_pte_xor[2]; 1738 pte_val |= _PAGE_PMD_HUGE; 1739 vend = vstart + mask2gb + 1UL; 1740 } 1741 1742 while (vstart < vend) { 1743 pmd_val(*pmd) = pte_val; 1744 1745 pte_val += PMD_SIZE; 1746 vstart += PMD_SIZE; 1747 pmd++; 1748 } 1749 1750 return vstart; 1751 } 1752 1753 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, 1754 bool guard) 1755 { 1756 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) 1757 return true; 1758 1759 return false; 1760 } 1761 1762 static unsigned long __ref kernel_map_range(unsigned long pstart, 1763 unsigned long pend, pgprot_t prot, 1764 bool use_huge) 1765 { 1766 unsigned long vstart = PAGE_OFFSET + pstart; 1767 unsigned long vend = PAGE_OFFSET + pend; 1768 unsigned long alloc_bytes = 0UL; 1769 1770 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { 1771 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", 1772 vstart, vend); 1773 prom_halt(); 1774 } 1775 1776 while (vstart < vend) { 1777 unsigned long this_end, paddr = __pa(vstart); 1778 pgd_t *pgd = pgd_offset_k(vstart); 1779 p4d_t *p4d; 1780 pud_t *pud; 1781 pmd_t *pmd; 1782 pte_t *pte; 1783 1784 if (pgd_none(*pgd)) { 1785 pud_t *new; 1786 1787 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1788 PAGE_SIZE); 1789 if (!new) 1790 goto err_alloc; 1791 alloc_bytes += PAGE_SIZE; 1792 pgd_populate(&init_mm, pgd, new); 1793 } 1794 1795 p4d = p4d_offset(pgd, vstart); 1796 if (p4d_none(*p4d)) { 1797 pud_t *new; 1798 1799 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1800 PAGE_SIZE); 1801 if (!new) 1802 goto err_alloc; 1803 alloc_bytes += PAGE_SIZE; 1804 p4d_populate(&init_mm, p4d, new); 1805 } 1806 1807 pud = pud_offset(p4d, vstart); 1808 if (pud_none(*pud)) { 1809 pmd_t *new; 1810 1811 if (kernel_can_map_hugepud(vstart, vend, use_huge)) { 1812 vstart = kernel_map_hugepud(vstart, vend, pud); 1813 continue; 1814 } 1815 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1816 PAGE_SIZE); 1817 if (!new) 1818 goto err_alloc; 1819 alloc_bytes += PAGE_SIZE; 1820 pud_populate(&init_mm, pud, new); 1821 } 1822 1823 pmd = pmd_offset(pud, vstart); 1824 if (pmd_none(*pmd)) { 1825 pte_t *new; 1826 1827 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { 1828 vstart = kernel_map_hugepmd(vstart, vend, pmd); 1829 continue; 1830 } 1831 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE, 1832 PAGE_SIZE); 1833 if (!new) 1834 goto err_alloc; 1835 alloc_bytes += PAGE_SIZE; 1836 pmd_populate_kernel(&init_mm, pmd, new); 1837 } 1838 1839 pte = pte_offset_kernel(pmd, vstart); 1840 this_end = (vstart + PMD_SIZE) & PMD_MASK; 1841 if (this_end > vend) 1842 this_end = vend; 1843 1844 while (vstart < this_end) { 1845 pte_val(*pte) = (paddr | pgprot_val(prot)); 1846 1847 vstart += PAGE_SIZE; 1848 paddr += PAGE_SIZE; 1849 pte++; 1850 } 1851 } 1852 1853 return alloc_bytes; 1854 1855 err_alloc: 1856 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n", 1857 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); 1858 return -ENOMEM; 1859 } 1860 1861 static void __init flush_all_kernel_tsbs(void) 1862 { 1863 int i; 1864 1865 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { 1866 struct tsb *ent = &swapper_tsb[i]; 1867 1868 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1869 } 1870 #ifndef CONFIG_DEBUG_PAGEALLOC 1871 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { 1872 struct tsb *ent = &swapper_4m_tsb[i]; 1873 1874 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 1875 } 1876 #endif 1877 } 1878 1879 extern unsigned int kvmap_linear_patch[1]; 1880 1881 static void __init kernel_physical_mapping_init(void) 1882 { 1883 unsigned long i, mem_alloced = 0UL; 1884 bool use_huge = true; 1885 1886 #ifdef CONFIG_DEBUG_PAGEALLOC 1887 use_huge = false; 1888 #endif 1889 for (i = 0; i < pall_ents; i++) { 1890 unsigned long phys_start, phys_end; 1891 1892 phys_start = pall[i].phys_addr; 1893 phys_end = phys_start + pall[i].reg_size; 1894 1895 mem_alloced += kernel_map_range(phys_start, phys_end, 1896 PAGE_KERNEL, use_huge); 1897 } 1898 1899 printk("Allocated %ld bytes for kernel page tables.\n", 1900 mem_alloced); 1901 1902 kvmap_linear_patch[0] = 0x01000000; /* nop */ 1903 flushi(&kvmap_linear_patch[0]); 1904 1905 flush_all_kernel_tsbs(); 1906 1907 __flush_tlb_all(); 1908 } 1909 1910 #ifdef CONFIG_DEBUG_PAGEALLOC 1911 void __kernel_map_pages(struct page *page, int numpages, int enable) 1912 { 1913 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; 1914 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); 1915 1916 kernel_map_range(phys_start, phys_end, 1917 (enable ? PAGE_KERNEL : __pgprot(0)), false); 1918 1919 flush_tsb_kernel_range(PAGE_OFFSET + phys_start, 1920 PAGE_OFFSET + phys_end); 1921 1922 /* we should perform an IPI and flush all tlbs, 1923 * but that can deadlock->flush only current cpu. 1924 */ 1925 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, 1926 PAGE_OFFSET + phys_end); 1927 } 1928 #endif 1929 1930 unsigned long __init find_ecache_flush_span(unsigned long size) 1931 { 1932 int i; 1933 1934 for (i = 0; i < pavail_ents; i++) { 1935 if (pavail[i].reg_size >= size) 1936 return pavail[i].phys_addr; 1937 } 1938 1939 return ~0UL; 1940 } 1941 1942 unsigned long PAGE_OFFSET; 1943 EXPORT_SYMBOL(PAGE_OFFSET); 1944 1945 unsigned long VMALLOC_END = 0x0000010000000000UL; 1946 EXPORT_SYMBOL(VMALLOC_END); 1947 1948 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; 1949 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; 1950 1951 static void __init setup_page_offset(void) 1952 { 1953 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 1954 /* Cheetah/Panther support a full 64-bit virtual 1955 * address, so we can use all that our page tables 1956 * support. 1957 */ 1958 sparc64_va_hole_top = 0xfff0000000000000UL; 1959 sparc64_va_hole_bottom = 0x0010000000000000UL; 1960 1961 max_phys_bits = 42; 1962 } else if (tlb_type == hypervisor) { 1963 switch (sun4v_chip_type) { 1964 case SUN4V_CHIP_NIAGARA1: 1965 case SUN4V_CHIP_NIAGARA2: 1966 /* T1 and T2 support 48-bit virtual addresses. */ 1967 sparc64_va_hole_top = 0xffff800000000000UL; 1968 sparc64_va_hole_bottom = 0x0000800000000000UL; 1969 1970 max_phys_bits = 39; 1971 break; 1972 case SUN4V_CHIP_NIAGARA3: 1973 /* T3 supports 48-bit virtual addresses. */ 1974 sparc64_va_hole_top = 0xffff800000000000UL; 1975 sparc64_va_hole_bottom = 0x0000800000000000UL; 1976 1977 max_phys_bits = 43; 1978 break; 1979 case SUN4V_CHIP_NIAGARA4: 1980 case SUN4V_CHIP_NIAGARA5: 1981 case SUN4V_CHIP_SPARC64X: 1982 case SUN4V_CHIP_SPARC_M6: 1983 /* T4 and later support 52-bit virtual addresses. */ 1984 sparc64_va_hole_top = 0xfff8000000000000UL; 1985 sparc64_va_hole_bottom = 0x0008000000000000UL; 1986 max_phys_bits = 47; 1987 break; 1988 case SUN4V_CHIP_SPARC_M7: 1989 case SUN4V_CHIP_SPARC_SN: 1990 /* M7 and later support 52-bit virtual addresses. */ 1991 sparc64_va_hole_top = 0xfff8000000000000UL; 1992 sparc64_va_hole_bottom = 0x0008000000000000UL; 1993 max_phys_bits = 49; 1994 break; 1995 case SUN4V_CHIP_SPARC_M8: 1996 default: 1997 /* M8 and later support 54-bit virtual addresses. 1998 * However, restricting M8 and above VA bits to 53 1999 * as 4-level page table cannot support more than 2000 * 53 VA bits. 2001 */ 2002 sparc64_va_hole_top = 0xfff0000000000000UL; 2003 sparc64_va_hole_bottom = 0x0010000000000000UL; 2004 max_phys_bits = 51; 2005 break; 2006 } 2007 } 2008 2009 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { 2010 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", 2011 max_phys_bits); 2012 prom_halt(); 2013 } 2014 2015 PAGE_OFFSET = sparc64_va_hole_top; 2016 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + 2017 (sparc64_va_hole_bottom >> 2)); 2018 2019 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", 2020 PAGE_OFFSET, max_phys_bits); 2021 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", 2022 VMALLOC_START, VMALLOC_END); 2023 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", 2024 VMEMMAP_BASE, VMEMMAP_BASE << 1); 2025 } 2026 2027 static void __init tsb_phys_patch(void) 2028 { 2029 struct tsb_ldquad_phys_patch_entry *pquad; 2030 struct tsb_phys_patch_entry *p; 2031 2032 pquad = &__tsb_ldquad_phys_patch; 2033 while (pquad < &__tsb_ldquad_phys_patch_end) { 2034 unsigned long addr = pquad->addr; 2035 2036 if (tlb_type == hypervisor) 2037 *(unsigned int *) addr = pquad->sun4v_insn; 2038 else 2039 *(unsigned int *) addr = pquad->sun4u_insn; 2040 wmb(); 2041 __asm__ __volatile__("flush %0" 2042 : /* no outputs */ 2043 : "r" (addr)); 2044 2045 pquad++; 2046 } 2047 2048 p = &__tsb_phys_patch; 2049 while (p < &__tsb_phys_patch_end) { 2050 unsigned long addr = p->addr; 2051 2052 *(unsigned int *) addr = p->insn; 2053 wmb(); 2054 __asm__ __volatile__("flush %0" 2055 : /* no outputs */ 2056 : "r" (addr)); 2057 2058 p++; 2059 } 2060 } 2061 2062 /* Don't mark as init, we give this to the Hypervisor. */ 2063 #ifndef CONFIG_DEBUG_PAGEALLOC 2064 #define NUM_KTSB_DESCR 2 2065 #else 2066 #define NUM_KTSB_DESCR 1 2067 #endif 2068 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; 2069 2070 /* The swapper TSBs are loaded with a base sequence of: 2071 * 2072 * sethi %uhi(SYMBOL), REG1 2073 * sethi %hi(SYMBOL), REG2 2074 * or REG1, %ulo(SYMBOL), REG1 2075 * or REG2, %lo(SYMBOL), REG2 2076 * sllx REG1, 32, REG1 2077 * or REG1, REG2, REG1 2078 * 2079 * When we use physical addressing for the TSB accesses, we patch the 2080 * first four instructions in the above sequence. 2081 */ 2082 2083 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) 2084 { 2085 unsigned long high_bits, low_bits; 2086 2087 high_bits = (pa >> 32) & 0xffffffff; 2088 low_bits = (pa >> 0) & 0xffffffff; 2089 2090 while (start < end) { 2091 unsigned int *ia = (unsigned int *)(unsigned long)*start; 2092 2093 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); 2094 __asm__ __volatile__("flush %0" : : "r" (ia)); 2095 2096 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); 2097 __asm__ __volatile__("flush %0" : : "r" (ia + 1)); 2098 2099 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); 2100 __asm__ __volatile__("flush %0" : : "r" (ia + 2)); 2101 2102 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); 2103 __asm__ __volatile__("flush %0" : : "r" (ia + 3)); 2104 2105 start++; 2106 } 2107 } 2108 2109 static void ktsb_phys_patch(void) 2110 { 2111 extern unsigned int __swapper_tsb_phys_patch; 2112 extern unsigned int __swapper_tsb_phys_patch_end; 2113 unsigned long ktsb_pa; 2114 2115 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2116 patch_one_ktsb_phys(&__swapper_tsb_phys_patch, 2117 &__swapper_tsb_phys_patch_end, ktsb_pa); 2118 #ifndef CONFIG_DEBUG_PAGEALLOC 2119 { 2120 extern unsigned int __swapper_4m_tsb_phys_patch; 2121 extern unsigned int __swapper_4m_tsb_phys_patch_end; 2122 ktsb_pa = (kern_base + 2123 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2124 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, 2125 &__swapper_4m_tsb_phys_patch_end, ktsb_pa); 2126 } 2127 #endif 2128 } 2129 2130 static void __init sun4v_ktsb_init(void) 2131 { 2132 unsigned long ktsb_pa; 2133 2134 /* First KTSB for PAGE_SIZE mappings. */ 2135 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); 2136 2137 switch (PAGE_SIZE) { 2138 case 8 * 1024: 2139 default: 2140 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; 2141 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; 2142 break; 2143 2144 case 64 * 1024: 2145 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; 2146 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; 2147 break; 2148 2149 case 512 * 1024: 2150 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; 2151 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; 2152 break; 2153 2154 case 4 * 1024 * 1024: 2155 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; 2156 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; 2157 break; 2158 } 2159 2160 ktsb_descr[0].assoc = 1; 2161 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; 2162 ktsb_descr[0].ctx_idx = 0; 2163 ktsb_descr[0].tsb_base = ktsb_pa; 2164 ktsb_descr[0].resv = 0; 2165 2166 #ifndef CONFIG_DEBUG_PAGEALLOC 2167 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ 2168 ktsb_pa = (kern_base + 2169 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); 2170 2171 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; 2172 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | 2173 HV_PGSZ_MASK_256MB | 2174 HV_PGSZ_MASK_2GB | 2175 HV_PGSZ_MASK_16GB) & 2176 cpu_pgsz_mask); 2177 ktsb_descr[1].assoc = 1; 2178 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; 2179 ktsb_descr[1].ctx_idx = 0; 2180 ktsb_descr[1].tsb_base = ktsb_pa; 2181 ktsb_descr[1].resv = 0; 2182 #endif 2183 } 2184 2185 void sun4v_ktsb_register(void) 2186 { 2187 unsigned long pa, ret; 2188 2189 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); 2190 2191 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); 2192 if (ret != 0) { 2193 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " 2194 "errors with %lx\n", pa, ret); 2195 prom_halt(); 2196 } 2197 } 2198 2199 static void __init sun4u_linear_pte_xor_finalize(void) 2200 { 2201 #ifndef CONFIG_DEBUG_PAGEALLOC 2202 /* This is where we would add Panther support for 2203 * 32MB and 256MB pages. 2204 */ 2205 #endif 2206 } 2207 2208 static void __init sun4v_linear_pte_xor_finalize(void) 2209 { 2210 unsigned long pagecv_flag; 2211 2212 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead 2213 * enables MCD error. Do not set bit 9 on M7 processor. 2214 */ 2215 switch (sun4v_chip_type) { 2216 case SUN4V_CHIP_SPARC_M7: 2217 case SUN4V_CHIP_SPARC_M8: 2218 case SUN4V_CHIP_SPARC_SN: 2219 pagecv_flag = 0x00; 2220 break; 2221 default: 2222 pagecv_flag = _PAGE_CV_4V; 2223 break; 2224 } 2225 #ifndef CONFIG_DEBUG_PAGEALLOC 2226 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { 2227 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ 2228 PAGE_OFFSET; 2229 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | 2230 _PAGE_P_4V | _PAGE_W_4V); 2231 } else { 2232 kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; 2233 } 2234 2235 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { 2236 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ 2237 PAGE_OFFSET; 2238 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | 2239 _PAGE_P_4V | _PAGE_W_4V); 2240 } else { 2241 kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; 2242 } 2243 2244 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { 2245 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ 2246 PAGE_OFFSET; 2247 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | 2248 _PAGE_P_4V | _PAGE_W_4V); 2249 } else { 2250 kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; 2251 } 2252 #endif 2253 } 2254 2255 /* paging_init() sets up the page tables */ 2256 2257 static unsigned long last_valid_pfn; 2258 2259 static void sun4u_pgprot_init(void); 2260 static void sun4v_pgprot_init(void); 2261 2262 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) 2263 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) 2264 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) 2265 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) 2266 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) 2267 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) 2268 2269 /* We need to exclude reserved regions. This exclusion will include 2270 * vmlinux and initrd. To be more precise the initrd size could be used to 2271 * compute a new lower limit because it is freed later during initialization. 2272 */ 2273 static void __init reduce_memory(phys_addr_t limit_ram) 2274 { 2275 limit_ram += memblock_reserved_size(); 2276 memblock_enforce_memory_limit(limit_ram); 2277 } 2278 2279 void __init paging_init(void) 2280 { 2281 unsigned long end_pfn, shift, phys_base; 2282 unsigned long real_end, i; 2283 2284 setup_page_offset(); 2285 2286 /* These build time checkes make sure that the dcache_dirty_cpu() 2287 * page->flags usage will work. 2288 * 2289 * When a page gets marked as dcache-dirty, we store the 2290 * cpu number starting at bit 32 in the page->flags. Also, 2291 * functions like clear_dcache_dirty_cpu use the cpu mask 2292 * in 13-bit signed-immediate instruction fields. 2293 */ 2294 2295 /* 2296 * Page flags must not reach into upper 32 bits that are used 2297 * for the cpu number 2298 */ 2299 BUILD_BUG_ON(NR_PAGEFLAGS > 32); 2300 2301 /* 2302 * The bit fields placed in the high range must not reach below 2303 * the 32 bit boundary. Otherwise we cannot place the cpu field 2304 * at the 32 bit boundary. 2305 */ 2306 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + 2307 ilog2(roundup_pow_of_two(NR_CPUS)) > 32); 2308 2309 BUILD_BUG_ON(NR_CPUS > 4096); 2310 2311 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; 2312 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; 2313 2314 /* Invalidate both kernel TSBs. */ 2315 memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); 2316 #ifndef CONFIG_DEBUG_PAGEALLOC 2317 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2318 #endif 2319 2320 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde 2321 * bit on M7 processor. This is a conflicting usage of the same 2322 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption 2323 * Detection error on all pages and this will lead to problems 2324 * later. Kernel does not run with MCD enabled and hence rest 2325 * of the required steps to fully configure memory corruption 2326 * detection are not taken. We need to ensure TTE.mcde is not 2327 * set on M7 processor. Compute the value of cacheability 2328 * flag for use later taking this into consideration. 2329 */ 2330 switch (sun4v_chip_type) { 2331 case SUN4V_CHIP_SPARC_M7: 2332 case SUN4V_CHIP_SPARC_M8: 2333 case SUN4V_CHIP_SPARC_SN: 2334 page_cache4v_flag = _PAGE_CP_4V; 2335 break; 2336 default: 2337 page_cache4v_flag = _PAGE_CACHE_4V; 2338 break; 2339 } 2340 2341 if (tlb_type == hypervisor) 2342 sun4v_pgprot_init(); 2343 else 2344 sun4u_pgprot_init(); 2345 2346 if (tlb_type == cheetah_plus || 2347 tlb_type == hypervisor) { 2348 tsb_phys_patch(); 2349 ktsb_phys_patch(); 2350 } 2351 2352 if (tlb_type == hypervisor) 2353 sun4v_patch_tlb_handlers(); 2354 2355 /* Find available physical memory... 2356 * 2357 * Read it twice in order to work around a bug in openfirmware. 2358 * The call to grab this table itself can cause openfirmware to 2359 * allocate memory, which in turn can take away some space from 2360 * the list of available memory. Reading it twice makes sure 2361 * we really do get the final value. 2362 */ 2363 read_obp_translations(); 2364 read_obp_memory("reg", &pall[0], &pall_ents); 2365 read_obp_memory("available", &pavail[0], &pavail_ents); 2366 read_obp_memory("available", &pavail[0], &pavail_ents); 2367 2368 phys_base = 0xffffffffffffffffUL; 2369 for (i = 0; i < pavail_ents; i++) { 2370 phys_base = min(phys_base, pavail[i].phys_addr); 2371 memblock_add(pavail[i].phys_addr, pavail[i].reg_size); 2372 } 2373 2374 memblock_reserve(kern_base, kern_size); 2375 2376 find_ramdisk(phys_base); 2377 2378 if (cmdline_memory_size) 2379 reduce_memory(cmdline_memory_size); 2380 2381 memblock_allow_resize(); 2382 memblock_dump_all(); 2383 2384 set_bit(0, mmu_context_bmap); 2385 2386 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); 2387 2388 real_end = (unsigned long)_end; 2389 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); 2390 printk("Kernel: Using %d locked TLB entries for main kernel image.\n", 2391 num_kernel_image_mappings); 2392 2393 /* Set kernel pgd to upper alias so physical page computations 2394 * work. 2395 */ 2396 init_mm.pgd += ((shift) / (sizeof(pgd_t))); 2397 2398 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); 2399 2400 inherit_prom_mappings(); 2401 2402 /* Ok, we can use our TLB miss and window trap handlers safely. */ 2403 setup_tba(); 2404 2405 __flush_tlb_all(); 2406 2407 prom_build_devicetree(); 2408 of_populate_present_mask(); 2409 #ifndef CONFIG_SMP 2410 of_fill_in_cpu_data(); 2411 #endif 2412 2413 if (tlb_type == hypervisor) { 2414 sun4v_mdesc_init(); 2415 mdesc_populate_present_mask(cpu_all_mask); 2416 #ifndef CONFIG_SMP 2417 mdesc_fill_in_cpu_data(cpu_all_mask); 2418 #endif 2419 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); 2420 2421 sun4v_linear_pte_xor_finalize(); 2422 2423 sun4v_ktsb_init(); 2424 sun4v_ktsb_register(); 2425 } else { 2426 unsigned long impl, ver; 2427 2428 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | 2429 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); 2430 2431 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 2432 impl = ((ver >> 32) & 0xffff); 2433 if (impl == PANTHER_IMPL) 2434 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | 2435 HV_PGSZ_MASK_256MB); 2436 2437 sun4u_linear_pte_xor_finalize(); 2438 } 2439 2440 /* Flush the TLBs and the 4M TSB so that the updated linear 2441 * pte XOR settings are realized for all mappings. 2442 */ 2443 __flush_tlb_all(); 2444 #ifndef CONFIG_DEBUG_PAGEALLOC 2445 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); 2446 #endif 2447 __flush_tlb_all(); 2448 2449 /* Setup bootmem... */ 2450 last_valid_pfn = end_pfn = bootmem_init(phys_base); 2451 2452 kernel_physical_mapping_init(); 2453 2454 { 2455 unsigned long max_zone_pfns[MAX_NR_ZONES]; 2456 2457 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 2458 2459 max_zone_pfns[ZONE_NORMAL] = end_pfn; 2460 2461 free_area_init(max_zone_pfns); 2462 } 2463 2464 printk("Booting Linux...\n"); 2465 } 2466 2467 int page_in_phys_avail(unsigned long paddr) 2468 { 2469 int i; 2470 2471 paddr &= PAGE_MASK; 2472 2473 for (i = 0; i < pavail_ents; i++) { 2474 unsigned long start, end; 2475 2476 start = pavail[i].phys_addr; 2477 end = start + pavail[i].reg_size; 2478 2479 if (paddr >= start && paddr < end) 2480 return 1; 2481 } 2482 if (paddr >= kern_base && paddr < (kern_base + kern_size)) 2483 return 1; 2484 #ifdef CONFIG_BLK_DEV_INITRD 2485 if (paddr >= __pa(initrd_start) && 2486 paddr < __pa(PAGE_ALIGN(initrd_end))) 2487 return 1; 2488 #endif 2489 2490 return 0; 2491 } 2492 2493 static void __init register_page_bootmem_info(void) 2494 { 2495 #ifdef CONFIG_NEED_MULTIPLE_NODES 2496 int i; 2497 2498 for_each_online_node(i) 2499 if (NODE_DATA(i)->node_spanned_pages) 2500 register_page_bootmem_info_node(NODE_DATA(i)); 2501 #endif 2502 } 2503 void __init mem_init(void) 2504 { 2505 high_memory = __va(last_valid_pfn << PAGE_SHIFT); 2506 2507 memblock_free_all(); 2508 2509 /* 2510 * Must be done after boot memory is put on freelist, because here we 2511 * might set fields in deferred struct pages that have not yet been 2512 * initialized, and memblock_free_all() initializes all the reserved 2513 * deferred pages for us. 2514 */ 2515 register_page_bootmem_info(); 2516 2517 /* 2518 * Set up the zero page, mark it reserved, so that page count 2519 * is not manipulated when freeing the page from user ptes. 2520 */ 2521 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); 2522 if (mem_map_zero == NULL) { 2523 prom_printf("paging_init: Cannot alloc zero page.\n"); 2524 prom_halt(); 2525 } 2526 mark_page_reserved(mem_map_zero); 2527 2528 mem_init_print_info(NULL); 2529 2530 if (tlb_type == cheetah || tlb_type == cheetah_plus) 2531 cheetah_ecache_flush_init(); 2532 } 2533 2534 void free_initmem(void) 2535 { 2536 unsigned long addr, initend; 2537 int do_free = 1; 2538 2539 /* If the physical memory maps were trimmed by kernel command 2540 * line options, don't even try freeing this initmem stuff up. 2541 * The kernel image could have been in the trimmed out region 2542 * and if so the freeing below will free invalid page structs. 2543 */ 2544 if (cmdline_memory_size) 2545 do_free = 0; 2546 2547 /* 2548 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. 2549 */ 2550 addr = PAGE_ALIGN((unsigned long)(__init_begin)); 2551 initend = (unsigned long)(__init_end) & PAGE_MASK; 2552 for (; addr < initend; addr += PAGE_SIZE) { 2553 unsigned long page; 2554 2555 page = (addr + 2556 ((unsigned long) __va(kern_base)) - 2557 ((unsigned long) KERNBASE)); 2558 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 2559 2560 if (do_free) 2561 free_reserved_page(virt_to_page(page)); 2562 } 2563 } 2564 2565 pgprot_t PAGE_KERNEL __read_mostly; 2566 EXPORT_SYMBOL(PAGE_KERNEL); 2567 2568 pgprot_t PAGE_KERNEL_LOCKED __read_mostly; 2569 pgprot_t PAGE_COPY __read_mostly; 2570 2571 pgprot_t PAGE_SHARED __read_mostly; 2572 EXPORT_SYMBOL(PAGE_SHARED); 2573 2574 unsigned long pg_iobits __read_mostly; 2575 2576 unsigned long _PAGE_IE __read_mostly; 2577 EXPORT_SYMBOL(_PAGE_IE); 2578 2579 unsigned long _PAGE_E __read_mostly; 2580 EXPORT_SYMBOL(_PAGE_E); 2581 2582 unsigned long _PAGE_CACHE __read_mostly; 2583 EXPORT_SYMBOL(_PAGE_CACHE); 2584 2585 #ifdef CONFIG_SPARSEMEM_VMEMMAP 2586 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, 2587 int node, struct vmem_altmap *altmap) 2588 { 2589 unsigned long pte_base; 2590 2591 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2592 _PAGE_CP_4U | _PAGE_CV_4U | 2593 _PAGE_P_4U | _PAGE_W_4U); 2594 if (tlb_type == hypervisor) 2595 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2596 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); 2597 2598 pte_base |= _PAGE_PMD_HUGE; 2599 2600 vstart = vstart & PMD_MASK; 2601 vend = ALIGN(vend, PMD_SIZE); 2602 for (; vstart < vend; vstart += PMD_SIZE) { 2603 pgd_t *pgd = vmemmap_pgd_populate(vstart, node); 2604 unsigned long pte; 2605 p4d_t *p4d; 2606 pud_t *pud; 2607 pmd_t *pmd; 2608 2609 if (!pgd) 2610 return -ENOMEM; 2611 2612 p4d = vmemmap_p4d_populate(pgd, vstart, node); 2613 if (!p4d) 2614 return -ENOMEM; 2615 2616 pud = vmemmap_pud_populate(p4d, vstart, node); 2617 if (!pud) 2618 return -ENOMEM; 2619 2620 pmd = pmd_offset(pud, vstart); 2621 pte = pmd_val(*pmd); 2622 if (!(pte & _PAGE_VALID)) { 2623 void *block = vmemmap_alloc_block(PMD_SIZE, node); 2624 2625 if (!block) 2626 return -ENOMEM; 2627 2628 pmd_val(*pmd) = pte_base | __pa(block); 2629 } 2630 } 2631 2632 return 0; 2633 } 2634 2635 void vmemmap_free(unsigned long start, unsigned long end, 2636 struct vmem_altmap *altmap) 2637 { 2638 } 2639 #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 2640 2641 static void prot_init_common(unsigned long page_none, 2642 unsigned long page_shared, 2643 unsigned long page_copy, 2644 unsigned long page_readonly, 2645 unsigned long page_exec_bit) 2646 { 2647 PAGE_COPY = __pgprot(page_copy); 2648 PAGE_SHARED = __pgprot(page_shared); 2649 2650 protection_map[0x0] = __pgprot(page_none); 2651 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); 2652 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); 2653 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); 2654 protection_map[0x4] = __pgprot(page_readonly); 2655 protection_map[0x5] = __pgprot(page_readonly); 2656 protection_map[0x6] = __pgprot(page_copy); 2657 protection_map[0x7] = __pgprot(page_copy); 2658 protection_map[0x8] = __pgprot(page_none); 2659 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); 2660 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); 2661 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); 2662 protection_map[0xc] = __pgprot(page_readonly); 2663 protection_map[0xd] = __pgprot(page_readonly); 2664 protection_map[0xe] = __pgprot(page_shared); 2665 protection_map[0xf] = __pgprot(page_shared); 2666 } 2667 2668 static void __init sun4u_pgprot_init(void) 2669 { 2670 unsigned long page_none, page_shared, page_copy, page_readonly; 2671 unsigned long page_exec_bit; 2672 int i; 2673 2674 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2675 _PAGE_CACHE_4U | _PAGE_P_4U | 2676 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2677 _PAGE_EXEC_4U); 2678 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | 2679 _PAGE_CACHE_4U | _PAGE_P_4U | 2680 __ACCESS_BITS_4U | __DIRTY_BITS_4U | 2681 _PAGE_EXEC_4U | _PAGE_L_4U); 2682 2683 _PAGE_IE = _PAGE_IE_4U; 2684 _PAGE_E = _PAGE_E_4U; 2685 _PAGE_CACHE = _PAGE_CACHE_4U; 2686 2687 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | 2688 __ACCESS_BITS_4U | _PAGE_E_4U); 2689 2690 #ifdef CONFIG_DEBUG_PAGEALLOC 2691 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2692 #else 2693 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ 2694 PAGE_OFFSET; 2695 #endif 2696 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | 2697 _PAGE_P_4U | _PAGE_W_4U); 2698 2699 for (i = 1; i < 4; i++) 2700 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2701 2702 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | 2703 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | 2704 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); 2705 2706 2707 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; 2708 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2709 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); 2710 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2711 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2712 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | 2713 __ACCESS_BITS_4U | _PAGE_EXEC_4U); 2714 2715 page_exec_bit = _PAGE_EXEC_4U; 2716 2717 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2718 page_exec_bit); 2719 } 2720 2721 static void __init sun4v_pgprot_init(void) 2722 { 2723 unsigned long page_none, page_shared, page_copy, page_readonly; 2724 unsigned long page_exec_bit; 2725 int i; 2726 2727 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | 2728 page_cache4v_flag | _PAGE_P_4V | 2729 __ACCESS_BITS_4V | __DIRTY_BITS_4V | 2730 _PAGE_EXEC_4V); 2731 PAGE_KERNEL_LOCKED = PAGE_KERNEL; 2732 2733 _PAGE_IE = _PAGE_IE_4V; 2734 _PAGE_E = _PAGE_E_4V; 2735 _PAGE_CACHE = page_cache4v_flag; 2736 2737 #ifdef CONFIG_DEBUG_PAGEALLOC 2738 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; 2739 #else 2740 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ 2741 PAGE_OFFSET; 2742 #endif 2743 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | 2744 _PAGE_W_4V); 2745 2746 for (i = 1; i < 4; i++) 2747 kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; 2748 2749 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | 2750 __ACCESS_BITS_4V | _PAGE_E_4V); 2751 2752 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | 2753 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | 2754 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | 2755 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); 2756 2757 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; 2758 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2759 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); 2760 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2761 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2762 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | 2763 __ACCESS_BITS_4V | _PAGE_EXEC_4V); 2764 2765 page_exec_bit = _PAGE_EXEC_4V; 2766 2767 prot_init_common(page_none, page_shared, page_copy, page_readonly, 2768 page_exec_bit); 2769 } 2770 2771 unsigned long pte_sz_bits(unsigned long sz) 2772 { 2773 if (tlb_type == hypervisor) { 2774 switch (sz) { 2775 case 8 * 1024: 2776 default: 2777 return _PAGE_SZ8K_4V; 2778 case 64 * 1024: 2779 return _PAGE_SZ64K_4V; 2780 case 512 * 1024: 2781 return _PAGE_SZ512K_4V; 2782 case 4 * 1024 * 1024: 2783 return _PAGE_SZ4MB_4V; 2784 } 2785 } else { 2786 switch (sz) { 2787 case 8 * 1024: 2788 default: 2789 return _PAGE_SZ8K_4U; 2790 case 64 * 1024: 2791 return _PAGE_SZ64K_4U; 2792 case 512 * 1024: 2793 return _PAGE_SZ512K_4U; 2794 case 4 * 1024 * 1024: 2795 return _PAGE_SZ4MB_4U; 2796 } 2797 } 2798 } 2799 2800 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) 2801 { 2802 pte_t pte; 2803 2804 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); 2805 pte_val(pte) |= (((unsigned long)space) << 32); 2806 pte_val(pte) |= pte_sz_bits(page_size); 2807 2808 return pte; 2809 } 2810 2811 static unsigned long kern_large_tte(unsigned long paddr) 2812 { 2813 unsigned long val; 2814 2815 val = (_PAGE_VALID | _PAGE_SZ4MB_4U | 2816 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | 2817 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); 2818 if (tlb_type == hypervisor) 2819 val = (_PAGE_VALID | _PAGE_SZ4MB_4V | 2820 page_cache4v_flag | _PAGE_P_4V | 2821 _PAGE_EXEC_4V | _PAGE_W_4V); 2822 2823 return val | paddr; 2824 } 2825 2826 /* If not locked, zap it. */ 2827 void __flush_tlb_all(void) 2828 { 2829 unsigned long pstate; 2830 int i; 2831 2832 __asm__ __volatile__("flushw\n\t" 2833 "rdpr %%pstate, %0\n\t" 2834 "wrpr %0, %1, %%pstate" 2835 : "=r" (pstate) 2836 : "i" (PSTATE_IE)); 2837 if (tlb_type == hypervisor) { 2838 sun4v_mmu_demap_all(); 2839 } else if (tlb_type == spitfire) { 2840 for (i = 0; i < 64; i++) { 2841 /* Spitfire Errata #32 workaround */ 2842 /* NOTE: Always runs on spitfire, so no 2843 * cheetah+ page size encodings. 2844 */ 2845 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2846 "flush %%g6" 2847 : /* No outputs */ 2848 : "r" (0), 2849 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2850 2851 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { 2852 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2853 "membar #Sync" 2854 : /* no outputs */ 2855 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); 2856 spitfire_put_dtlb_data(i, 0x0UL); 2857 } 2858 2859 /* Spitfire Errata #32 workaround */ 2860 /* NOTE: Always runs on spitfire, so no 2861 * cheetah+ page size encodings. 2862 */ 2863 __asm__ __volatile__("stxa %0, [%1] %2\n\t" 2864 "flush %%g6" 2865 : /* No outputs */ 2866 : "r" (0), 2867 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); 2868 2869 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { 2870 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 2871 "membar #Sync" 2872 : /* no outputs */ 2873 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); 2874 spitfire_put_itlb_data(i, 0x0UL); 2875 } 2876 } 2877 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { 2878 cheetah_flush_dtlb_all(); 2879 cheetah_flush_itlb_all(); 2880 } 2881 __asm__ __volatile__("wrpr %0, 0, %%pstate" 2882 : : "r" (pstate)); 2883 } 2884 2885 pte_t *pte_alloc_one_kernel(struct mm_struct *mm) 2886 { 2887 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO); 2888 pte_t *pte = NULL; 2889 2890 if (page) 2891 pte = (pte_t *) page_address(page); 2892 2893 return pte; 2894 } 2895 2896 pgtable_t pte_alloc_one(struct mm_struct *mm) 2897 { 2898 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO); 2899 if (!page) 2900 return NULL; 2901 if (!pgtable_pte_page_ctor(page)) { 2902 free_unref_page(page); 2903 return NULL; 2904 } 2905 return (pte_t *) page_address(page); 2906 } 2907 2908 void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 2909 { 2910 free_page((unsigned long)pte); 2911 } 2912 2913 static void __pte_free(pgtable_t pte) 2914 { 2915 struct page *page = virt_to_page(pte); 2916 2917 pgtable_pte_page_dtor(page); 2918 __free_page(page); 2919 } 2920 2921 void pte_free(struct mm_struct *mm, pgtable_t pte) 2922 { 2923 __pte_free(pte); 2924 } 2925 2926 void pgtable_free(void *table, bool is_page) 2927 { 2928 if (is_page) 2929 __pte_free(table); 2930 else 2931 kmem_cache_free(pgtable_cache, table); 2932 } 2933 2934 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 2935 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 2936 pmd_t *pmd) 2937 { 2938 unsigned long pte, flags; 2939 struct mm_struct *mm; 2940 pmd_t entry = *pmd; 2941 2942 if (!pmd_large(entry) || !pmd_young(entry)) 2943 return; 2944 2945 pte = pmd_val(entry); 2946 2947 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ 2948 if (!(pte & _PAGE_VALID)) 2949 return; 2950 2951 /* We are fabricating 8MB pages using 4MB real hw pages. */ 2952 pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); 2953 2954 mm = vma->vm_mm; 2955 2956 spin_lock_irqsave(&mm->context.lock, flags); 2957 2958 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) 2959 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, 2960 addr, pte); 2961 2962 spin_unlock_irqrestore(&mm->context.lock, flags); 2963 } 2964 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 2965 2966 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 2967 static void context_reload(void *__data) 2968 { 2969 struct mm_struct *mm = __data; 2970 2971 if (mm == current->mm) 2972 load_secondary_context(mm); 2973 } 2974 2975 void hugetlb_setup(struct pt_regs *regs) 2976 { 2977 struct mm_struct *mm = current->mm; 2978 struct tsb_config *tp; 2979 2980 if (faulthandler_disabled() || !mm) { 2981 const struct exception_table_entry *entry; 2982 2983 entry = search_exception_tables(regs->tpc); 2984 if (entry) { 2985 regs->tpc = entry->fixup; 2986 regs->tnpc = regs->tpc + 4; 2987 return; 2988 } 2989 pr_alert("Unexpected HugeTLB setup in atomic context.\n"); 2990 die_if_kernel("HugeTSB in atomic", regs); 2991 } 2992 2993 tp = &mm->context.tsb_block[MM_TSB_HUGE]; 2994 if (likely(tp->tsb == NULL)) 2995 tsb_grow(mm, MM_TSB_HUGE, 0); 2996 2997 tsb_context_switch(mm); 2998 smp_tsb_sync(mm); 2999 3000 /* On UltraSPARC-III+ and later, configure the second half of 3001 * the Data-TLB for huge pages. 3002 */ 3003 if (tlb_type == cheetah_plus) { 3004 bool need_context_reload = false; 3005 unsigned long ctx; 3006 3007 spin_lock_irq(&ctx_alloc_lock); 3008 ctx = mm->context.sparc64_ctx_val; 3009 ctx &= ~CTX_PGSZ_MASK; 3010 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; 3011 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; 3012 3013 if (ctx != mm->context.sparc64_ctx_val) { 3014 /* When changing the page size fields, we 3015 * must perform a context flush so that no 3016 * stale entries match. This flush must 3017 * occur with the original context register 3018 * settings. 3019 */ 3020 do_flush_tlb_mm(mm); 3021 3022 /* Reload the context register of all processors 3023 * also executing in this address space. 3024 */ 3025 mm->context.sparc64_ctx_val = ctx; 3026 need_context_reload = true; 3027 } 3028 spin_unlock_irq(&ctx_alloc_lock); 3029 3030 if (need_context_reload) 3031 on_each_cpu(context_reload, mm, 0); 3032 } 3033 } 3034 #endif 3035 3036 static struct resource code_resource = { 3037 .name = "Kernel code", 3038 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3039 }; 3040 3041 static struct resource data_resource = { 3042 .name = "Kernel data", 3043 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3044 }; 3045 3046 static struct resource bss_resource = { 3047 .name = "Kernel bss", 3048 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM 3049 }; 3050 3051 static inline resource_size_t compute_kern_paddr(void *addr) 3052 { 3053 return (resource_size_t) (addr - KERNBASE + kern_base); 3054 } 3055 3056 static void __init kernel_lds_init(void) 3057 { 3058 code_resource.start = compute_kern_paddr(_text); 3059 code_resource.end = compute_kern_paddr(_etext - 1); 3060 data_resource.start = compute_kern_paddr(_etext); 3061 data_resource.end = compute_kern_paddr(_edata - 1); 3062 bss_resource.start = compute_kern_paddr(__bss_start); 3063 bss_resource.end = compute_kern_paddr(_end - 1); 3064 } 3065 3066 static int __init report_memory(void) 3067 { 3068 int i; 3069 struct resource *res; 3070 3071 kernel_lds_init(); 3072 3073 for (i = 0; i < pavail_ents; i++) { 3074 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 3075 3076 if (!res) { 3077 pr_warn("Failed to allocate source.\n"); 3078 break; 3079 } 3080 3081 res->name = "System RAM"; 3082 res->start = pavail[i].phys_addr; 3083 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; 3084 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; 3085 3086 if (insert_resource(&iomem_resource, res) < 0) { 3087 pr_warn("Resource insertion failed.\n"); 3088 break; 3089 } 3090 3091 insert_resource(res, &code_resource); 3092 insert_resource(res, &data_resource); 3093 insert_resource(res, &bss_resource); 3094 } 3095 3096 return 0; 3097 } 3098 arch_initcall(report_memory); 3099 3100 #ifdef CONFIG_SMP 3101 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range 3102 #else 3103 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range 3104 #endif 3105 3106 void flush_tlb_kernel_range(unsigned long start, unsigned long end) 3107 { 3108 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { 3109 if (start < LOW_OBP_ADDRESS) { 3110 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); 3111 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); 3112 } 3113 if (end > HI_OBP_ADDRESS) { 3114 flush_tsb_kernel_range(HI_OBP_ADDRESS, end); 3115 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); 3116 } 3117 } else { 3118 flush_tsb_kernel_range(start, end); 3119 do_flush_tlb_kernel_range(start, end); 3120 } 3121 } 3122 3123 void copy_user_highpage(struct page *to, struct page *from, 3124 unsigned long vaddr, struct vm_area_struct *vma) 3125 { 3126 char *vfrom, *vto; 3127 3128 vfrom = kmap_atomic(from); 3129 vto = kmap_atomic(to); 3130 copy_user_page(vto, vfrom, vaddr, to); 3131 kunmap_atomic(vto); 3132 kunmap_atomic(vfrom); 3133 3134 /* If this page has ADI enabled, copy over any ADI tags 3135 * as well 3136 */ 3137 if (vma->vm_flags & VM_SPARC_ADI) { 3138 unsigned long pfrom, pto, i, adi_tag; 3139 3140 pfrom = page_to_phys(from); 3141 pto = page_to_phys(to); 3142 3143 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3144 asm volatile("ldxa [%1] %2, %0\n\t" 3145 : "=r" (adi_tag) 3146 : "r" (i), "i" (ASI_MCD_REAL)); 3147 asm volatile("stxa %0, [%1] %2\n\t" 3148 : 3149 : "r" (adi_tag), "r" (pto), 3150 "i" (ASI_MCD_REAL)); 3151 pto += adi_blksize(); 3152 } 3153 asm volatile("membar #Sync\n\t"); 3154 } 3155 } 3156 EXPORT_SYMBOL(copy_user_highpage); 3157 3158 void copy_highpage(struct page *to, struct page *from) 3159 { 3160 char *vfrom, *vto; 3161 3162 vfrom = kmap_atomic(from); 3163 vto = kmap_atomic(to); 3164 copy_page(vto, vfrom); 3165 kunmap_atomic(vto); 3166 kunmap_atomic(vfrom); 3167 3168 /* If this platform is ADI enabled, copy any ADI tags 3169 * as well 3170 */ 3171 if (adi_capable()) { 3172 unsigned long pfrom, pto, i, adi_tag; 3173 3174 pfrom = page_to_phys(from); 3175 pto = page_to_phys(to); 3176 3177 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) { 3178 asm volatile("ldxa [%1] %2, %0\n\t" 3179 : "=r" (adi_tag) 3180 : "r" (i), "i" (ASI_MCD_REAL)); 3181 asm volatile("stxa %0, [%1] %2\n\t" 3182 : 3183 : "r" (adi_tag), "r" (pto), 3184 "i" (ASI_MCD_REAL)); 3185 pto += adi_blksize(); 3186 } 3187 asm volatile("membar #Sync\n\t"); 3188 } 3189 } 3190 EXPORT_SYMBOL(copy_highpage); 3191