1#include <asm/thread_info.h> 2#include <asm/trap_block.h> 3#include <asm/spitfire.h> 4#include <asm/ptrace.h> 5#include <asm/head.h> 6 7 .text 8 .align 8 9 .globl user_rtt_fill_fixup_common 10user_rtt_fill_fixup_common: 11 rdpr %cwp, %g1 12 add %g1, 1, %g1 13 wrpr %g1, 0x0, %cwp 14 15 rdpr %wstate, %g2 16 sll %g2, 3, %g2 17 wrpr %g2, 0x0, %wstate 18 19 /* We know %canrestore and %otherwin are both zero. */ 20 21 sethi %hi(sparc64_kern_pri_context), %g2 22 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2 23 mov PRIMARY_CONTEXT, %g1 24 25661: stxa %g2, [%g1] ASI_DMMU 26 .section .sun4v_1insn_patch, "ax" 27 .word 661b 28 stxa %g2, [%g1] ASI_MMU 29 .previous 30 31 sethi %hi(KERNBASE), %g1 32 flush %g1 33 34 mov %g4, %l4 35 mov %g5, %l5 36 brnz,pn %g3, 1f 37 mov %g3, %l3 38 39 or %g4, FAULT_CODE_WINFIXUP, %g4 40 stb %g4, [%g6 + TI_FAULT_CODE] 41 stx %g5, [%g6 + TI_FAULT_ADDR] 421: 43 mov %g6, %l1 44 wrpr %g0, 0x0, %tl 45 46661: nop 47 .section .sun4v_1insn_patch, "ax" 48 .word 661b 49 SET_GL(0) 50 .previous 51 52 wrpr %g0, RTRAP_PSTATE, %pstate 53 54 mov %l1, %g6 55 ldx [%g6 + TI_TASK], %g4 56 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3) 57 58 brnz,pn %l3, 1f 59 nop 60 61 call do_sparc64_fault 62 add %sp, PTREGS_OFF, %o0 63 ba,pt %xcc, rtrap 64 nop 65 661: cmp %g3, 2 67 bne,pn %xcc, 2f 68 nop 69 70 sethi %hi(tlb_type), %g1 71 lduw [%g1 + %lo(tlb_type)], %g1 72 cmp %g1, 3 73 bne,pt %icc, 1f 74 add %sp, PTREGS_OFF, %o0 75 mov %l4, %o2 76 call sun4v_do_mna 77 mov %l5, %o1 78 ba,a,pt %xcc, rtrap 791: mov %l4, %o1 80 mov %l5, %o2 81 call mem_address_unaligned 82 nop 83 ba,a,pt %xcc, rtrap 84 852: sethi %hi(tlb_type), %g1 86 mov %l4, %o1 87 lduw [%g1 + %lo(tlb_type)], %g1 88 mov %l5, %o2 89 cmp %g1, 3 90 bne,pt %icc, 1f 91 add %sp, PTREGS_OFF, %o0 92 call sun4v_data_access_exception 93 nop 94 ba,a,pt %xcc, rtrap 95 961: call spitfire_data_access_exception 97 nop 98 ba,a,pt %xcc, rtrap 99