1/*
2 * trampoline.S: SMP cpu boot-up trampoline code.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/init.h>
9#include <asm/head.h>
10#include <asm/psr.h>
11#include <asm/page.h>
12#include <asm/asi.h>
13#include <asm/ptrace.h>
14#include <asm/vaddrs.h>
15#include <asm/contregs.h>
16#include <asm/thread_info.h>
17
18	.globl sun4m_cpu_startup
19	.globl sun4d_cpu_startup
20
21	__CPUINIT
22	.align 4
23
24/* When we start up a cpu for the first time it enters this routine.
25 * This initializes the chip from whatever state the prom left it
26 * in and sets PIL in %psr to 15, no irqs.
27 */
28
29sun4m_cpu_startup:
30cpu1_startup:
31	sethi	%hi(trapbase_cpu1), %g3
32	b	1f
33	 or	%g3, %lo(trapbase_cpu1), %g3
34
35cpu2_startup:
36	sethi	%hi(trapbase_cpu2), %g3
37	b	1f
38	 or	%g3, %lo(trapbase_cpu2), %g3
39
40cpu3_startup:
41	sethi	%hi(trapbase_cpu3), %g3
42	b	1f
43	 or	%g3, %lo(trapbase_cpu3), %g3
44
451:
46	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
47	set	(PSR_PIL | PSR_S | PSR_PS), %g1
48	wr	%g1, 0x0, %psr		! traps off though
49	WRITE_PAUSE
50
51	/* Our %wim is one behind CWP */
52	mov	2, %g1
53	wr	%g1, 0x0, %wim
54	WRITE_PAUSE
55
56	/* This identifies "this cpu". */
57	wr	%g3, 0x0, %tbr
58	WRITE_PAUSE
59
60	/* Give ourselves a stack and curptr. */
61	set	current_set, %g5
62	srl	%g3, 10, %g4
63	and	%g4, 0xc, %g4
64	ld	[%g5 + %g4], %g6
65
66	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
67	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
68	add	%g6, %sp, %sp
69
70	/* Turn on traps (PSR_ET). */
71	rd	%psr, %g1
72	wr	%g1, PSR_ET, %psr	! traps on
73	WRITE_PAUSE
74
75	/* Init our caches, etc. */
76	set	poke_srmmu, %g5
77	ld	[%g5], %g5
78	call	%g5
79	 nop
80
81	/* Start this processor. */
82	call	smp4m_callin
83	 nop
84
85	b,a	smp_do_cpu_idle
86
87	.text
88	.align	4
89
90smp_do_cpu_idle:
91	call	cpu_idle
92	 mov	0, %o0
93
94	call	cpu_panic
95	 nop
96
97/* CPUID in bootbus can be found at PA 0xff0140000 */
98#define SUN4D_BOOTBUS_CPUID	0xf0140000
99
100	__CPUINIT
101	.align	4
102
103sun4d_cpu_startup:
104	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
105	set	(PSR_PIL | PSR_S | PSR_PS), %g1
106	wr	%g1, 0x0, %psr		! traps off though
107	WRITE_PAUSE
108
109	/* Our %wim is one behind CWP */
110	mov	2, %g1
111	wr	%g1, 0x0, %wim
112	WRITE_PAUSE
113
114	/* Set tbr - we use just one trap table. */
115	set	trapbase, %g1
116	wr	%g1, 0x0, %tbr
117	WRITE_PAUSE
118
119	/* Get our CPU id out of bootbus */
120	set	SUN4D_BOOTBUS_CPUID, %g3
121	lduba	[%g3] ASI_M_CTL, %g3
122	and	%g3, 0xf8, %g3
123	srl	%g3, 3, %g1
124	sta	%g1, [%g0] ASI_M_VIKING_TMP1
125
126	/* Give ourselves a stack and curptr. */
127	set	current_set, %g5
128	srl	%g3, 1, %g4
129	ld	[%g5 + %g4], %g6
130
131	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
132	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
133	add	%g6, %sp, %sp
134
135	/* Turn on traps (PSR_ET). */
136	rd	%psr, %g1
137	wr	%g1, PSR_ET, %psr	! traps on
138	WRITE_PAUSE
139
140	/* Init our caches, etc. */
141	set	poke_srmmu, %g5
142	ld	[%g5], %g5
143	call	%g5
144	 nop
145
146	/* Start this processor. */
147	call	smp4d_callin
148	 nop
149
150	b,a	smp_do_cpu_idle
151
152	__CPUINIT
153	.align	4
154        .global leon_smp_cpu_startup, smp_penguin_ctable
155
156leon_smp_cpu_startup:
157
158        set smp_penguin_ctable,%g1
159        ld [%g1+4],%g1
160        srl %g1,4,%g1
161        set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
162	sta %g1, [%g5] ASI_LEON_MMUREGS
163
164	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
165	set	(PSR_PIL | PSR_S | PSR_PS), %g1
166	wr	%g1, 0x0, %psr		! traps off though
167	WRITE_PAUSE
168
169	/* Our %wim is one behind CWP */
170	mov	2, %g1
171	wr	%g1, 0x0, %wim
172	WRITE_PAUSE
173
174	/* Set tbr - we use just one trap table. */
175	set	trapbase, %g1
176	wr	%g1, 0x0, %tbr
177	WRITE_PAUSE
178
179	/* Get our CPU id */
180        rd     %asr17,%g3
181
182	/* Give ourselves a stack and curptr. */
183	set	current_set, %g5
184	srl	%g3, 28, %g4
185	sll	%g4, 2, %g4
186	ld	[%g5 + %g4], %g6
187
188	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
189	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
190	add	%g6, %sp, %sp
191
192	/* Turn on traps (PSR_ET). */
193	rd	%psr, %g1
194	wr	%g1, PSR_ET, %psr	! traps on
195	WRITE_PAUSE
196
197	/* Init our caches, etc. */
198	set	poke_srmmu, %g5
199	ld	[%g5], %g5
200	call	%g5
201	 nop
202
203	/* Start this processor. */
204	call	leon_callin
205	 nop
206
207	b,a	smp_do_cpu_idle
208