1 /* time.c: UltraSparc timer and TOD clock support. 2 * 3 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net) 4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 5 * 6 * Based largely on code which is: 7 * 8 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/export.h> 13 #include <linux/sched.h> 14 #include <linux/kernel.h> 15 #include <linux/param.h> 16 #include <linux/string.h> 17 #include <linux/mm.h> 18 #include <linux/interrupt.h> 19 #include <linux/time.h> 20 #include <linux/timex.h> 21 #include <linux/init.h> 22 #include <linux/ioport.h> 23 #include <linux/mc146818rtc.h> 24 #include <linux/delay.h> 25 #include <linux/profile.h> 26 #include <linux/bcd.h> 27 #include <linux/jiffies.h> 28 #include <linux/cpufreq.h> 29 #include <linux/percpu.h> 30 #include <linux/miscdevice.h> 31 #include <linux/rtc/m48t59.h> 32 #include <linux/kernel_stat.h> 33 #include <linux/clockchips.h> 34 #include <linux/clocksource.h> 35 #include <linux/of_device.h> 36 #include <linux/platform_device.h> 37 #include <linux/ftrace.h> 38 39 #include <asm/oplib.h> 40 #include <asm/timer.h> 41 #include <asm/irq.h> 42 #include <asm/io.h> 43 #include <asm/prom.h> 44 #include <asm/starfire.h> 45 #include <asm/smp.h> 46 #include <asm/sections.h> 47 #include <asm/cpudata.h> 48 #include <linux/uaccess.h> 49 #include <asm/irq_regs.h> 50 #include <asm/cacheflush.h> 51 52 #include "entry.h" 53 #include "kernel.h" 54 55 DEFINE_SPINLOCK(rtc_lock); 56 57 #ifdef CONFIG_SMP 58 unsigned long profile_pc(struct pt_regs *regs) 59 { 60 unsigned long pc = instruction_pointer(regs); 61 62 if (in_lock_functions(pc)) 63 return regs->u_regs[UREG_RETPC]; 64 return pc; 65 } 66 EXPORT_SYMBOL(profile_pc); 67 #endif 68 69 static void tick_disable_protection(void) 70 { 71 /* Set things up so user can access tick register for profiling 72 * purposes. Also workaround BB_ERRATA_1 by doing a dummy 73 * read back of %tick after writing it. 74 */ 75 __asm__ __volatile__( 76 " ba,pt %%xcc, 1f\n" 77 " nop\n" 78 " .align 64\n" 79 "1: rd %%tick, %%g2\n" 80 " add %%g2, 6, %%g2\n" 81 " andn %%g2, %0, %%g2\n" 82 " wrpr %%g2, 0, %%tick\n" 83 " rdpr %%tick, %%g0" 84 : /* no outputs */ 85 : "r" (TICK_PRIV_BIT) 86 : "g2"); 87 } 88 89 static void tick_disable_irq(void) 90 { 91 __asm__ __volatile__( 92 " ba,pt %%xcc, 1f\n" 93 " nop\n" 94 " .align 64\n" 95 "1: wr %0, 0x0, %%tick_cmpr\n" 96 " rd %%tick_cmpr, %%g0" 97 : /* no outputs */ 98 : "r" (TICKCMP_IRQ_BIT)); 99 } 100 101 static void tick_init_tick(void) 102 { 103 tick_disable_protection(); 104 tick_disable_irq(); 105 } 106 107 static unsigned long long tick_get_tick(void) 108 { 109 unsigned long ret; 110 111 __asm__ __volatile__("rd %%tick, %0\n\t" 112 "mov %0, %0" 113 : "=r" (ret)); 114 115 return ret & ~TICK_PRIV_BIT; 116 } 117 118 static int tick_add_compare(unsigned long adj) 119 { 120 unsigned long orig_tick, new_tick, new_compare; 121 122 __asm__ __volatile__("rd %%tick, %0" 123 : "=r" (orig_tick)); 124 125 orig_tick &= ~TICKCMP_IRQ_BIT; 126 127 /* Workaround for Spitfire Errata (#54 I think??), I discovered 128 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch 129 * number 103640. 130 * 131 * On Blackbird writes to %tick_cmpr can fail, the 132 * workaround seems to be to execute the wr instruction 133 * at the start of an I-cache line, and perform a dummy 134 * read back from %tick_cmpr right after writing to it. -DaveM 135 */ 136 __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" 137 " add %1, %2, %0\n\t" 138 ".align 64\n" 139 "1:\n\t" 140 "wr %0, 0, %%tick_cmpr\n\t" 141 "rd %%tick_cmpr, %%g0\n\t" 142 : "=r" (new_compare) 143 : "r" (orig_tick), "r" (adj)); 144 145 __asm__ __volatile__("rd %%tick, %0" 146 : "=r" (new_tick)); 147 new_tick &= ~TICKCMP_IRQ_BIT; 148 149 return ((long)(new_tick - (orig_tick+adj))) > 0L; 150 } 151 152 static unsigned long tick_add_tick(unsigned long adj) 153 { 154 unsigned long new_tick; 155 156 /* Also need to handle Blackbird bug here too. */ 157 __asm__ __volatile__("rd %%tick, %0\n\t" 158 "add %0, %1, %0\n\t" 159 "wrpr %0, 0, %%tick\n\t" 160 : "=&r" (new_tick) 161 : "r" (adj)); 162 163 return new_tick; 164 } 165 166 static unsigned long tick_get_frequency(void) 167 { 168 return local_cpu_data().clock_tick; 169 } 170 171 static struct sparc64_tick_ops tick_operations __cacheline_aligned = { 172 .name = "tick", 173 .init_tick = tick_init_tick, 174 .disable_irq = tick_disable_irq, 175 .get_tick = tick_get_tick, 176 .add_tick = tick_add_tick, 177 .add_compare = tick_add_compare, 178 .get_frequency = tick_get_frequency, 179 .softint_mask = 1UL << 0, 180 }; 181 182 struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations; 183 EXPORT_SYMBOL(tick_ops); 184 185 static void stick_disable_irq(void) 186 { 187 __asm__ __volatile__( 188 "wr %0, 0x0, %%asr25" 189 : /* no outputs */ 190 : "r" (TICKCMP_IRQ_BIT)); 191 } 192 193 static void stick_init_tick(void) 194 { 195 /* Writes to the %tick and %stick register are not 196 * allowed on sun4v. The Hypervisor controls that 197 * bit, per-strand. 198 */ 199 if (tlb_type != hypervisor) { 200 tick_disable_protection(); 201 tick_disable_irq(); 202 203 /* Let the user get at STICK too. */ 204 __asm__ __volatile__( 205 " rd %%asr24, %%g2\n" 206 " andn %%g2, %0, %%g2\n" 207 " wr %%g2, 0, %%asr24" 208 : /* no outputs */ 209 : "r" (TICK_PRIV_BIT) 210 : "g1", "g2"); 211 } 212 213 stick_disable_irq(); 214 } 215 216 static unsigned long long stick_get_tick(void) 217 { 218 unsigned long ret; 219 220 __asm__ __volatile__("rd %%asr24, %0" 221 : "=r" (ret)); 222 223 return ret & ~TICK_PRIV_BIT; 224 } 225 226 static unsigned long stick_add_tick(unsigned long adj) 227 { 228 unsigned long new_tick; 229 230 __asm__ __volatile__("rd %%asr24, %0\n\t" 231 "add %0, %1, %0\n\t" 232 "wr %0, 0, %%asr24\n\t" 233 : "=&r" (new_tick) 234 : "r" (adj)); 235 236 return new_tick; 237 } 238 239 static int stick_add_compare(unsigned long adj) 240 { 241 unsigned long orig_tick, new_tick; 242 243 __asm__ __volatile__("rd %%asr24, %0" 244 : "=r" (orig_tick)); 245 orig_tick &= ~TICKCMP_IRQ_BIT; 246 247 __asm__ __volatile__("wr %0, 0, %%asr25" 248 : /* no outputs */ 249 : "r" (orig_tick + adj)); 250 251 __asm__ __volatile__("rd %%asr24, %0" 252 : "=r" (new_tick)); 253 new_tick &= ~TICKCMP_IRQ_BIT; 254 255 return ((long)(new_tick - (orig_tick+adj))) > 0L; 256 } 257 258 static unsigned long stick_get_frequency(void) 259 { 260 return prom_getint(prom_root_node, "stick-frequency"); 261 } 262 263 static struct sparc64_tick_ops stick_operations __read_mostly = { 264 .name = "stick", 265 .init_tick = stick_init_tick, 266 .disable_irq = stick_disable_irq, 267 .get_tick = stick_get_tick, 268 .add_tick = stick_add_tick, 269 .add_compare = stick_add_compare, 270 .get_frequency = stick_get_frequency, 271 .softint_mask = 1UL << 16, 272 }; 273 274 /* On Hummingbird the STICK/STICK_CMPR register is implemented 275 * in I/O space. There are two 64-bit registers each, the 276 * first holds the low 32-bits of the value and the second holds 277 * the high 32-bits. 278 * 279 * Since STICK is constantly updating, we have to access it carefully. 280 * 281 * The sequence we use to read is: 282 * 1) read high 283 * 2) read low 284 * 3) read high again, if it rolled re-read both low and high again. 285 * 286 * Writing STICK safely is also tricky: 287 * 1) write low to zero 288 * 2) write high 289 * 3) write low 290 */ 291 static unsigned long __hbird_read_stick(void) 292 { 293 unsigned long ret, tmp1, tmp2, tmp3; 294 unsigned long addr = HBIRD_STICK_ADDR+8; 295 296 __asm__ __volatile__("ldxa [%1] %5, %2\n" 297 "1:\n\t" 298 "sub %1, 0x8, %1\n\t" 299 "ldxa [%1] %5, %3\n\t" 300 "add %1, 0x8, %1\n\t" 301 "ldxa [%1] %5, %4\n\t" 302 "cmp %4, %2\n\t" 303 "bne,a,pn %%xcc, 1b\n\t" 304 " mov %4, %2\n\t" 305 "sllx %4, 32, %4\n\t" 306 "or %3, %4, %0\n\t" 307 : "=&r" (ret), "=&r" (addr), 308 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3) 309 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr)); 310 311 return ret; 312 } 313 314 static void __hbird_write_stick(unsigned long val) 315 { 316 unsigned long low = (val & 0xffffffffUL); 317 unsigned long high = (val >> 32UL); 318 unsigned long addr = HBIRD_STICK_ADDR; 319 320 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t" 321 "add %0, 0x8, %0\n\t" 322 "stxa %3, [%0] %4\n\t" 323 "sub %0, 0x8, %0\n\t" 324 "stxa %2, [%0] %4" 325 : "=&r" (addr) 326 : "0" (addr), "r" (low), "r" (high), 327 "i" (ASI_PHYS_BYPASS_EC_E)); 328 } 329 330 static void __hbird_write_compare(unsigned long val) 331 { 332 unsigned long low = (val & 0xffffffffUL); 333 unsigned long high = (val >> 32UL); 334 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL; 335 336 __asm__ __volatile__("stxa %3, [%0] %4\n\t" 337 "sub %0, 0x8, %0\n\t" 338 "stxa %2, [%0] %4" 339 : "=&r" (addr) 340 : "0" (addr), "r" (low), "r" (high), 341 "i" (ASI_PHYS_BYPASS_EC_E)); 342 } 343 344 static void hbtick_disable_irq(void) 345 { 346 __hbird_write_compare(TICKCMP_IRQ_BIT); 347 } 348 349 static void hbtick_init_tick(void) 350 { 351 tick_disable_protection(); 352 353 /* XXX This seems to be necessary to 'jumpstart' Hummingbird 354 * XXX into actually sending STICK interrupts. I think because 355 * XXX of how we store %tick_cmpr in head.S this somehow resets the 356 * XXX {TICK + STICK} interrupt mux. -DaveM 357 */ 358 __hbird_write_stick(__hbird_read_stick()); 359 360 hbtick_disable_irq(); 361 } 362 363 static unsigned long long hbtick_get_tick(void) 364 { 365 return __hbird_read_stick() & ~TICK_PRIV_BIT; 366 } 367 368 static unsigned long hbtick_add_tick(unsigned long adj) 369 { 370 unsigned long val; 371 372 val = __hbird_read_stick() + adj; 373 __hbird_write_stick(val); 374 375 return val; 376 } 377 378 static int hbtick_add_compare(unsigned long adj) 379 { 380 unsigned long val = __hbird_read_stick(); 381 unsigned long val2; 382 383 val &= ~TICKCMP_IRQ_BIT; 384 val += adj; 385 __hbird_write_compare(val); 386 387 val2 = __hbird_read_stick() & ~TICKCMP_IRQ_BIT; 388 389 return ((long)(val2 - val)) > 0L; 390 } 391 392 static unsigned long hbtick_get_frequency(void) 393 { 394 struct device_node *dp = of_find_node_by_path("/"); 395 396 return of_getintprop_default(dp, "stick-frequency", 0); 397 } 398 399 static struct sparc64_tick_ops hbtick_operations __read_mostly = { 400 .name = "hbtick", 401 .init_tick = hbtick_init_tick, 402 .disable_irq = hbtick_disable_irq, 403 .get_tick = hbtick_get_tick, 404 .add_tick = hbtick_add_tick, 405 .add_compare = hbtick_add_compare, 406 .get_frequency = hbtick_get_frequency, 407 .softint_mask = 1UL << 0, 408 }; 409 410 unsigned long cmos_regs; 411 EXPORT_SYMBOL(cmos_regs); 412 413 static struct resource rtc_cmos_resource; 414 415 static struct platform_device rtc_cmos_device = { 416 .name = "rtc_cmos", 417 .id = -1, 418 .resource = &rtc_cmos_resource, 419 .num_resources = 1, 420 }; 421 422 static int rtc_probe(struct platform_device *op) 423 { 424 struct resource *r; 425 426 printk(KERN_INFO "%s: RTC regs at 0x%llx\n", 427 op->dev.of_node->full_name, op->resource[0].start); 428 429 /* The CMOS RTC driver only accepts IORESOURCE_IO, so cons 430 * up a fake resource so that the probe works for all cases. 431 * When the RTC is behind an ISA bus it will have IORESOURCE_IO 432 * already, whereas when it's behind EBUS is will be IORESOURCE_MEM. 433 */ 434 435 r = &rtc_cmos_resource; 436 r->flags = IORESOURCE_IO; 437 r->name = op->resource[0].name; 438 r->start = op->resource[0].start; 439 r->end = op->resource[0].end; 440 441 cmos_regs = op->resource[0].start; 442 return platform_device_register(&rtc_cmos_device); 443 } 444 445 static const struct of_device_id rtc_match[] = { 446 { 447 .name = "rtc", 448 .compatible = "m5819", 449 }, 450 { 451 .name = "rtc", 452 .compatible = "isa-m5819p", 453 }, 454 { 455 .name = "rtc", 456 .compatible = "isa-m5823p", 457 }, 458 { 459 .name = "rtc", 460 .compatible = "ds1287", 461 }, 462 {}, 463 }; 464 465 static struct platform_driver rtc_driver = { 466 .probe = rtc_probe, 467 .driver = { 468 .name = "rtc", 469 .of_match_table = rtc_match, 470 }, 471 }; 472 473 static struct platform_device rtc_bq4802_device = { 474 .name = "rtc-bq4802", 475 .id = -1, 476 .num_resources = 1, 477 }; 478 479 static int bq4802_probe(struct platform_device *op) 480 { 481 482 printk(KERN_INFO "%s: BQ4802 regs at 0x%llx\n", 483 op->dev.of_node->full_name, op->resource[0].start); 484 485 rtc_bq4802_device.resource = &op->resource[0]; 486 return platform_device_register(&rtc_bq4802_device); 487 } 488 489 static const struct of_device_id bq4802_match[] = { 490 { 491 .name = "rtc", 492 .compatible = "bq4802", 493 }, 494 {}, 495 }; 496 497 static struct platform_driver bq4802_driver = { 498 .probe = bq4802_probe, 499 .driver = { 500 .name = "bq4802", 501 .of_match_table = bq4802_match, 502 }, 503 }; 504 505 static unsigned char mostek_read_byte(struct device *dev, u32 ofs) 506 { 507 struct platform_device *pdev = to_platform_device(dev); 508 void __iomem *regs = (void __iomem *) pdev->resource[0].start; 509 510 return readb(regs + ofs); 511 } 512 513 static void mostek_write_byte(struct device *dev, u32 ofs, u8 val) 514 { 515 struct platform_device *pdev = to_platform_device(dev); 516 void __iomem *regs = (void __iomem *) pdev->resource[0].start; 517 518 writeb(val, regs + ofs); 519 } 520 521 static struct m48t59_plat_data m48t59_data = { 522 .read_byte = mostek_read_byte, 523 .write_byte = mostek_write_byte, 524 }; 525 526 static struct platform_device m48t59_rtc = { 527 .name = "rtc-m48t59", 528 .id = 0, 529 .num_resources = 1, 530 .dev = { 531 .platform_data = &m48t59_data, 532 }, 533 }; 534 535 static int mostek_probe(struct platform_device *op) 536 { 537 struct device_node *dp = op->dev.of_node; 538 539 /* On an Enterprise system there can be multiple mostek clocks. 540 * We should only match the one that is on the central FHC bus. 541 */ 542 if (!strcmp(dp->parent->name, "fhc") && 543 strcmp(dp->parent->parent->name, "central") != 0) 544 return -ENODEV; 545 546 printk(KERN_INFO "%s: Mostek regs at 0x%llx\n", 547 dp->full_name, op->resource[0].start); 548 549 m48t59_rtc.resource = &op->resource[0]; 550 return platform_device_register(&m48t59_rtc); 551 } 552 553 static const struct of_device_id mostek_match[] = { 554 { 555 .name = "eeprom", 556 }, 557 {}, 558 }; 559 560 static struct platform_driver mostek_driver = { 561 .probe = mostek_probe, 562 .driver = { 563 .name = "mostek", 564 .of_match_table = mostek_match, 565 }, 566 }; 567 568 static struct platform_device rtc_sun4v_device = { 569 .name = "rtc-sun4v", 570 .id = -1, 571 }; 572 573 static struct platform_device rtc_starfire_device = { 574 .name = "rtc-starfire", 575 .id = -1, 576 }; 577 578 static int __init clock_init(void) 579 { 580 if (this_is_starfire) 581 return platform_device_register(&rtc_starfire_device); 582 583 if (tlb_type == hypervisor) 584 return platform_device_register(&rtc_sun4v_device); 585 586 (void) platform_driver_register(&rtc_driver); 587 (void) platform_driver_register(&mostek_driver); 588 (void) platform_driver_register(&bq4802_driver); 589 590 return 0; 591 } 592 593 /* Must be after subsys_initcall() so that busses are probed. Must 594 * be before device_initcall() because things like the RTC driver 595 * need to see the clock registers. 596 */ 597 fs_initcall(clock_init); 598 599 /* Return true if this is Hummingbird, aka Ultra-IIe */ 600 static bool is_hummingbird(void) 601 { 602 unsigned long ver, manuf, impl; 603 604 __asm__ __volatile__ ("rdpr %%ver, %0" 605 : "=&r" (ver)); 606 manuf = ((ver >> 48) & 0xffff); 607 impl = ((ver >> 32) & 0xffff); 608 609 return (manuf == 0x17 && impl == 0x13); 610 } 611 612 struct freq_table { 613 unsigned long clock_tick_ref; 614 unsigned int ref_freq; 615 }; 616 static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0 }; 617 618 unsigned long sparc64_get_clock_tick(unsigned int cpu) 619 { 620 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu); 621 622 if (ft->clock_tick_ref) 623 return ft->clock_tick_ref; 624 return cpu_data(cpu).clock_tick; 625 } 626 EXPORT_SYMBOL(sparc64_get_clock_tick); 627 628 #ifdef CONFIG_CPU_FREQ 629 630 static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 631 void *data) 632 { 633 struct cpufreq_freqs *freq = data; 634 unsigned int cpu = freq->cpu; 635 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu); 636 637 if (!ft->ref_freq) { 638 ft->ref_freq = freq->old; 639 ft->clock_tick_ref = cpu_data(cpu).clock_tick; 640 } 641 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 642 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { 643 cpu_data(cpu).clock_tick = 644 cpufreq_scale(ft->clock_tick_ref, 645 ft->ref_freq, 646 freq->new); 647 } 648 649 return 0; 650 } 651 652 static struct notifier_block sparc64_cpufreq_notifier_block = { 653 .notifier_call = sparc64_cpufreq_notifier 654 }; 655 656 static int __init register_sparc64_cpufreq_notifier(void) 657 { 658 659 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block, 660 CPUFREQ_TRANSITION_NOTIFIER); 661 return 0; 662 } 663 664 core_initcall(register_sparc64_cpufreq_notifier); 665 666 #endif /* CONFIG_CPU_FREQ */ 667 668 static int sparc64_next_event(unsigned long delta, 669 struct clock_event_device *evt) 670 { 671 return tick_operations.add_compare(delta) ? -ETIME : 0; 672 } 673 674 static int sparc64_timer_shutdown(struct clock_event_device *evt) 675 { 676 tick_operations.disable_irq(); 677 return 0; 678 } 679 680 static struct clock_event_device sparc64_clockevent = { 681 .features = CLOCK_EVT_FEAT_ONESHOT, 682 .set_state_shutdown = sparc64_timer_shutdown, 683 .set_next_event = sparc64_next_event, 684 .rating = 100, 685 .shift = 30, 686 .irq = -1, 687 }; 688 static DEFINE_PER_CPU(struct clock_event_device, sparc64_events); 689 690 void __irq_entry timer_interrupt(int irq, struct pt_regs *regs) 691 { 692 struct pt_regs *old_regs = set_irq_regs(regs); 693 unsigned long tick_mask = tick_operations.softint_mask; 694 int cpu = smp_processor_id(); 695 struct clock_event_device *evt = &per_cpu(sparc64_events, cpu); 696 697 clear_softint(tick_mask); 698 699 irq_enter(); 700 701 local_cpu_data().irq0_irqs++; 702 kstat_incr_irq_this_cpu(0); 703 704 if (unlikely(!evt->event_handler)) { 705 printk(KERN_WARNING 706 "Spurious SPARC64 timer interrupt on cpu %d\n", cpu); 707 } else 708 evt->event_handler(evt); 709 710 irq_exit(); 711 712 set_irq_regs(old_regs); 713 } 714 715 void setup_sparc64_timer(void) 716 { 717 struct clock_event_device *sevt; 718 unsigned long pstate; 719 720 /* Guarantee that the following sequences execute 721 * uninterrupted. 722 */ 723 __asm__ __volatile__("rdpr %%pstate, %0\n\t" 724 "wrpr %0, %1, %%pstate" 725 : "=r" (pstate) 726 : "i" (PSTATE_IE)); 727 728 tick_operations.init_tick(); 729 730 /* Restore PSTATE_IE. */ 731 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" 732 : /* no outputs */ 733 : "r" (pstate)); 734 735 sevt = this_cpu_ptr(&sparc64_events); 736 737 memcpy(sevt, &sparc64_clockevent, sizeof(*sevt)); 738 sevt->cpumask = cpumask_of(smp_processor_id()); 739 740 clockevents_register_device(sevt); 741 } 742 743 #define SPARC64_NSEC_PER_CYC_SHIFT 10UL 744 745 static struct clocksource clocksource_tick = { 746 .rating = 100, 747 .mask = CLOCKSOURCE_MASK(64), 748 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 749 }; 750 751 static unsigned long tb_ticks_per_usec __read_mostly; 752 753 void __delay(unsigned long loops) 754 { 755 unsigned long bclock, now; 756 757 bclock = tick_operations.get_tick(); 758 do { 759 now = tick_operations.get_tick(); 760 } while ((now-bclock) < loops); 761 } 762 EXPORT_SYMBOL(__delay); 763 764 void udelay(unsigned long usecs) 765 { 766 __delay(tb_ticks_per_usec * usecs); 767 } 768 EXPORT_SYMBOL(udelay); 769 770 static u64 clocksource_tick_read(struct clocksource *cs) 771 { 772 return tick_operations.get_tick(); 773 } 774 775 static void __init get_tick_patch(void) 776 { 777 unsigned int *addr, *instr, i; 778 struct get_tick_patch *p; 779 780 if (tlb_type == spitfire && is_hummingbird()) 781 return; 782 783 for (p = &__get_tick_patch; p < &__get_tick_patch_end; p++) { 784 instr = (tlb_type == spitfire) ? p->tick : p->stick; 785 addr = (unsigned int *)(unsigned long)p->addr; 786 for (i = 0; i < GET_TICK_NINSTR; i++) { 787 addr[i] = instr[i]; 788 /* ensure that address is modified before flush */ 789 wmb(); 790 flushi(&addr[i]); 791 } 792 } 793 } 794 795 static void init_tick_ops(struct sparc64_tick_ops *ops) 796 { 797 unsigned long freq, quotient, tick; 798 799 freq = ops->get_frequency(); 800 quotient = clocksource_hz2mult(freq, SPARC64_NSEC_PER_CYC_SHIFT); 801 tick = ops->get_tick(); 802 803 ops->offset = (tick * quotient) >> SPARC64_NSEC_PER_CYC_SHIFT; 804 ops->ticks_per_nsec_quotient = quotient; 805 ops->frequency = freq; 806 tick_operations = *ops; 807 get_tick_patch(); 808 } 809 810 void __init time_init_early(void) 811 { 812 if (tlb_type == spitfire) { 813 if (is_hummingbird()) 814 init_tick_ops(&hbtick_operations); 815 else 816 init_tick_ops(&tick_operations); 817 } else { 818 init_tick_ops(&stick_operations); 819 } 820 } 821 822 void __init time_init(void) 823 { 824 unsigned long freq; 825 826 freq = tick_operations.frequency; 827 tb_ticks_per_usec = freq / USEC_PER_SEC; 828 829 clocksource_tick.name = tick_operations.name; 830 clocksource_tick.read = clocksource_tick_read; 831 832 clocksource_register_hz(&clocksource_tick, freq); 833 printk("clocksource: mult[%x] shift[%d]\n", 834 clocksource_tick.mult, clocksource_tick.shift); 835 836 sparc64_clockevent.name = tick_operations.name; 837 clockevents_calc_mult_shift(&sparc64_clockevent, freq, 4); 838 839 sparc64_clockevent.max_delta_ns = 840 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent); 841 sparc64_clockevent.max_delta_ticks = 0x7fffffffffffffffUL; 842 sparc64_clockevent.min_delta_ns = 843 clockevent_delta2ns(0xF, &sparc64_clockevent); 844 sparc64_clockevent.min_delta_ticks = 0xF; 845 846 printk("clockevent: mult[%x] shift[%d]\n", 847 sparc64_clockevent.mult, sparc64_clockevent.shift); 848 849 setup_sparc64_timer(); 850 } 851 852 unsigned long long sched_clock(void) 853 { 854 unsigned long quotient = tick_operations.ticks_per_nsec_quotient; 855 unsigned long offset = tick_operations.offset; 856 unsigned long ticks = tick_operations.get_tick(); 857 858 return ((ticks * quotient) >> SPARC64_NSEC_PER_CYC_SHIFT) - offset; 859 } 860 861 int read_current_timer(unsigned long *timer_val) 862 { 863 *timer_val = tick_operations.get_tick(); 864 return 0; 865 } 866