1 /* 2 * linux/arch/sparc64/kernel/setup.c 3 * 4 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #include <linux/errno.h> 9 #include <linux/sched.h> 10 #include <linux/kernel.h> 11 #include <linux/mm.h> 12 #include <linux/stddef.h> 13 #include <linux/unistd.h> 14 #include <linux/ptrace.h> 15 #include <asm/smp.h> 16 #include <linux/user.h> 17 #include <linux/screen_info.h> 18 #include <linux/delay.h> 19 #include <linux/fs.h> 20 #include <linux/seq_file.h> 21 #include <linux/syscalls.h> 22 #include <linux/kdev_t.h> 23 #include <linux/major.h> 24 #include <linux/string.h> 25 #include <linux/init.h> 26 #include <linux/inet.h> 27 #include <linux/console.h> 28 #include <linux/root_dev.h> 29 #include <linux/interrupt.h> 30 #include <linux/cpu.h> 31 #include <linux/initrd.h> 32 #include <linux/module.h> 33 #include <linux/start_kernel.h> 34 #include <linux/bootmem.h> 35 36 #include <asm/io.h> 37 #include <asm/processor.h> 38 #include <asm/oplib.h> 39 #include <asm/page.h> 40 #include <asm/pgtable.h> 41 #include <asm/idprom.h> 42 #include <asm/head.h> 43 #include <asm/starfire.h> 44 #include <asm/mmu_context.h> 45 #include <asm/timer.h> 46 #include <asm/sections.h> 47 #include <asm/setup.h> 48 #include <asm/mmu.h> 49 #include <asm/ns87303.h> 50 #include <asm/btext.h> 51 #include <asm/elf.h> 52 #include <asm/mdesc.h> 53 #include <asm/cacheflush.h> 54 #include <asm/dma.h> 55 #include <asm/irq.h> 56 57 #ifdef CONFIG_IP_PNP 58 #include <net/ipconfig.h> 59 #endif 60 61 #include "entry.h" 62 #include "kernel.h" 63 64 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure 65 * operations in asm/ns87303.h 66 */ 67 DEFINE_SPINLOCK(ns87303_lock); 68 EXPORT_SYMBOL(ns87303_lock); 69 70 struct screen_info screen_info = { 71 0, 0, /* orig-x, orig-y */ 72 0, /* unused */ 73 0, /* orig-video-page */ 74 0, /* orig-video-mode */ 75 128, /* orig-video-cols */ 76 0, 0, 0, /* unused, ega_bx, unused */ 77 54, /* orig-video-lines */ 78 0, /* orig-video-isVGA */ 79 16 /* orig-video-points */ 80 }; 81 82 static void 83 prom_console_write(struct console *con, const char *s, unsigned int n) 84 { 85 prom_write(s, n); 86 } 87 88 /* Exported for mm/init.c:paging_init. */ 89 unsigned long cmdline_memory_size = 0; 90 91 static struct console prom_early_console = { 92 .name = "earlyprom", 93 .write = prom_console_write, 94 .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME, 95 .index = -1, 96 }; 97 98 /* 99 * Process kernel command line switches that are specific to the 100 * SPARC or that require special low-level processing. 101 */ 102 static void __init process_switch(char c) 103 { 104 switch (c) { 105 case 'd': 106 case 's': 107 break; 108 case 'h': 109 prom_printf("boot_flags_init: Halt!\n"); 110 prom_halt(); 111 break; 112 case 'p': 113 prom_early_console.flags &= ~CON_BOOT; 114 break; 115 case 'P': 116 /* Force UltraSPARC-III P-Cache on. */ 117 if (tlb_type != cheetah) { 118 printk("BOOT: Ignoring P-Cache force option.\n"); 119 break; 120 } 121 cheetah_pcache_forced_on = 1; 122 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 123 cheetah_enable_pcache(); 124 break; 125 126 default: 127 printk("Unknown boot switch (-%c)\n", c); 128 break; 129 } 130 } 131 132 static void __init boot_flags_init(char *commands) 133 { 134 while (*commands) { 135 /* Move to the start of the next "argument". */ 136 while (*commands == ' ') 137 commands++; 138 139 /* Process any command switches, otherwise skip it. */ 140 if (*commands == '\0') 141 break; 142 if (*commands == '-') { 143 commands++; 144 while (*commands && *commands != ' ') 145 process_switch(*commands++); 146 continue; 147 } 148 if (!strncmp(commands, "mem=", 4)) 149 cmdline_memory_size = memparse(commands + 4, &commands); 150 151 while (*commands && *commands != ' ') 152 commands++; 153 } 154 } 155 156 extern unsigned short root_flags; 157 extern unsigned short root_dev; 158 extern unsigned short ram_flags; 159 #define RAMDISK_IMAGE_START_MASK 0x07FF 160 #define RAMDISK_PROMPT_FLAG 0x8000 161 #define RAMDISK_LOAD_FLAG 0x4000 162 163 extern int root_mountflags; 164 165 char reboot_command[COMMAND_LINE_SIZE]; 166 167 static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 }; 168 169 static void __init per_cpu_patch(void) 170 { 171 struct cpuid_patch_entry *p; 172 unsigned long ver; 173 int is_jbus; 174 175 if (tlb_type == spitfire && !this_is_starfire) 176 return; 177 178 is_jbus = 0; 179 if (tlb_type != hypervisor) { 180 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 181 is_jbus = ((ver >> 32UL) == __JALAPENO_ID || 182 (ver >> 32UL) == __SERRANO_ID); 183 } 184 185 p = &__cpuid_patch; 186 while (p < &__cpuid_patch_end) { 187 unsigned long addr = p->addr; 188 unsigned int *insns; 189 190 switch (tlb_type) { 191 case spitfire: 192 insns = &p->starfire[0]; 193 break; 194 case cheetah: 195 case cheetah_plus: 196 if (is_jbus) 197 insns = &p->cheetah_jbus[0]; 198 else 199 insns = &p->cheetah_safari[0]; 200 break; 201 case hypervisor: 202 insns = &p->sun4v[0]; 203 break; 204 default: 205 prom_printf("Unknown cpu type, halting.\n"); 206 prom_halt(); 207 } 208 209 *(unsigned int *) (addr + 0) = insns[0]; 210 wmb(); 211 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); 212 213 *(unsigned int *) (addr + 4) = insns[1]; 214 wmb(); 215 __asm__ __volatile__("flush %0" : : "r" (addr + 4)); 216 217 *(unsigned int *) (addr + 8) = insns[2]; 218 wmb(); 219 __asm__ __volatile__("flush %0" : : "r" (addr + 8)); 220 221 *(unsigned int *) (addr + 12) = insns[3]; 222 wmb(); 223 __asm__ __volatile__("flush %0" : : "r" (addr + 12)); 224 225 p++; 226 } 227 } 228 229 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start, 230 struct sun4v_1insn_patch_entry *end) 231 { 232 while (start < end) { 233 unsigned long addr = start->addr; 234 235 *(unsigned int *) (addr + 0) = start->insn; 236 wmb(); 237 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); 238 239 start++; 240 } 241 } 242 243 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start, 244 struct sun4v_2insn_patch_entry *end) 245 { 246 while (start < end) { 247 unsigned long addr = start->addr; 248 249 *(unsigned int *) (addr + 0) = start->insns[0]; 250 wmb(); 251 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); 252 253 *(unsigned int *) (addr + 4) = start->insns[1]; 254 wmb(); 255 __asm__ __volatile__("flush %0" : : "r" (addr + 4)); 256 257 start++; 258 } 259 } 260 261 void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start, 262 struct sun4v_2insn_patch_entry *end) 263 { 264 while (start < end) { 265 unsigned long addr = start->addr; 266 267 *(unsigned int *) (addr + 0) = start->insns[0]; 268 wmb(); 269 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); 270 271 *(unsigned int *) (addr + 4) = start->insns[1]; 272 wmb(); 273 __asm__ __volatile__("flush %0" : : "r" (addr + 4)); 274 275 start++; 276 } 277 } 278 279 static void __init sun4v_patch(void) 280 { 281 extern void sun4v_hvapi_init(void); 282 283 if (tlb_type != hypervisor) 284 return; 285 286 sun4v_patch_1insn_range(&__sun4v_1insn_patch, 287 &__sun4v_1insn_patch_end); 288 289 sun4v_patch_2insn_range(&__sun4v_2insn_patch, 290 &__sun4v_2insn_patch_end); 291 292 switch (sun4v_chip_type) { 293 case SUN4V_CHIP_SPARC_M7: 294 case SUN4V_CHIP_SPARC_M8: 295 case SUN4V_CHIP_SPARC_SN: 296 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch, 297 &__sun_m7_2insn_patch_end); 298 break; 299 default: 300 break; 301 } 302 303 if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) { 304 sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch, 305 &__fast_win_ctrl_1insn_patch_end); 306 } 307 308 sun4v_hvapi_init(); 309 } 310 311 static void __init popc_patch(void) 312 { 313 struct popc_3insn_patch_entry *p3; 314 struct popc_6insn_patch_entry *p6; 315 316 p3 = &__popc_3insn_patch; 317 while (p3 < &__popc_3insn_patch_end) { 318 unsigned long i, addr = p3->addr; 319 320 for (i = 0; i < 3; i++) { 321 *(unsigned int *) (addr + (i * 4)) = p3->insns[i]; 322 wmb(); 323 __asm__ __volatile__("flush %0" 324 : : "r" (addr + (i * 4))); 325 } 326 327 p3++; 328 } 329 330 p6 = &__popc_6insn_patch; 331 while (p6 < &__popc_6insn_patch_end) { 332 unsigned long i, addr = p6->addr; 333 334 for (i = 0; i < 6; i++) { 335 *(unsigned int *) (addr + (i * 4)) = p6->insns[i]; 336 wmb(); 337 __asm__ __volatile__("flush %0" 338 : : "r" (addr + (i * 4))); 339 } 340 341 p6++; 342 } 343 } 344 345 static void __init pause_patch(void) 346 { 347 struct pause_patch_entry *p; 348 349 p = &__pause_3insn_patch; 350 while (p < &__pause_3insn_patch_end) { 351 unsigned long i, addr = p->addr; 352 353 for (i = 0; i < 3; i++) { 354 *(unsigned int *) (addr + (i * 4)) = p->insns[i]; 355 wmb(); 356 __asm__ __volatile__("flush %0" 357 : : "r" (addr + (i * 4))); 358 } 359 360 p++; 361 } 362 } 363 364 void __init start_early_boot(void) 365 { 366 int cpu; 367 368 check_if_starfire(); 369 per_cpu_patch(); 370 sun4v_patch(); 371 smp_init_cpu_poke(); 372 373 cpu = hard_smp_processor_id(); 374 if (cpu >= NR_CPUS) { 375 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n", 376 cpu, NR_CPUS); 377 prom_halt(); 378 } 379 current_thread_info()->cpu = cpu; 380 381 time_init_early(); 382 prom_init_report(); 383 start_kernel(); 384 } 385 386 /* On Ultra, we support all of the v8 capabilities. */ 387 unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | 388 HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | 389 HWCAP_SPARC_V9); 390 EXPORT_SYMBOL(sparc64_elf_hwcap); 391 392 static const char *hwcaps[] = { 393 "flush", "stbar", "swap", "muldiv", "v9", 394 "ultra3", "blkinit", "n2", 395 396 /* These strings are as they appear in the machine description 397 * 'hwcap-list' property for cpu nodes. 398 */ 399 "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2", 400 "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau", 401 "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */, 402 "adp", 403 }; 404 405 static const char *crypto_hwcaps[] = { 406 "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256", 407 "sha512", "mpmul", "montmul", "montsqr", "crc32c", 408 }; 409 410 void cpucap_info(struct seq_file *m) 411 { 412 unsigned long caps = sparc64_elf_hwcap; 413 int i, printed = 0; 414 415 seq_puts(m, "cpucaps\t\t: "); 416 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { 417 unsigned long bit = 1UL << i; 418 if (hwcaps[i] && (caps & bit)) { 419 seq_printf(m, "%s%s", 420 printed ? "," : "", hwcaps[i]); 421 printed++; 422 } 423 } 424 if (caps & HWCAP_SPARC_CRYPTO) { 425 unsigned long cfr; 426 427 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr)); 428 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { 429 unsigned long bit = 1UL << i; 430 if (cfr & bit) { 431 seq_printf(m, "%s%s", 432 printed ? "," : "", crypto_hwcaps[i]); 433 printed++; 434 } 435 } 436 } 437 seq_putc(m, '\n'); 438 } 439 440 static void __init report_one_hwcap(int *printed, const char *name) 441 { 442 if ((*printed) == 0) 443 printk(KERN_INFO "CPU CAPS: ["); 444 printk(KERN_CONT "%s%s", 445 (*printed) ? "," : "", name); 446 if (++(*printed) == 8) { 447 printk(KERN_CONT "]\n"); 448 *printed = 0; 449 } 450 } 451 452 static void __init report_crypto_hwcaps(int *printed) 453 { 454 unsigned long cfr; 455 int i; 456 457 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr)); 458 459 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { 460 unsigned long bit = 1UL << i; 461 if (cfr & bit) 462 report_one_hwcap(printed, crypto_hwcaps[i]); 463 } 464 } 465 466 static void __init report_hwcaps(unsigned long caps) 467 { 468 int i, printed = 0; 469 470 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { 471 unsigned long bit = 1UL << i; 472 if (hwcaps[i] && (caps & bit)) 473 report_one_hwcap(&printed, hwcaps[i]); 474 } 475 if (caps & HWCAP_SPARC_CRYPTO) 476 report_crypto_hwcaps(&printed); 477 if (printed != 0) 478 printk(KERN_CONT "]\n"); 479 } 480 481 static unsigned long __init mdesc_cpu_hwcap_list(void) 482 { 483 struct mdesc_handle *hp; 484 unsigned long caps = 0; 485 const char *prop; 486 int len; 487 u64 pn; 488 489 hp = mdesc_grab(); 490 if (!hp) 491 return 0; 492 493 pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu"); 494 if (pn == MDESC_NODE_NULL) 495 goto out; 496 497 prop = mdesc_get_property(hp, pn, "hwcap-list", &len); 498 if (!prop) 499 goto out; 500 501 while (len) { 502 int i, plen; 503 504 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { 505 unsigned long bit = 1UL << i; 506 507 if (hwcaps[i] && !strcmp(prop, hwcaps[i])) { 508 caps |= bit; 509 break; 510 } 511 } 512 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { 513 if (!strcmp(prop, crypto_hwcaps[i])) 514 caps |= HWCAP_SPARC_CRYPTO; 515 } 516 517 plen = strlen(prop) + 1; 518 prop += plen; 519 len -= plen; 520 } 521 522 out: 523 mdesc_release(hp); 524 return caps; 525 } 526 527 /* This yields a mask that user programs can use to figure out what 528 * instruction set this cpu supports. 529 */ 530 static void __init init_sparc64_elf_hwcap(void) 531 { 532 unsigned long cap = sparc64_elf_hwcap; 533 unsigned long mdesc_caps; 534 535 if (tlb_type == cheetah || tlb_type == cheetah_plus) 536 cap |= HWCAP_SPARC_ULTRA3; 537 else if (tlb_type == hypervisor) { 538 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || 539 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 540 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 541 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 542 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 543 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 544 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 545 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 || 546 sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 547 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 548 cap |= HWCAP_SPARC_BLKINIT; 549 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 550 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 551 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 552 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 553 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 554 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 555 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 || 556 sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 557 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 558 cap |= HWCAP_SPARC_N2; 559 } 560 561 cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS); 562 563 mdesc_caps = mdesc_cpu_hwcap_list(); 564 if (!mdesc_caps) { 565 if (tlb_type == spitfire) 566 cap |= AV_SPARC_VIS; 567 if (tlb_type == cheetah || tlb_type == cheetah_plus) 568 cap |= AV_SPARC_VIS | AV_SPARC_VIS2; 569 if (tlb_type == cheetah_plus) { 570 unsigned long impl, ver; 571 572 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 573 impl = ((ver >> 32) & 0xffff); 574 if (impl == PANTHER_IMPL) 575 cap |= AV_SPARC_POPC; 576 } 577 if (tlb_type == hypervisor) { 578 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1) 579 cap |= AV_SPARC_ASI_BLK_INIT; 580 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 581 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 582 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 583 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 584 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 585 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 586 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 || 587 sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 588 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 589 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | 590 AV_SPARC_ASI_BLK_INIT | 591 AV_SPARC_POPC); 592 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 593 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 594 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 595 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 596 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 597 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 || 598 sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 599 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 600 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | 601 AV_SPARC_FMAF); 602 } 603 } 604 sparc64_elf_hwcap = cap | mdesc_caps; 605 606 report_hwcaps(sparc64_elf_hwcap); 607 608 if (sparc64_elf_hwcap & AV_SPARC_POPC) 609 popc_patch(); 610 if (sparc64_elf_hwcap & AV_SPARC_PAUSE) 611 pause_patch(); 612 } 613 614 void __init alloc_irqstack_bootmem(void) 615 { 616 unsigned int i, node; 617 618 for_each_possible_cpu(i) { 619 node = cpu_to_node(i); 620 621 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node), 622 THREAD_SIZE, 623 THREAD_SIZE, 0); 624 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node), 625 THREAD_SIZE, 626 THREAD_SIZE, 0); 627 } 628 } 629 630 void __init setup_arch(char **cmdline_p) 631 { 632 /* Initialize PROM console and command line. */ 633 *cmdline_p = prom_getbootargs(); 634 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 635 parse_early_param(); 636 637 boot_flags_init(*cmdline_p); 638 #ifdef CONFIG_EARLYFB 639 if (btext_find_display()) 640 #endif 641 register_console(&prom_early_console); 642 643 if (tlb_type == hypervisor) 644 printk("ARCH: SUN4V\n"); 645 else 646 printk("ARCH: SUN4U\n"); 647 648 #ifdef CONFIG_DUMMY_CONSOLE 649 conswitchp = &dummy_con; 650 #endif 651 652 idprom_init(); 653 654 if (!root_flags) 655 root_mountflags &= ~MS_RDONLY; 656 ROOT_DEV = old_decode_dev(root_dev); 657 #ifdef CONFIG_BLK_DEV_RAM 658 rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK; 659 rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0); 660 rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0); 661 #endif 662 663 task_thread_info(&init_task)->kregs = &fake_swapper_regs; 664 665 #ifdef CONFIG_IP_PNP 666 if (!ic_set_manually) { 667 phandle chosen = prom_finddevice("/chosen"); 668 u32 cl, sv, gw; 669 670 cl = prom_getintdefault (chosen, "client-ip", 0); 671 sv = prom_getintdefault (chosen, "server-ip", 0); 672 gw = prom_getintdefault (chosen, "gateway-ip", 0); 673 if (cl && sv) { 674 ic_myaddr = cl; 675 ic_servaddr = sv; 676 if (gw) 677 ic_gateway = gw; 678 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP) 679 ic_proto_enabled = 0; 680 #endif 681 } 682 } 683 #endif 684 685 /* Get boot processor trap_block[] setup. */ 686 init_cur_cpu_trap(current_thread_info()); 687 688 paging_init(); 689 init_sparc64_elf_hwcap(); 690 smp_fill_in_cpu_possible_map(); 691 /* 692 * Once the OF device tree and MDESC have been setup and nr_cpus has 693 * been parsed, we know the list of possible cpus. Therefore we can 694 * allocate the IRQ stacks. 695 */ 696 alloc_irqstack_bootmem(); 697 } 698 699 extern int stop_a_enabled; 700 701 void sun_do_break(void) 702 { 703 if (!stop_a_enabled) 704 return; 705 706 prom_printf("\n"); 707 flush_user_windows(); 708 709 prom_cmdline(); 710 } 711 EXPORT_SYMBOL(sun_do_break); 712 713 int stop_a_enabled = 1; 714 EXPORT_SYMBOL(stop_a_enabled); 715