1 /* 2 * linux/arch/sparc64/kernel/setup.c 3 * 4 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #include <linux/errno.h> 9 #include <linux/sched.h> 10 #include <linux/kernel.h> 11 #include <linux/mm.h> 12 #include <linux/stddef.h> 13 #include <linux/unistd.h> 14 #include <linux/ptrace.h> 15 #include <asm/smp.h> 16 #include <linux/user.h> 17 #include <linux/screen_info.h> 18 #include <linux/delay.h> 19 #include <linux/fs.h> 20 #include <linux/seq_file.h> 21 #include <linux/syscalls.h> 22 #include <linux/kdev_t.h> 23 #include <linux/major.h> 24 #include <linux/string.h> 25 #include <linux/init.h> 26 #include <linux/inet.h> 27 #include <linux/console.h> 28 #include <linux/root_dev.h> 29 #include <linux/interrupt.h> 30 #include <linux/cpu.h> 31 #include <linux/initrd.h> 32 #include <linux/module.h> 33 #include <linux/start_kernel.h> 34 35 #include <asm/io.h> 36 #include <asm/processor.h> 37 #include <asm/oplib.h> 38 #include <asm/page.h> 39 #include <asm/pgtable.h> 40 #include <asm/idprom.h> 41 #include <asm/head.h> 42 #include <asm/starfire.h> 43 #include <asm/mmu_context.h> 44 #include <asm/timer.h> 45 #include <asm/sections.h> 46 #include <asm/setup.h> 47 #include <asm/mmu.h> 48 #include <asm/ns87303.h> 49 #include <asm/btext.h> 50 #include <asm/elf.h> 51 #include <asm/mdesc.h> 52 #include <asm/cacheflush.h> 53 54 #ifdef CONFIG_IP_PNP 55 #include <net/ipconfig.h> 56 #endif 57 58 #include "entry.h" 59 #include "kernel.h" 60 61 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure 62 * operations in asm/ns87303.h 63 */ 64 DEFINE_SPINLOCK(ns87303_lock); 65 EXPORT_SYMBOL(ns87303_lock); 66 67 struct screen_info screen_info = { 68 0, 0, /* orig-x, orig-y */ 69 0, /* unused */ 70 0, /* orig-video-page */ 71 0, /* orig-video-mode */ 72 128, /* orig-video-cols */ 73 0, 0, 0, /* unused, ega_bx, unused */ 74 54, /* orig-video-lines */ 75 0, /* orig-video-isVGA */ 76 16 /* orig-video-points */ 77 }; 78 79 static void 80 prom_console_write(struct console *con, const char *s, unsigned n) 81 { 82 prom_write(s, n); 83 } 84 85 /* Exported for mm/init.c:paging_init. */ 86 unsigned long cmdline_memory_size = 0; 87 88 static struct console prom_early_console = { 89 .name = "earlyprom", 90 .write = prom_console_write, 91 .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME, 92 .index = -1, 93 }; 94 95 /* 96 * Process kernel command line switches that are specific to the 97 * SPARC or that require special low-level processing. 98 */ 99 static void __init process_switch(char c) 100 { 101 switch (c) { 102 case 'd': 103 case 's': 104 break; 105 case 'h': 106 prom_printf("boot_flags_init: Halt!\n"); 107 prom_halt(); 108 break; 109 case 'p': 110 prom_early_console.flags &= ~CON_BOOT; 111 break; 112 case 'P': 113 /* Force UltraSPARC-III P-Cache on. */ 114 if (tlb_type != cheetah) { 115 printk("BOOT: Ignoring P-Cache force option.\n"); 116 break; 117 } 118 cheetah_pcache_forced_on = 1; 119 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 120 cheetah_enable_pcache(); 121 break; 122 123 default: 124 printk("Unknown boot switch (-%c)\n", c); 125 break; 126 } 127 } 128 129 static void __init boot_flags_init(char *commands) 130 { 131 while (*commands) { 132 /* Move to the start of the next "argument". */ 133 while (*commands && *commands == ' ') 134 commands++; 135 136 /* Process any command switches, otherwise skip it. */ 137 if (*commands == '\0') 138 break; 139 if (*commands == '-') { 140 commands++; 141 while (*commands && *commands != ' ') 142 process_switch(*commands++); 143 continue; 144 } 145 if (!strncmp(commands, "mem=", 4)) 146 cmdline_memory_size = memparse(commands + 4, &commands); 147 148 while (*commands && *commands != ' ') 149 commands++; 150 } 151 } 152 153 extern unsigned short root_flags; 154 extern unsigned short root_dev; 155 extern unsigned short ram_flags; 156 #define RAMDISK_IMAGE_START_MASK 0x07FF 157 #define RAMDISK_PROMPT_FLAG 0x8000 158 #define RAMDISK_LOAD_FLAG 0x4000 159 160 extern int root_mountflags; 161 162 char reboot_command[COMMAND_LINE_SIZE]; 163 164 static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 }; 165 166 static void __init per_cpu_patch(void) 167 { 168 struct cpuid_patch_entry *p; 169 unsigned long ver; 170 int is_jbus; 171 172 if (tlb_type == spitfire && !this_is_starfire) 173 return; 174 175 is_jbus = 0; 176 if (tlb_type != hypervisor) { 177 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 178 is_jbus = ((ver >> 32UL) == __JALAPENO_ID || 179 (ver >> 32UL) == __SERRANO_ID); 180 } 181 182 p = &__cpuid_patch; 183 while (p < &__cpuid_patch_end) { 184 unsigned long addr = p->addr; 185 unsigned int *insns; 186 187 switch (tlb_type) { 188 case spitfire: 189 insns = &p->starfire[0]; 190 break; 191 case cheetah: 192 case cheetah_plus: 193 if (is_jbus) 194 insns = &p->cheetah_jbus[0]; 195 else 196 insns = &p->cheetah_safari[0]; 197 break; 198 case hypervisor: 199 insns = &p->sun4v[0]; 200 break; 201 default: 202 prom_printf("Unknown cpu type, halting.\n"); 203 prom_halt(); 204 } 205 206 *(unsigned int *) (addr + 0) = insns[0]; 207 wmb(); 208 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); 209 210 *(unsigned int *) (addr + 4) = insns[1]; 211 wmb(); 212 __asm__ __volatile__("flush %0" : : "r" (addr + 4)); 213 214 *(unsigned int *) (addr + 8) = insns[2]; 215 wmb(); 216 __asm__ __volatile__("flush %0" : : "r" (addr + 8)); 217 218 *(unsigned int *) (addr + 12) = insns[3]; 219 wmb(); 220 __asm__ __volatile__("flush %0" : : "r" (addr + 12)); 221 222 p++; 223 } 224 } 225 226 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start, 227 struct sun4v_1insn_patch_entry *end) 228 { 229 while (start < end) { 230 unsigned long addr = start->addr; 231 232 *(unsigned int *) (addr + 0) = start->insn; 233 wmb(); 234 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); 235 236 start++; 237 } 238 } 239 240 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start, 241 struct sun4v_2insn_patch_entry *end) 242 { 243 while (start < end) { 244 unsigned long addr = start->addr; 245 246 *(unsigned int *) (addr + 0) = start->insns[0]; 247 wmb(); 248 __asm__ __volatile__("flush %0" : : "r" (addr + 0)); 249 250 *(unsigned int *) (addr + 4) = start->insns[1]; 251 wmb(); 252 __asm__ __volatile__("flush %0" : : "r" (addr + 4)); 253 254 start++; 255 } 256 } 257 258 static void __init sun4v_patch(void) 259 { 260 extern void sun4v_hvapi_init(void); 261 262 if (tlb_type != hypervisor) 263 return; 264 265 sun4v_patch_1insn_range(&__sun4v_1insn_patch, 266 &__sun4v_1insn_patch_end); 267 268 sun4v_patch_2insn_range(&__sun4v_2insn_patch, 269 &__sun4v_2insn_patch_end); 270 271 sun4v_hvapi_init(); 272 } 273 274 static void __init popc_patch(void) 275 { 276 struct popc_3insn_patch_entry *p3; 277 struct popc_6insn_patch_entry *p6; 278 279 p3 = &__popc_3insn_patch; 280 while (p3 < &__popc_3insn_patch_end) { 281 unsigned long i, addr = p3->addr; 282 283 for (i = 0; i < 3; i++) { 284 *(unsigned int *) (addr + (i * 4)) = p3->insns[i]; 285 wmb(); 286 __asm__ __volatile__("flush %0" 287 : : "r" (addr + (i * 4))); 288 } 289 290 p3++; 291 } 292 293 p6 = &__popc_6insn_patch; 294 while (p6 < &__popc_6insn_patch_end) { 295 unsigned long i, addr = p6->addr; 296 297 for (i = 0; i < 6; i++) { 298 *(unsigned int *) (addr + (i * 4)) = p6->insns[i]; 299 wmb(); 300 __asm__ __volatile__("flush %0" 301 : : "r" (addr + (i * 4))); 302 } 303 304 p6++; 305 } 306 } 307 308 static void __init pause_patch(void) 309 { 310 struct pause_patch_entry *p; 311 312 p = &__pause_3insn_patch; 313 while (p < &__pause_3insn_patch_end) { 314 unsigned long i, addr = p->addr; 315 316 for (i = 0; i < 3; i++) { 317 *(unsigned int *) (addr + (i * 4)) = p->insns[i]; 318 wmb(); 319 __asm__ __volatile__("flush %0" 320 : : "r" (addr + (i * 4))); 321 } 322 323 p++; 324 } 325 } 326 327 void __init start_early_boot(void) 328 { 329 int cpu; 330 331 check_if_starfire(); 332 per_cpu_patch(); 333 sun4v_patch(); 334 335 cpu = hard_smp_processor_id(); 336 if (cpu >= NR_CPUS) { 337 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n", 338 cpu, NR_CPUS); 339 prom_halt(); 340 } 341 current_thread_info()->cpu = cpu; 342 343 prom_init_report(); 344 start_kernel(); 345 } 346 347 /* On Ultra, we support all of the v8 capabilities. */ 348 unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | 349 HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | 350 HWCAP_SPARC_V9); 351 EXPORT_SYMBOL(sparc64_elf_hwcap); 352 353 static const char *hwcaps[] = { 354 "flush", "stbar", "swap", "muldiv", "v9", 355 "ultra3", "blkinit", "n2", 356 357 /* These strings are as they appear in the machine description 358 * 'hwcap-list' property for cpu nodes. 359 */ 360 "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2", 361 "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau", 362 "ima", "cspare", "pause", "cbcond", 363 }; 364 365 static const char *crypto_hwcaps[] = { 366 "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256", 367 "sha512", "mpmul", "montmul", "montsqr", "crc32c", 368 }; 369 370 void cpucap_info(struct seq_file *m) 371 { 372 unsigned long caps = sparc64_elf_hwcap; 373 int i, printed = 0; 374 375 seq_puts(m, "cpucaps\t\t: "); 376 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { 377 unsigned long bit = 1UL << i; 378 if (caps & bit) { 379 seq_printf(m, "%s%s", 380 printed ? "," : "", hwcaps[i]); 381 printed++; 382 } 383 } 384 if (caps & HWCAP_SPARC_CRYPTO) { 385 unsigned long cfr; 386 387 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr)); 388 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { 389 unsigned long bit = 1UL << i; 390 if (cfr & bit) { 391 seq_printf(m, "%s%s", 392 printed ? "," : "", crypto_hwcaps[i]); 393 printed++; 394 } 395 } 396 } 397 seq_putc(m, '\n'); 398 } 399 400 static void __init report_one_hwcap(int *printed, const char *name) 401 { 402 if ((*printed) == 0) 403 printk(KERN_INFO "CPU CAPS: ["); 404 printk(KERN_CONT "%s%s", 405 (*printed) ? "," : "", name); 406 if (++(*printed) == 8) { 407 printk(KERN_CONT "]\n"); 408 *printed = 0; 409 } 410 } 411 412 static void __init report_crypto_hwcaps(int *printed) 413 { 414 unsigned long cfr; 415 int i; 416 417 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr)); 418 419 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { 420 unsigned long bit = 1UL << i; 421 if (cfr & bit) 422 report_one_hwcap(printed, crypto_hwcaps[i]); 423 } 424 } 425 426 static void __init report_hwcaps(unsigned long caps) 427 { 428 int i, printed = 0; 429 430 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { 431 unsigned long bit = 1UL << i; 432 if (caps & bit) 433 report_one_hwcap(&printed, hwcaps[i]); 434 } 435 if (caps & HWCAP_SPARC_CRYPTO) 436 report_crypto_hwcaps(&printed); 437 if (printed != 0) 438 printk(KERN_CONT "]\n"); 439 } 440 441 static unsigned long __init mdesc_cpu_hwcap_list(void) 442 { 443 struct mdesc_handle *hp; 444 unsigned long caps = 0; 445 const char *prop; 446 int len; 447 u64 pn; 448 449 hp = mdesc_grab(); 450 if (!hp) 451 return 0; 452 453 pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu"); 454 if (pn == MDESC_NODE_NULL) 455 goto out; 456 457 prop = mdesc_get_property(hp, pn, "hwcap-list", &len); 458 if (!prop) 459 goto out; 460 461 while (len) { 462 int i, plen; 463 464 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { 465 unsigned long bit = 1UL << i; 466 467 if (!strcmp(prop, hwcaps[i])) { 468 caps |= bit; 469 break; 470 } 471 } 472 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { 473 if (!strcmp(prop, crypto_hwcaps[i])) 474 caps |= HWCAP_SPARC_CRYPTO; 475 } 476 477 plen = strlen(prop) + 1; 478 prop += plen; 479 len -= plen; 480 } 481 482 out: 483 mdesc_release(hp); 484 return caps; 485 } 486 487 /* This yields a mask that user programs can use to figure out what 488 * instruction set this cpu supports. 489 */ 490 static void __init init_sparc64_elf_hwcap(void) 491 { 492 unsigned long cap = sparc64_elf_hwcap; 493 unsigned long mdesc_caps; 494 495 if (tlb_type == cheetah || tlb_type == cheetah_plus) 496 cap |= HWCAP_SPARC_ULTRA3; 497 else if (tlb_type == hypervisor) { 498 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || 499 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 500 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 501 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 502 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 503 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 504 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 505 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 506 cap |= HWCAP_SPARC_BLKINIT; 507 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 508 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 509 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 510 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 511 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 512 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 513 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 514 cap |= HWCAP_SPARC_N2; 515 } 516 517 cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS); 518 519 mdesc_caps = mdesc_cpu_hwcap_list(); 520 if (!mdesc_caps) { 521 if (tlb_type == spitfire) 522 cap |= AV_SPARC_VIS; 523 if (tlb_type == cheetah || tlb_type == cheetah_plus) 524 cap |= AV_SPARC_VIS | AV_SPARC_VIS2; 525 if (tlb_type == cheetah_plus) { 526 unsigned long impl, ver; 527 528 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); 529 impl = ((ver >> 32) & 0xffff); 530 if (impl == PANTHER_IMPL) 531 cap |= AV_SPARC_POPC; 532 } 533 if (tlb_type == hypervisor) { 534 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1) 535 cap |= AV_SPARC_ASI_BLK_INIT; 536 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 537 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 538 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 539 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 540 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 541 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 542 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 543 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | 544 AV_SPARC_ASI_BLK_INIT | 545 AV_SPARC_POPC); 546 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 547 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 548 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 549 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 550 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 551 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 552 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | 553 AV_SPARC_FMAF); 554 } 555 } 556 sparc64_elf_hwcap = cap | mdesc_caps; 557 558 report_hwcaps(sparc64_elf_hwcap); 559 560 if (sparc64_elf_hwcap & AV_SPARC_POPC) 561 popc_patch(); 562 if (sparc64_elf_hwcap & AV_SPARC_PAUSE) 563 pause_patch(); 564 } 565 566 void __init setup_arch(char **cmdline_p) 567 { 568 /* Initialize PROM console and command line. */ 569 *cmdline_p = prom_getbootargs(); 570 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 571 parse_early_param(); 572 573 boot_flags_init(*cmdline_p); 574 #ifdef CONFIG_EARLYFB 575 if (btext_find_display()) 576 #endif 577 register_console(&prom_early_console); 578 579 if (tlb_type == hypervisor) 580 printk("ARCH: SUN4V\n"); 581 else 582 printk("ARCH: SUN4U\n"); 583 584 #ifdef CONFIG_DUMMY_CONSOLE 585 conswitchp = &dummy_con; 586 #endif 587 588 idprom_init(); 589 590 if (!root_flags) 591 root_mountflags &= ~MS_RDONLY; 592 ROOT_DEV = old_decode_dev(root_dev); 593 #ifdef CONFIG_BLK_DEV_RAM 594 rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK; 595 rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0); 596 rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0); 597 #endif 598 599 task_thread_info(&init_task)->kregs = &fake_swapper_regs; 600 601 #ifdef CONFIG_IP_PNP 602 if (!ic_set_manually) { 603 phandle chosen = prom_finddevice("/chosen"); 604 u32 cl, sv, gw; 605 606 cl = prom_getintdefault (chosen, "client-ip", 0); 607 sv = prom_getintdefault (chosen, "server-ip", 0); 608 gw = prom_getintdefault (chosen, "gateway-ip", 0); 609 if (cl && sv) { 610 ic_myaddr = cl; 611 ic_servaddr = sv; 612 if (gw) 613 ic_gateway = gw; 614 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP) 615 ic_proto_enabled = 0; 616 #endif 617 } 618 } 619 #endif 620 621 /* Get boot processor trap_block[] setup. */ 622 init_cur_cpu_trap(current_thread_info()); 623 624 paging_init(); 625 init_sparc64_elf_hwcap(); 626 } 627 628 extern int stop_a_enabled; 629 630 void sun_do_break(void) 631 { 632 if (!stop_a_enabled) 633 return; 634 635 prom_printf("\n"); 636 flush_user_windows(); 637 638 prom_cmdline(); 639 } 640 EXPORT_SYMBOL(sun_do_break); 641 642 int stop_a_enabled = 1; 643 EXPORT_SYMBOL(stop_a_enabled); 644