1 /* 2 * sbus.c: UltraSparc SBUS controller support. 3 * 4 * Copyright (C) 1999 David S. Miller (davem@redhat.com) 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/mm.h> 10 #include <linux/spinlock.h> 11 #include <linux/slab.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 17 #include <asm/page.h> 18 #include <asm/io.h> 19 #include <asm/upa.h> 20 #include <asm/cache.h> 21 #include <asm/dma.h> 22 #include <asm/irq.h> 23 #include <asm/prom.h> 24 #include <asm/oplib.h> 25 #include <asm/starfire.h> 26 27 #include "iommu_common.h" 28 29 #define MAP_BASE ((u32)0xc0000000) 30 31 /* Offsets from iommu_regs */ 32 #define SYSIO_IOMMUREG_BASE 0x2400UL 33 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */ 34 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */ 35 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */ 36 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */ 37 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */ 38 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */ 39 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */ 40 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */ 41 42 #define IOMMU_DRAM_VALID (1UL << 30UL) 43 44 /* Offsets from strbuf_regs */ 45 #define SYSIO_STRBUFREG_BASE 0x2800UL 46 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */ 47 #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */ 48 #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */ 49 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */ 50 #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */ 51 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */ 52 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */ 53 54 #define STRBUF_TAG_VALID 0x02UL 55 56 /* Enable 64-bit DVMA mode for the given device. */ 57 void sbus_set_sbus64(struct device *dev, int bursts) 58 { 59 struct iommu *iommu = dev->archdata.iommu; 60 struct platform_device *op = to_platform_device(dev); 61 const struct linux_prom_registers *regs; 62 unsigned long cfg_reg; 63 int slot; 64 u64 val; 65 66 regs = of_get_property(op->dev.of_node, "reg", NULL); 67 if (!regs) { 68 printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %s\n", 69 op->dev.of_node->full_name); 70 return; 71 } 72 slot = regs->which_io; 73 74 cfg_reg = iommu->write_complete_reg; 75 switch (slot) { 76 case 0: 77 cfg_reg += 0x20UL; 78 break; 79 case 1: 80 cfg_reg += 0x28UL; 81 break; 82 case 2: 83 cfg_reg += 0x30UL; 84 break; 85 case 3: 86 cfg_reg += 0x38UL; 87 break; 88 case 13: 89 cfg_reg += 0x40UL; 90 break; 91 case 14: 92 cfg_reg += 0x48UL; 93 break; 94 case 15: 95 cfg_reg += 0x50UL; 96 break; 97 98 default: 99 return; 100 } 101 102 val = upa_readq(cfg_reg); 103 if (val & (1UL << 14UL)) { 104 /* Extended transfer mode already enabled. */ 105 return; 106 } 107 108 val |= (1UL << 14UL); 109 110 if (bursts & DMA_BURST8) 111 val |= (1UL << 1UL); 112 if (bursts & DMA_BURST16) 113 val |= (1UL << 2UL); 114 if (bursts & DMA_BURST32) 115 val |= (1UL << 3UL); 116 if (bursts & DMA_BURST64) 117 val |= (1UL << 4UL); 118 upa_writeq(val, cfg_reg); 119 } 120 EXPORT_SYMBOL(sbus_set_sbus64); 121 122 /* INO number to IMAP register offset for SYSIO external IRQ's. 123 * This should conform to both Sunfire/Wildfire server and Fusion 124 * desktop designs. 125 */ 126 #define SYSIO_IMAP_SLOT0 0x2c00UL 127 #define SYSIO_IMAP_SLOT1 0x2c08UL 128 #define SYSIO_IMAP_SLOT2 0x2c10UL 129 #define SYSIO_IMAP_SLOT3 0x2c18UL 130 #define SYSIO_IMAP_SCSI 0x3000UL 131 #define SYSIO_IMAP_ETH 0x3008UL 132 #define SYSIO_IMAP_BPP 0x3010UL 133 #define SYSIO_IMAP_AUDIO 0x3018UL 134 #define SYSIO_IMAP_PFAIL 0x3020UL 135 #define SYSIO_IMAP_KMS 0x3028UL 136 #define SYSIO_IMAP_FLPY 0x3030UL 137 #define SYSIO_IMAP_SHW 0x3038UL 138 #define SYSIO_IMAP_KBD 0x3040UL 139 #define SYSIO_IMAP_MS 0x3048UL 140 #define SYSIO_IMAP_SER 0x3050UL 141 #define SYSIO_IMAP_TIM0 0x3060UL 142 #define SYSIO_IMAP_TIM1 0x3068UL 143 #define SYSIO_IMAP_UE 0x3070UL 144 #define SYSIO_IMAP_CE 0x3078UL 145 #define SYSIO_IMAP_SBERR 0x3080UL 146 #define SYSIO_IMAP_PMGMT 0x3088UL 147 #define SYSIO_IMAP_GFX 0x3090UL 148 #define SYSIO_IMAP_EUPA 0x3098UL 149 150 #define bogon ((unsigned long) -1) 151 static unsigned long sysio_irq_offsets[] = { 152 /* SBUS Slot 0 --> 3, level 1 --> 7 */ 153 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, 154 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, 155 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, 156 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, 157 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, 158 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, 159 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, 160 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, 161 162 /* Onboard devices (not relevant/used on SunFire). */ 163 SYSIO_IMAP_SCSI, 164 SYSIO_IMAP_ETH, 165 SYSIO_IMAP_BPP, 166 bogon, 167 SYSIO_IMAP_AUDIO, 168 SYSIO_IMAP_PFAIL, 169 bogon, 170 bogon, 171 SYSIO_IMAP_KMS, 172 SYSIO_IMAP_FLPY, 173 SYSIO_IMAP_SHW, 174 SYSIO_IMAP_KBD, 175 SYSIO_IMAP_MS, 176 SYSIO_IMAP_SER, 177 bogon, 178 bogon, 179 SYSIO_IMAP_TIM0, 180 SYSIO_IMAP_TIM1, 181 bogon, 182 bogon, 183 SYSIO_IMAP_UE, 184 SYSIO_IMAP_CE, 185 SYSIO_IMAP_SBERR, 186 SYSIO_IMAP_PMGMT, 187 }; 188 189 #undef bogon 190 191 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets) 192 193 /* Convert Interrupt Mapping register pointer to associated 194 * Interrupt Clear register pointer, SYSIO specific version. 195 */ 196 #define SYSIO_ICLR_UNUSED0 0x3400UL 197 #define SYSIO_ICLR_SLOT0 0x3408UL 198 #define SYSIO_ICLR_SLOT1 0x3448UL 199 #define SYSIO_ICLR_SLOT2 0x3488UL 200 #define SYSIO_ICLR_SLOT3 0x34c8UL 201 static unsigned long sysio_imap_to_iclr(unsigned long imap) 202 { 203 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0; 204 return imap + diff; 205 } 206 207 static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino) 208 { 209 struct iommu *iommu = op->dev.archdata.iommu; 210 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 211 unsigned long imap, iclr; 212 int sbus_level = 0; 213 214 imap = sysio_irq_offsets[ino]; 215 if (imap == ((unsigned long)-1)) { 216 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n", 217 ino); 218 prom_halt(); 219 } 220 imap += reg_base; 221 222 /* SYSIO inconsistency. For external SLOTS, we have to select 223 * the right ICLR register based upon the lower SBUS irq level 224 * bits. 225 */ 226 if (ino >= 0x20) { 227 iclr = sysio_imap_to_iclr(imap); 228 } else { 229 int sbus_slot = (ino & 0x18)>>3; 230 231 sbus_level = ino & 0x7; 232 233 switch(sbus_slot) { 234 case 0: 235 iclr = reg_base + SYSIO_ICLR_SLOT0; 236 break; 237 case 1: 238 iclr = reg_base + SYSIO_ICLR_SLOT1; 239 break; 240 case 2: 241 iclr = reg_base + SYSIO_ICLR_SLOT2; 242 break; 243 default: 244 case 3: 245 iclr = reg_base + SYSIO_ICLR_SLOT3; 246 break; 247 } 248 249 iclr += ((unsigned long)sbus_level - 1UL) * 8UL; 250 } 251 return build_irq(sbus_level, iclr, imap); 252 } 253 254 /* Error interrupt handling. */ 255 #define SYSIO_UE_AFSR 0x0030UL 256 #define SYSIO_UE_AFAR 0x0038UL 257 #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ 258 #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ 259 #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ 260 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ 261 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ 262 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ 263 #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ 264 #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */ 265 #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ 266 #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ 267 #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ 268 static irqreturn_t sysio_ue_handler(int irq, void *dev_id) 269 { 270 struct platform_device *op = dev_id; 271 struct iommu *iommu = op->dev.archdata.iommu; 272 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 273 unsigned long afsr_reg, afar_reg; 274 unsigned long afsr, afar, error_bits; 275 int reported, portid; 276 277 afsr_reg = reg_base + SYSIO_UE_AFSR; 278 afar_reg = reg_base + SYSIO_UE_AFAR; 279 280 /* Latch error status. */ 281 afsr = upa_readq(afsr_reg); 282 afar = upa_readq(afar_reg); 283 284 /* Clear primary/secondary error status bits. */ 285 error_bits = afsr & 286 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR | 287 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR); 288 upa_writeq(error_bits, afsr_reg); 289 290 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 291 292 /* Log the error. */ 293 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n", 294 portid, 295 (((error_bits & SYSIO_UEAFSR_PPIO) ? 296 "PIO" : 297 ((error_bits & SYSIO_UEAFSR_PDRD) ? 298 "DVMA Read" : 299 ((error_bits & SYSIO_UEAFSR_PDWR) ? 300 "DVMA Write" : "???"))))); 301 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n", 302 portid, 303 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL, 304 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL, 305 (afsr & SYSIO_UEAFSR_MID) >> 37UL); 306 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar); 307 printk("SYSIO[%x]: Secondary UE errors [", portid); 308 reported = 0; 309 if (afsr & SYSIO_UEAFSR_SPIO) { 310 reported++; 311 printk("(PIO)"); 312 } 313 if (afsr & SYSIO_UEAFSR_SDRD) { 314 reported++; 315 printk("(DVMA Read)"); 316 } 317 if (afsr & SYSIO_UEAFSR_SDWR) { 318 reported++; 319 printk("(DVMA Write)"); 320 } 321 if (!reported) 322 printk("(none)"); 323 printk("]\n"); 324 325 return IRQ_HANDLED; 326 } 327 328 #define SYSIO_CE_AFSR 0x0040UL 329 #define SYSIO_CE_AFAR 0x0048UL 330 #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ 331 #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ 332 #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ 333 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */ 334 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ 335 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ 336 #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ 337 #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ 338 #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */ 339 #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ 340 #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ 341 #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ 342 static irqreturn_t sysio_ce_handler(int irq, void *dev_id) 343 { 344 struct platform_device *op = dev_id; 345 struct iommu *iommu = op->dev.archdata.iommu; 346 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 347 unsigned long afsr_reg, afar_reg; 348 unsigned long afsr, afar, error_bits; 349 int reported, portid; 350 351 afsr_reg = reg_base + SYSIO_CE_AFSR; 352 afar_reg = reg_base + SYSIO_CE_AFAR; 353 354 /* Latch error status. */ 355 afsr = upa_readq(afsr_reg); 356 afar = upa_readq(afar_reg); 357 358 /* Clear primary/secondary error status bits. */ 359 error_bits = afsr & 360 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR | 361 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR); 362 upa_writeq(error_bits, afsr_reg); 363 364 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 365 366 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n", 367 portid, 368 (((error_bits & SYSIO_CEAFSR_PPIO) ? 369 "PIO" : 370 ((error_bits & SYSIO_CEAFSR_PDRD) ? 371 "DVMA Read" : 372 ((error_bits & SYSIO_CEAFSR_PDWR) ? 373 "DVMA Write" : "???"))))); 374 375 /* XXX Use syndrome and afar to print out module string just like 376 * XXX UDB CE trap handler does... -DaveM 377 */ 378 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n", 379 portid, 380 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL, 381 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL, 382 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL, 383 (afsr & SYSIO_CEAFSR_MID) >> 37UL); 384 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar); 385 386 printk("SYSIO[%x]: Secondary CE errors [", portid); 387 reported = 0; 388 if (afsr & SYSIO_CEAFSR_SPIO) { 389 reported++; 390 printk("(PIO)"); 391 } 392 if (afsr & SYSIO_CEAFSR_SDRD) { 393 reported++; 394 printk("(DVMA Read)"); 395 } 396 if (afsr & SYSIO_CEAFSR_SDWR) { 397 reported++; 398 printk("(DVMA Write)"); 399 } 400 if (!reported) 401 printk("(none)"); 402 printk("]\n"); 403 404 return IRQ_HANDLED; 405 } 406 407 #define SYSIO_SBUS_AFSR 0x2010UL 408 #define SYSIO_SBUS_AFAR 0x2018UL 409 #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */ 410 #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */ 411 #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */ 412 #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */ 413 #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */ 414 #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */ 415 #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */ 416 #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */ 417 #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */ 418 #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */ 419 #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */ 420 #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */ 421 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id) 422 { 423 struct platform_device *op = dev_id; 424 struct iommu *iommu = op->dev.archdata.iommu; 425 unsigned long afsr_reg, afar_reg, reg_base; 426 unsigned long afsr, afar, error_bits; 427 int reported, portid; 428 429 reg_base = iommu->write_complete_reg - 0x2000UL; 430 afsr_reg = reg_base + SYSIO_SBUS_AFSR; 431 afar_reg = reg_base + SYSIO_SBUS_AFAR; 432 433 afsr = upa_readq(afsr_reg); 434 afar = upa_readq(afar_reg); 435 436 /* Clear primary/secondary error status bits. */ 437 error_bits = afsr & 438 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR | 439 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR); 440 upa_writeq(error_bits, afsr_reg); 441 442 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 443 444 /* Log the error. */ 445 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n", 446 portid, 447 (((error_bits & SYSIO_SBAFSR_PLE) ? 448 "Late PIO Error" : 449 ((error_bits & SYSIO_SBAFSR_PTO) ? 450 "Time Out" : 451 ((error_bits & SYSIO_SBAFSR_PBERR) ? 452 "Error Ack" : "???")))), 453 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0); 454 printk("SYSIO[%x]: size[%lx] MID[%lx]\n", 455 portid, 456 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL, 457 (afsr & SYSIO_SBAFSR_MID) >> 37UL); 458 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar); 459 printk("SYSIO[%x]: Secondary SBUS errors [", portid); 460 reported = 0; 461 if (afsr & SYSIO_SBAFSR_SLE) { 462 reported++; 463 printk("(Late PIO Error)"); 464 } 465 if (afsr & SYSIO_SBAFSR_STO) { 466 reported++; 467 printk("(Time Out)"); 468 } 469 if (afsr & SYSIO_SBAFSR_SBERR) { 470 reported++; 471 printk("(Error Ack)"); 472 } 473 if (!reported) 474 printk("(none)"); 475 printk("]\n"); 476 477 /* XXX check iommu/strbuf for further error status XXX */ 478 479 return IRQ_HANDLED; 480 } 481 482 #define ECC_CONTROL 0x0020UL 483 #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */ 484 #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */ 485 #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */ 486 487 #define SYSIO_UE_INO 0x34 488 #define SYSIO_CE_INO 0x35 489 #define SYSIO_SBUSERR_INO 0x36 490 491 static void __init sysio_register_error_handlers(struct platform_device *op) 492 { 493 struct iommu *iommu = op->dev.archdata.iommu; 494 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 495 unsigned int irq; 496 u64 control; 497 int portid; 498 499 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 500 501 irq = sbus_build_irq(op, SYSIO_UE_INO); 502 if (request_irq(irq, sysio_ue_handler, 0, 503 "SYSIO_UE", op) < 0) { 504 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n", 505 portid); 506 prom_halt(); 507 } 508 509 irq = sbus_build_irq(op, SYSIO_CE_INO); 510 if (request_irq(irq, sysio_ce_handler, 0, 511 "SYSIO_CE", op) < 0) { 512 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n", 513 portid); 514 prom_halt(); 515 } 516 517 irq = sbus_build_irq(op, SYSIO_SBUSERR_INO); 518 if (request_irq(irq, sysio_sbus_error_handler, 0, 519 "SYSIO_SBERR", op) < 0) { 520 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n", 521 portid); 522 prom_halt(); 523 } 524 525 /* Now turn the error interrupts on and also enable ECC checking. */ 526 upa_writeq((SYSIO_ECNTRL_ECCEN | 527 SYSIO_ECNTRL_UEEN | 528 SYSIO_ECNTRL_CEEN), 529 reg_base + ECC_CONTROL); 530 531 control = upa_readq(iommu->write_complete_reg); 532 control |= 0x100UL; /* SBUS Error Interrupt Enable */ 533 upa_writeq(control, iommu->write_complete_reg); 534 } 535 536 /* Boot time initialization. */ 537 static void __init sbus_iommu_init(struct platform_device *op) 538 { 539 const struct linux_prom64_registers *pr; 540 struct device_node *dp = op->dev.of_node; 541 struct iommu *iommu; 542 struct strbuf *strbuf; 543 unsigned long regs, reg_base; 544 int i, portid; 545 u64 control; 546 547 pr = of_get_property(dp, "reg", NULL); 548 if (!pr) { 549 prom_printf("sbus_iommu_init: Cannot map SYSIO " 550 "control registers.\n"); 551 prom_halt(); 552 } 553 regs = pr->phys_addr; 554 555 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC); 556 if (!iommu) 557 goto fatal_memory_error; 558 strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC); 559 if (!strbuf) 560 goto fatal_memory_error; 561 562 op->dev.archdata.iommu = iommu; 563 op->dev.archdata.stc = strbuf; 564 op->dev.archdata.numa_node = -1; 565 566 reg_base = regs + SYSIO_IOMMUREG_BASE; 567 iommu->iommu_control = reg_base + IOMMU_CONTROL; 568 iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE; 569 iommu->iommu_flush = reg_base + IOMMU_FLUSH; 570 iommu->iommu_tags = iommu->iommu_control + 571 (IOMMU_TAGDIAG - IOMMU_CONTROL); 572 573 reg_base = regs + SYSIO_STRBUFREG_BASE; 574 strbuf->strbuf_control = reg_base + STRBUF_CONTROL; 575 strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH; 576 strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC; 577 578 strbuf->strbuf_enabled = 1; 579 580 strbuf->strbuf_flushflag = (volatile unsigned long *) 581 ((((unsigned long)&strbuf->__flushflag_buf[0]) 582 + 63UL) 583 & ~63UL); 584 strbuf->strbuf_flushflag_pa = (unsigned long) 585 __pa(strbuf->strbuf_flushflag); 586 587 /* The SYSIO SBUS control register is used for dummy reads 588 * in order to ensure write completion. 589 */ 590 iommu->write_complete_reg = regs + 0x2000UL; 591 592 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 593 printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n", 594 portid, regs); 595 596 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */ 597 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1)) 598 goto fatal_memory_error; 599 600 control = upa_readq(iommu->iommu_control); 601 control = ((7UL << 16UL) | 602 (0UL << 2UL) | 603 (1UL << 1UL) | 604 (1UL << 0UL)); 605 upa_writeq(control, iommu->iommu_control); 606 607 /* Clean out any cruft in the IOMMU using 608 * diagnostic accesses. 609 */ 610 for (i = 0; i < 16; i++) { 611 unsigned long dram, tag; 612 613 dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL); 614 tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL); 615 616 dram += (unsigned long)i * 8UL; 617 tag += (unsigned long)i * 8UL; 618 upa_writeq(0, dram); 619 upa_writeq(0, tag); 620 } 621 upa_readq(iommu->write_complete_reg); 622 623 /* Give the TSB to SYSIO. */ 624 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 625 626 /* Setup streaming buffer, DE=1 SB_EN=1 */ 627 control = (1UL << 1UL) | (1UL << 0UL); 628 upa_writeq(control, strbuf->strbuf_control); 629 630 /* Clear out the tags using diagnostics. */ 631 for (i = 0; i < 16; i++) { 632 unsigned long ptag, ltag; 633 634 ptag = strbuf->strbuf_control + 635 (STRBUF_PTAGDIAG - STRBUF_CONTROL); 636 ltag = strbuf->strbuf_control + 637 (STRBUF_LTAGDIAG - STRBUF_CONTROL); 638 ptag += (unsigned long)i * 8UL; 639 ltag += (unsigned long)i * 8UL; 640 641 upa_writeq(0UL, ptag); 642 upa_writeq(0UL, ltag); 643 } 644 645 /* Enable DVMA arbitration for all devices/slots. */ 646 control = upa_readq(iommu->write_complete_reg); 647 control |= 0x3fUL; 648 upa_writeq(control, iommu->write_complete_reg); 649 650 /* Now some Xfire specific grot... */ 651 if (this_is_starfire) 652 starfire_hookup(portid); 653 654 sysio_register_error_handlers(op); 655 return; 656 657 fatal_memory_error: 658 prom_printf("sbus_iommu_init: Fatal memory allocation error.\n"); 659 } 660 661 static int __init sbus_init(void) 662 { 663 struct device_node *dp; 664 665 for_each_node_by_name(dp, "sbus") { 666 struct platform_device *op = of_find_device_by_node(dp); 667 668 sbus_iommu_init(op); 669 of_propagate_archdata(op); 670 } 671 672 return 0; 673 } 674 675 subsys_initcall(sbus_init); 676