1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sbus.c: UltraSparc SBUS controller support. 4 * 5 * Copyright (C) 1999 David S. Miller (davem@redhat.com) 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/types.h> 10 #include <linux/mm.h> 11 #include <linux/spinlock.h> 12 #include <linux/slab.h> 13 #include <linux/export.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/numa.h> 19 20 #include <asm/page.h> 21 #include <asm/io.h> 22 #include <asm/upa.h> 23 #include <asm/cache.h> 24 #include <asm/dma.h> 25 #include <asm/irq.h> 26 #include <asm/prom.h> 27 #include <asm/oplib.h> 28 #include <asm/starfire.h> 29 30 #include "iommu_common.h" 31 32 #define MAP_BASE ((u32)0xc0000000) 33 34 /* Offsets from iommu_regs */ 35 #define SYSIO_IOMMUREG_BASE 0x2400UL 36 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */ 37 #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */ 38 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */ 39 #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */ 40 #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */ 41 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */ 42 #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */ 43 #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */ 44 45 #define IOMMU_DRAM_VALID (1UL << 30UL) 46 47 /* Offsets from strbuf_regs */ 48 #define SYSIO_STRBUFREG_BASE 0x2800UL 49 #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */ 50 #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */ 51 #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */ 52 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */ 53 #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */ 54 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */ 55 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */ 56 57 #define STRBUF_TAG_VALID 0x02UL 58 59 /* Enable 64-bit DVMA mode for the given device. */ 60 void sbus_set_sbus64(struct device *dev, int bursts) 61 { 62 struct iommu *iommu = dev->archdata.iommu; 63 struct platform_device *op = to_platform_device(dev); 64 const struct linux_prom_registers *regs; 65 unsigned long cfg_reg; 66 int slot; 67 u64 val; 68 69 regs = of_get_property(op->dev.of_node, "reg", NULL); 70 if (!regs) { 71 printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %pOF\n", 72 op->dev.of_node); 73 return; 74 } 75 slot = regs->which_io; 76 77 cfg_reg = iommu->write_complete_reg; 78 switch (slot) { 79 case 0: 80 cfg_reg += 0x20UL; 81 break; 82 case 1: 83 cfg_reg += 0x28UL; 84 break; 85 case 2: 86 cfg_reg += 0x30UL; 87 break; 88 case 3: 89 cfg_reg += 0x38UL; 90 break; 91 case 13: 92 cfg_reg += 0x40UL; 93 break; 94 case 14: 95 cfg_reg += 0x48UL; 96 break; 97 case 15: 98 cfg_reg += 0x50UL; 99 break; 100 101 default: 102 return; 103 } 104 105 val = upa_readq(cfg_reg); 106 if (val & (1UL << 14UL)) { 107 /* Extended transfer mode already enabled. */ 108 return; 109 } 110 111 val |= (1UL << 14UL); 112 113 if (bursts & DMA_BURST8) 114 val |= (1UL << 1UL); 115 if (bursts & DMA_BURST16) 116 val |= (1UL << 2UL); 117 if (bursts & DMA_BURST32) 118 val |= (1UL << 3UL); 119 if (bursts & DMA_BURST64) 120 val |= (1UL << 4UL); 121 upa_writeq(val, cfg_reg); 122 } 123 EXPORT_SYMBOL(sbus_set_sbus64); 124 125 /* INO number to IMAP register offset for SYSIO external IRQ's. 126 * This should conform to both Sunfire/Wildfire server and Fusion 127 * desktop designs. 128 */ 129 #define SYSIO_IMAP_SLOT0 0x2c00UL 130 #define SYSIO_IMAP_SLOT1 0x2c08UL 131 #define SYSIO_IMAP_SLOT2 0x2c10UL 132 #define SYSIO_IMAP_SLOT3 0x2c18UL 133 #define SYSIO_IMAP_SCSI 0x3000UL 134 #define SYSIO_IMAP_ETH 0x3008UL 135 #define SYSIO_IMAP_BPP 0x3010UL 136 #define SYSIO_IMAP_AUDIO 0x3018UL 137 #define SYSIO_IMAP_PFAIL 0x3020UL 138 #define SYSIO_IMAP_KMS 0x3028UL 139 #define SYSIO_IMAP_FLPY 0x3030UL 140 #define SYSIO_IMAP_SHW 0x3038UL 141 #define SYSIO_IMAP_KBD 0x3040UL 142 #define SYSIO_IMAP_MS 0x3048UL 143 #define SYSIO_IMAP_SER 0x3050UL 144 #define SYSIO_IMAP_TIM0 0x3060UL 145 #define SYSIO_IMAP_TIM1 0x3068UL 146 #define SYSIO_IMAP_UE 0x3070UL 147 #define SYSIO_IMAP_CE 0x3078UL 148 #define SYSIO_IMAP_SBERR 0x3080UL 149 #define SYSIO_IMAP_PMGMT 0x3088UL 150 #define SYSIO_IMAP_GFX 0x3090UL 151 #define SYSIO_IMAP_EUPA 0x3098UL 152 153 #define bogon ((unsigned long) -1) 154 static unsigned long sysio_irq_offsets[] = { 155 /* SBUS Slot 0 --> 3, level 1 --> 7 */ 156 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, 157 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, 158 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, 159 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, 160 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, 161 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, 162 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, 163 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, 164 165 /* Onboard devices (not relevant/used on SunFire). */ 166 SYSIO_IMAP_SCSI, 167 SYSIO_IMAP_ETH, 168 SYSIO_IMAP_BPP, 169 bogon, 170 SYSIO_IMAP_AUDIO, 171 SYSIO_IMAP_PFAIL, 172 bogon, 173 bogon, 174 SYSIO_IMAP_KMS, 175 SYSIO_IMAP_FLPY, 176 SYSIO_IMAP_SHW, 177 SYSIO_IMAP_KBD, 178 SYSIO_IMAP_MS, 179 SYSIO_IMAP_SER, 180 bogon, 181 bogon, 182 SYSIO_IMAP_TIM0, 183 SYSIO_IMAP_TIM1, 184 bogon, 185 bogon, 186 SYSIO_IMAP_UE, 187 SYSIO_IMAP_CE, 188 SYSIO_IMAP_SBERR, 189 SYSIO_IMAP_PMGMT, 190 }; 191 192 #undef bogon 193 194 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets) 195 196 /* Convert Interrupt Mapping register pointer to associated 197 * Interrupt Clear register pointer, SYSIO specific version. 198 */ 199 #define SYSIO_ICLR_UNUSED0 0x3400UL 200 #define SYSIO_ICLR_SLOT0 0x3408UL 201 #define SYSIO_ICLR_SLOT1 0x3448UL 202 #define SYSIO_ICLR_SLOT2 0x3488UL 203 #define SYSIO_ICLR_SLOT3 0x34c8UL 204 static unsigned long sysio_imap_to_iclr(unsigned long imap) 205 { 206 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0; 207 return imap + diff; 208 } 209 210 static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino) 211 { 212 struct iommu *iommu = op->dev.archdata.iommu; 213 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 214 unsigned long imap, iclr; 215 int sbus_level = 0; 216 217 imap = sysio_irq_offsets[ino]; 218 if (imap == ((unsigned long)-1)) { 219 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n", 220 ino); 221 prom_halt(); 222 } 223 imap += reg_base; 224 225 /* SYSIO inconsistency. For external SLOTS, we have to select 226 * the right ICLR register based upon the lower SBUS irq level 227 * bits. 228 */ 229 if (ino >= 0x20) { 230 iclr = sysio_imap_to_iclr(imap); 231 } else { 232 int sbus_slot = (ino & 0x18)>>3; 233 234 sbus_level = ino & 0x7; 235 236 switch(sbus_slot) { 237 case 0: 238 iclr = reg_base + SYSIO_ICLR_SLOT0; 239 break; 240 case 1: 241 iclr = reg_base + SYSIO_ICLR_SLOT1; 242 break; 243 case 2: 244 iclr = reg_base + SYSIO_ICLR_SLOT2; 245 break; 246 default: 247 case 3: 248 iclr = reg_base + SYSIO_ICLR_SLOT3; 249 break; 250 } 251 252 iclr += ((unsigned long)sbus_level - 1UL) * 8UL; 253 } 254 return build_irq(sbus_level, iclr, imap); 255 } 256 257 /* Error interrupt handling. */ 258 #define SYSIO_UE_AFSR 0x0030UL 259 #define SYSIO_UE_AFAR 0x0038UL 260 #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ 261 #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ 262 #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ 263 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ 264 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ 265 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ 266 #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ 267 #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */ 268 #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ 269 #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ 270 #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ 271 static irqreturn_t sysio_ue_handler(int irq, void *dev_id) 272 { 273 struct platform_device *op = dev_id; 274 struct iommu *iommu = op->dev.archdata.iommu; 275 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 276 unsigned long afsr_reg, afar_reg; 277 unsigned long afsr, afar, error_bits; 278 int reported, portid; 279 280 afsr_reg = reg_base + SYSIO_UE_AFSR; 281 afar_reg = reg_base + SYSIO_UE_AFAR; 282 283 /* Latch error status. */ 284 afsr = upa_readq(afsr_reg); 285 afar = upa_readq(afar_reg); 286 287 /* Clear primary/secondary error status bits. */ 288 error_bits = afsr & 289 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR | 290 SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR); 291 upa_writeq(error_bits, afsr_reg); 292 293 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 294 295 /* Log the error. */ 296 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n", 297 portid, 298 (((error_bits & SYSIO_UEAFSR_PPIO) ? 299 "PIO" : 300 ((error_bits & SYSIO_UEAFSR_PDRD) ? 301 "DVMA Read" : 302 ((error_bits & SYSIO_UEAFSR_PDWR) ? 303 "DVMA Write" : "???"))))); 304 printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n", 305 portid, 306 (afsr & SYSIO_UEAFSR_DOFF) >> 45UL, 307 (afsr & SYSIO_UEAFSR_SIZE) >> 42UL, 308 (afsr & SYSIO_UEAFSR_MID) >> 37UL); 309 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar); 310 printk("SYSIO[%x]: Secondary UE errors [", portid); 311 reported = 0; 312 if (afsr & SYSIO_UEAFSR_SPIO) { 313 reported++; 314 printk("(PIO)"); 315 } 316 if (afsr & SYSIO_UEAFSR_SDRD) { 317 reported++; 318 printk("(DVMA Read)"); 319 } 320 if (afsr & SYSIO_UEAFSR_SDWR) { 321 reported++; 322 printk("(DVMA Write)"); 323 } 324 if (!reported) 325 printk("(none)"); 326 printk("]\n"); 327 328 return IRQ_HANDLED; 329 } 330 331 #define SYSIO_CE_AFSR 0x0040UL 332 #define SYSIO_CE_AFAR 0x0048UL 333 #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ 334 #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ 335 #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ 336 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */ 337 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ 338 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ 339 #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ 340 #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ 341 #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */ 342 #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ 343 #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ 344 #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ 345 static irqreturn_t sysio_ce_handler(int irq, void *dev_id) 346 { 347 struct platform_device *op = dev_id; 348 struct iommu *iommu = op->dev.archdata.iommu; 349 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 350 unsigned long afsr_reg, afar_reg; 351 unsigned long afsr, afar, error_bits; 352 int reported, portid; 353 354 afsr_reg = reg_base + SYSIO_CE_AFSR; 355 afar_reg = reg_base + SYSIO_CE_AFAR; 356 357 /* Latch error status. */ 358 afsr = upa_readq(afsr_reg); 359 afar = upa_readq(afar_reg); 360 361 /* Clear primary/secondary error status bits. */ 362 error_bits = afsr & 363 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR | 364 SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR); 365 upa_writeq(error_bits, afsr_reg); 366 367 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 368 369 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n", 370 portid, 371 (((error_bits & SYSIO_CEAFSR_PPIO) ? 372 "PIO" : 373 ((error_bits & SYSIO_CEAFSR_PDRD) ? 374 "DVMA Read" : 375 ((error_bits & SYSIO_CEAFSR_PDWR) ? 376 "DVMA Write" : "???"))))); 377 378 /* XXX Use syndrome and afar to print out module string just like 379 * XXX UDB CE trap handler does... -DaveM 380 */ 381 printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n", 382 portid, 383 (afsr & SYSIO_CEAFSR_DOFF) >> 45UL, 384 (afsr & SYSIO_CEAFSR_ESYND) >> 48UL, 385 (afsr & SYSIO_CEAFSR_SIZE) >> 42UL, 386 (afsr & SYSIO_CEAFSR_MID) >> 37UL); 387 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar); 388 389 printk("SYSIO[%x]: Secondary CE errors [", portid); 390 reported = 0; 391 if (afsr & SYSIO_CEAFSR_SPIO) { 392 reported++; 393 printk("(PIO)"); 394 } 395 if (afsr & SYSIO_CEAFSR_SDRD) { 396 reported++; 397 printk("(DVMA Read)"); 398 } 399 if (afsr & SYSIO_CEAFSR_SDWR) { 400 reported++; 401 printk("(DVMA Write)"); 402 } 403 if (!reported) 404 printk("(none)"); 405 printk("]\n"); 406 407 return IRQ_HANDLED; 408 } 409 410 #define SYSIO_SBUS_AFSR 0x2010UL 411 #define SYSIO_SBUS_AFAR 0x2018UL 412 #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */ 413 #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */ 414 #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */ 415 #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */ 416 #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */ 417 #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */ 418 #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */ 419 #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */ 420 #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */ 421 #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */ 422 #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */ 423 #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */ 424 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id) 425 { 426 struct platform_device *op = dev_id; 427 struct iommu *iommu = op->dev.archdata.iommu; 428 unsigned long afsr_reg, afar_reg, reg_base; 429 unsigned long afsr, afar, error_bits; 430 int reported, portid; 431 432 reg_base = iommu->write_complete_reg - 0x2000UL; 433 afsr_reg = reg_base + SYSIO_SBUS_AFSR; 434 afar_reg = reg_base + SYSIO_SBUS_AFAR; 435 436 afsr = upa_readq(afsr_reg); 437 afar = upa_readq(afar_reg); 438 439 /* Clear primary/secondary error status bits. */ 440 error_bits = afsr & 441 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR | 442 SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR); 443 upa_writeq(error_bits, afsr_reg); 444 445 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 446 447 /* Log the error. */ 448 printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n", 449 portid, 450 (((error_bits & SYSIO_SBAFSR_PLE) ? 451 "Late PIO Error" : 452 ((error_bits & SYSIO_SBAFSR_PTO) ? 453 "Time Out" : 454 ((error_bits & SYSIO_SBAFSR_PBERR) ? 455 "Error Ack" : "???")))), 456 (afsr & SYSIO_SBAFSR_RD) ? 1 : 0); 457 printk("SYSIO[%x]: size[%lx] MID[%lx]\n", 458 portid, 459 (afsr & SYSIO_SBAFSR_SIZE) >> 42UL, 460 (afsr & SYSIO_SBAFSR_MID) >> 37UL); 461 printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar); 462 printk("SYSIO[%x]: Secondary SBUS errors [", portid); 463 reported = 0; 464 if (afsr & SYSIO_SBAFSR_SLE) { 465 reported++; 466 printk("(Late PIO Error)"); 467 } 468 if (afsr & SYSIO_SBAFSR_STO) { 469 reported++; 470 printk("(Time Out)"); 471 } 472 if (afsr & SYSIO_SBAFSR_SBERR) { 473 reported++; 474 printk("(Error Ack)"); 475 } 476 if (!reported) 477 printk("(none)"); 478 printk("]\n"); 479 480 /* XXX check iommu/strbuf for further error status XXX */ 481 482 return IRQ_HANDLED; 483 } 484 485 #define ECC_CONTROL 0x0020UL 486 #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */ 487 #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */ 488 #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */ 489 490 #define SYSIO_UE_INO 0x34 491 #define SYSIO_CE_INO 0x35 492 #define SYSIO_SBUSERR_INO 0x36 493 494 static void __init sysio_register_error_handlers(struct platform_device *op) 495 { 496 struct iommu *iommu = op->dev.archdata.iommu; 497 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; 498 unsigned int irq; 499 u64 control; 500 int portid; 501 502 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 503 504 irq = sbus_build_irq(op, SYSIO_UE_INO); 505 if (request_irq(irq, sysio_ue_handler, 0, 506 "SYSIO_UE", op) < 0) { 507 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n", 508 portid); 509 prom_halt(); 510 } 511 512 irq = sbus_build_irq(op, SYSIO_CE_INO); 513 if (request_irq(irq, sysio_ce_handler, 0, 514 "SYSIO_CE", op) < 0) { 515 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n", 516 portid); 517 prom_halt(); 518 } 519 520 irq = sbus_build_irq(op, SYSIO_SBUSERR_INO); 521 if (request_irq(irq, sysio_sbus_error_handler, 0, 522 "SYSIO_SBERR", op) < 0) { 523 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n", 524 portid); 525 prom_halt(); 526 } 527 528 /* Now turn the error interrupts on and also enable ECC checking. */ 529 upa_writeq((SYSIO_ECNTRL_ECCEN | 530 SYSIO_ECNTRL_UEEN | 531 SYSIO_ECNTRL_CEEN), 532 reg_base + ECC_CONTROL); 533 534 control = upa_readq(iommu->write_complete_reg); 535 control |= 0x100UL; /* SBUS Error Interrupt Enable */ 536 upa_writeq(control, iommu->write_complete_reg); 537 } 538 539 /* Boot time initialization. */ 540 static void __init sbus_iommu_init(struct platform_device *op) 541 { 542 const struct linux_prom64_registers *pr; 543 struct device_node *dp = op->dev.of_node; 544 struct iommu *iommu; 545 struct strbuf *strbuf; 546 unsigned long regs, reg_base; 547 int i, portid; 548 u64 control; 549 550 pr = of_get_property(dp, "reg", NULL); 551 if (!pr) { 552 prom_printf("sbus_iommu_init: Cannot map SYSIO " 553 "control registers.\n"); 554 prom_halt(); 555 } 556 regs = pr->phys_addr; 557 558 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC); 559 strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC); 560 if (!iommu || !strbuf) 561 goto fatal_memory_error; 562 563 op->dev.archdata.iommu = iommu; 564 op->dev.archdata.stc = strbuf; 565 op->dev.archdata.numa_node = NUMA_NO_NODE; 566 567 reg_base = regs + SYSIO_IOMMUREG_BASE; 568 iommu->iommu_control = reg_base + IOMMU_CONTROL; 569 iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE; 570 iommu->iommu_flush = reg_base + IOMMU_FLUSH; 571 iommu->iommu_tags = iommu->iommu_control + 572 (IOMMU_TAGDIAG - IOMMU_CONTROL); 573 574 reg_base = regs + SYSIO_STRBUFREG_BASE; 575 strbuf->strbuf_control = reg_base + STRBUF_CONTROL; 576 strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH; 577 strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC; 578 579 strbuf->strbuf_enabled = 1; 580 581 strbuf->strbuf_flushflag = (volatile unsigned long *) 582 ((((unsigned long)&strbuf->__flushflag_buf[0]) 583 + 63UL) 584 & ~63UL); 585 strbuf->strbuf_flushflag_pa = (unsigned long) 586 __pa(strbuf->strbuf_flushflag); 587 588 /* The SYSIO SBUS control register is used for dummy reads 589 * in order to ensure write completion. 590 */ 591 iommu->write_complete_reg = regs + 0x2000UL; 592 593 portid = of_getintprop_default(op->dev.of_node, "portid", -1); 594 printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n", 595 portid, regs); 596 597 /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */ 598 if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1)) 599 goto fatal_memory_error; 600 601 control = upa_readq(iommu->iommu_control); 602 control = ((7UL << 16UL) | 603 (0UL << 2UL) | 604 (1UL << 1UL) | 605 (1UL << 0UL)); 606 upa_writeq(control, iommu->iommu_control); 607 608 /* Clean out any cruft in the IOMMU using 609 * diagnostic accesses. 610 */ 611 for (i = 0; i < 16; i++) { 612 unsigned long dram, tag; 613 614 dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL); 615 tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL); 616 617 dram += (unsigned long)i * 8UL; 618 tag += (unsigned long)i * 8UL; 619 upa_writeq(0, dram); 620 upa_writeq(0, tag); 621 } 622 upa_readq(iommu->write_complete_reg); 623 624 /* Give the TSB to SYSIO. */ 625 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 626 627 /* Setup streaming buffer, DE=1 SB_EN=1 */ 628 control = (1UL << 1UL) | (1UL << 0UL); 629 upa_writeq(control, strbuf->strbuf_control); 630 631 /* Clear out the tags using diagnostics. */ 632 for (i = 0; i < 16; i++) { 633 unsigned long ptag, ltag; 634 635 ptag = strbuf->strbuf_control + 636 (STRBUF_PTAGDIAG - STRBUF_CONTROL); 637 ltag = strbuf->strbuf_control + 638 (STRBUF_LTAGDIAG - STRBUF_CONTROL); 639 ptag += (unsigned long)i * 8UL; 640 ltag += (unsigned long)i * 8UL; 641 642 upa_writeq(0UL, ptag); 643 upa_writeq(0UL, ltag); 644 } 645 646 /* Enable DVMA arbitration for all devices/slots. */ 647 control = upa_readq(iommu->write_complete_reg); 648 control |= 0x3fUL; 649 upa_writeq(control, iommu->write_complete_reg); 650 651 /* Now some Xfire specific grot... */ 652 if (this_is_starfire) 653 starfire_hookup(portid); 654 655 sysio_register_error_handlers(op); 656 return; 657 658 fatal_memory_error: 659 kfree(iommu); 660 kfree(strbuf); 661 prom_printf("sbus_iommu_init: Fatal memory allocation error.\n"); 662 } 663 664 static int __init sbus_init(void) 665 { 666 struct device_node *dp; 667 668 for_each_node_by_name(dp, "sbus") { 669 struct platform_device *op = of_find_device_by_node(dp); 670 671 sbus_iommu_init(op); 672 of_propagate_archdata(op); 673 } 674 675 return 0; 676 } 677 678 subsys_initcall(sbus_init); 679