1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * rtrap.S: Preparing for return from trap on Sparc V9. 4 * 5 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) 7 */ 8 9 10#include <asm/asi.h> 11#include <asm/pstate.h> 12#include <asm/ptrace.h> 13#include <asm/spitfire.h> 14#include <asm/head.h> 15#include <asm/visasm.h> 16#include <asm/processor.h> 17 18#ifdef CONFIG_CONTEXT_TRACKING 19# define SCHEDULE_USER schedule_user 20#else 21# define SCHEDULE_USER schedule 22#endif 23 24 .text 25 .align 32 26__handle_preemption: 27 call SCHEDULE_USER 28661: wrpr %g0, RTRAP_PSTATE, %pstate 29 /* If userspace is using ADI, it could potentially pass 30 * a pointer with version tag embedded in it. To maintain 31 * the ADI security, we must re-enable PSTATE.mcde before 32 * we continue execution in the kernel for another thread. 33 */ 34 .section .sun_m7_1insn_patch, "ax" 35 .word 661b 36 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate 37 .previous 38 ba,pt %xcc, __handle_preemption_continue 39 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate 40 41__handle_user_windows: 42 call fault_in_user_windows 43661: wrpr %g0, RTRAP_PSTATE, %pstate 44 /* If userspace is using ADI, it could potentially pass 45 * a pointer with version tag embedded in it. To maintain 46 * the ADI security, we must re-enable PSTATE.mcde before 47 * we continue execution in the kernel for another thread. 48 */ 49 .section .sun_m7_1insn_patch, "ax" 50 .word 661b 51 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate 52 .previous 53 ba,pt %xcc, __handle_preemption_continue 54 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate 55 56__handle_userfpu: 57 rd %fprs, %l5 58 andcc %l5, FPRS_FEF, %g0 59 sethi %hi(TSTATE_PEF), %o0 60 be,a,pn %icc, __handle_userfpu_continue 61 andn %l1, %o0, %l1 62 ba,a,pt %xcc, __handle_userfpu_continue 63 64__handle_signal: 65 mov %l5, %o1 66 add %sp, PTREGS_OFF, %o0 67 mov %l0, %o2 68 call do_notify_resume 69661: wrpr %g0, RTRAP_PSTATE, %pstate 70 /* If userspace is using ADI, it could potentially pass 71 * a pointer with version tag embedded in it. To maintain 72 * the ADI security, we must re-enable PSTATE.mcde before 73 * we continue execution in the kernel for another thread. 74 */ 75 .section .sun_m7_1insn_patch, "ax" 76 .word 661b 77 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate 78 .previous 79 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate 80 81 /* Signal delivery can modify pt_regs tstate, so we must 82 * reload it. 83 */ 84 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 85 sethi %hi(0xf << 20), %l4 86 and %l1, %l4, %l4 87 ba,pt %xcc, __handle_preemption_continue 88 andn %l1, %l4, %l1 89 90 /* When returning from a NMI (%pil==15) interrupt we want to 91 * avoid running softirqs, doing IRQ tracing, preempting, etc. 92 */ 93 .globl rtrap_nmi 94rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 95 sethi %hi(0xf << 20), %l4 96 and %l1, %l4, %l4 97 andn %l1, %l4, %l1 98 srl %l4, 20, %l4 99 ba,pt %xcc, rtrap_no_irq_enable 100 nop 101 /* Do not actually set the %pil here. We will do that 102 * below after we clear PSTATE_IE in the %pstate register. 103 * If we re-enable interrupts here, we can recurse down 104 * the hardirq stack potentially endlessly, causing a 105 * stack overflow. 106 */ 107 108 .align 64 109 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall 110rtrap_irq: 111rtrap: 112 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */ 113 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 114rtrap_xcall: 115 sethi %hi(0xf << 20), %l4 116 and %l1, %l4, %l4 117 andn %l1, %l4, %l1 118 srl %l4, 20, %l4 119#ifdef CONFIG_TRACE_IRQFLAGS 120 brnz,pn %l4, rtrap_no_irq_enable 121 nop 122 call trace_hardirqs_on 123 nop 124 /* Do not actually set the %pil here. We will do that 125 * below after we clear PSTATE_IE in the %pstate register. 126 * If we re-enable interrupts here, we can recurse down 127 * the hardirq stack potentially endlessly, causing a 128 * stack overflow. 129 * 130 * It is tempting to put this test and trace_hardirqs_on 131 * call at the 'rt_continue' label, but that will not work 132 * as that path hits unconditionally and we do not want to 133 * execute this in NMI return paths, for example. 134 */ 135#endif 136rtrap_no_irq_enable: 137 andcc %l1, TSTATE_PRIV, %l3 138 bne,pn %icc, to_kernel 139 nop 140 141 /* We must hold IRQs off and atomically test schedule+signal 142 * state, then hold them off all the way back to userspace. 143 * If we are returning to kernel, none of this matters. Note 144 * that we are disabling interrupts via PSTATE_IE, not using 145 * %pil. 146 * 147 * If we do not do this, there is a window where we would do 148 * the tests, later the signal/resched event arrives but we do 149 * not process it since we are still in kernel mode. It would 150 * take until the next local IRQ before the signal/resched 151 * event would be handled. 152 * 153 * This also means that if we have to deal with user 154 * windows, we have to redo all of these sched+signal checks 155 * with IRQs disabled. 156 */ 157to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate 158 wrpr 0, %pil 159__handle_preemption_continue: 160 ldx [%g6 + TI_FLAGS], %l0 161 sethi %hi(_TIF_USER_WORK_MASK), %o0 162 or %o0, %lo(_TIF_USER_WORK_MASK), %o0 163 andcc %l0, %o0, %g0 164 sethi %hi(TSTATE_PEF), %o0 165 be,pt %xcc, user_nowork 166 andcc %l1, %o0, %g0 167 andcc %l0, _TIF_NEED_RESCHED, %g0 168 bne,pn %xcc, __handle_preemption 169 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0 170 bne,pn %xcc, __handle_signal 171 ldub [%g6 + TI_WSAVED], %o2 172 brnz,pn %o2, __handle_user_windows 173 nop 174 sethi %hi(TSTATE_PEF), %o0 175 andcc %l1, %o0, %g0 176 177 /* This fpdepth clear is necessary for non-syscall rtraps only */ 178user_nowork: 179 bne,pn %xcc, __handle_userfpu 180 stb %g0, [%g6 + TI_FPDEPTH] 181__handle_userfpu_continue: 182 183rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 184 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2 185 186 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3 187 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4 188 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5 189 brz,pt %l3, 1f 190 mov %g6, %l2 191 192 /* Must do this before thread reg is clobbered below. */ 193 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2) 1941: 195 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6 196 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7 197 198 /* Normal globals are restored, go to trap globals. */ 199661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate 200 nop 201 .section .sun4v_2insn_patch, "ax" 202 .word 661b 203 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate 204 SET_GL(1) 205 .previous 206 207 mov %l2, %g6 208 209 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0 210 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1 211 212 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2 213 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3 214 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4 215 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5 216 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6 217 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7 218 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2 219 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2 220 221 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3 222 wr %o3, %g0, %y 223 wrpr %l4, 0x0, %pil 224 wrpr %g0, 0x1, %tl 225 andn %l1, TSTATE_SYSCALL, %l1 226 wrpr %l1, %g0, %tstate 227 wrpr %l2, %g0, %tpc 228 wrpr %o2, %g0, %tnpc 229 230 brnz,pn %l3, kern_rtt 231 mov PRIMARY_CONTEXT, %l7 232 233661: ldxa [%l7 + %l7] ASI_DMMU, %l0 234 .section .sun4v_1insn_patch, "ax" 235 .word 661b 236 ldxa [%l7 + %l7] ASI_MMU, %l0 237 .previous 238 239 sethi %hi(sparc64_kern_pri_nuc_bits), %l1 240 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1 241 or %l0, %l1, %l0 242 243661: stxa %l0, [%l7] ASI_DMMU 244 .section .sun4v_1insn_patch, "ax" 245 .word 661b 246 stxa %l0, [%l7] ASI_MMU 247 .previous 248 249 sethi %hi(KERNBASE), %l7 250 flush %l7 251 rdpr %wstate, %l1 252 rdpr %otherwin, %l2 253 srl %l1, 3, %l1 254 255661: wrpr %l2, %g0, %canrestore 256 .section .fast_win_ctrl_1insn_patch, "ax" 257 .word 661b 258 .word 0x89880000 ! normalw 259 .previous 260 261 wrpr %l1, %g0, %wstate 262 brnz,pt %l2, user_rtt_restore 263661: wrpr %g0, %g0, %otherwin 264 .section .fast_win_ctrl_1insn_patch, "ax" 265 .word 661b 266 nop 267 .previous 268 269 ldx [%g6 + TI_FLAGS], %g3 270 wr %g0, ASI_AIUP, %asi 271 rdpr %cwp, %g1 272 andcc %g3, _TIF_32BIT, %g0 273 sub %g1, 1, %g1 274 bne,pt %xcc, user_rtt_fill_32bit 275 wrpr %g1, %cwp 276 ba,a,pt %xcc, user_rtt_fill_64bit 277 nop 278 279user_rtt_fill_fixup_dax: 280 ba,pt %xcc, user_rtt_fill_fixup_common 281 mov 1, %g3 282 283user_rtt_fill_fixup_mna: 284 ba,pt %xcc, user_rtt_fill_fixup_common 285 mov 2, %g3 286 287user_rtt_fill_fixup: 288 ba,pt %xcc, user_rtt_fill_fixup_common 289 clr %g3 290 291user_rtt_pre_restore: 292 add %g1, 1, %g1 293 wrpr %g1, 0x0, %cwp 294 295user_rtt_restore: 296 restore 297 rdpr %canrestore, %g1 298 wrpr %g1, 0x0, %cleanwin 299 retry 300 nop 301 302kern_rtt: rdpr %canrestore, %g1 303 brz,pn %g1, kern_rtt_fill 304 nop 305kern_rtt_restore: 306 stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC] 307 restore 308 retry 309 310to_kernel: 311#ifdef CONFIG_PREEMPT 312 ldsw [%g6 + TI_PRE_COUNT], %l5 313 brnz %l5, kern_fpucheck 314 ldx [%g6 + TI_FLAGS], %l5 315 andcc %l5, _TIF_NEED_RESCHED, %g0 316 be,pt %xcc, kern_fpucheck 317 nop 318 cmp %l4, 0 319 bne,pn %xcc, kern_fpucheck 320 nop 321 call preempt_schedule_irq 322 nop 323 ba,pt %xcc, rtrap 324#endif 325kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5 326 brz,pt %l5, rt_continue 327 srl %l5, 1, %o0 328 add %g6, TI_FPSAVED, %l6 329 ldub [%l6 + %o0], %l2 330 sub %l5, 2, %l5 331 332 add %g6, TI_GSR, %o1 333 andcc %l2, (FPRS_FEF|FPRS_DU), %g0 334 be,pt %icc, 2f 335 and %l2, FPRS_DL, %l6 336 andcc %l2, FPRS_FEF, %g0 337 be,pn %icc, 5f 338 sll %o0, 3, %o5 339 rd %fprs, %g1 340 341 wr %g1, FPRS_FEF, %fprs 342 ldx [%o1 + %o5], %g1 343 add %g6, TI_XFSR, %o1 344 sll %o0, 8, %o2 345 add %g6, TI_FPREGS, %o3 346 brz,pn %l6, 1f 347 add %g6, TI_FPREGS+0x40, %o4 348 349 membar #Sync 350 ldda [%o3 + %o2] ASI_BLK_P, %f0 351 ldda [%o4 + %o2] ASI_BLK_P, %f16 352 membar #Sync 3531: andcc %l2, FPRS_DU, %g0 354 be,pn %icc, 1f 355 wr %g1, 0, %gsr 356 add %o2, 0x80, %o2 357 membar #Sync 358 ldda [%o3 + %o2] ASI_BLK_P, %f32 359 ldda [%o4 + %o2] ASI_BLK_P, %f48 3601: membar #Sync 361 ldx [%o1 + %o5], %fsr 3622: stb %l5, [%g6 + TI_FPDEPTH] 363 ba,pt %xcc, rt_continue 364 nop 3655: wr %g0, FPRS_FEF, %fprs 366 sll %o0, 8, %o2 367 368 add %g6, TI_FPREGS+0x80, %o3 369 add %g6, TI_FPREGS+0xc0, %o4 370 membar #Sync 371 ldda [%o3 + %o2] ASI_BLK_P, %f32 372 ldda [%o4 + %o2] ASI_BLK_P, %f48 373 membar #Sync 374 wr %g0, FPRS_DU, %fprs 375 ba,pt %xcc, rt_continue 376 stb %l5, [%g6 + TI_FPDEPTH] 377