1 // SPDX-License-Identifier: GPL-2.0 2 /* Performance event support for sparc64. 3 * 4 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net> 5 * 6 * This code is based almost entirely upon the x86 perf event 7 * code, which is: 8 * 9 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> 10 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar 11 * Copyright (C) 2009 Jaswinder Singh Rajput 12 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter 13 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra 14 */ 15 16 #include <linux/perf_event.h> 17 #include <linux/kprobes.h> 18 #include <linux/ftrace.h> 19 #include <linux/kernel.h> 20 #include <linux/kdebug.h> 21 #include <linux/mutex.h> 22 23 #include <asm/stacktrace.h> 24 #include <asm/cpudata.h> 25 #include <linux/uaccess.h> 26 #include <linux/atomic.h> 27 #include <linux/sched/clock.h> 28 #include <asm/nmi.h> 29 #include <asm/pcr.h> 30 #include <asm/cacheflush.h> 31 32 #include "kernel.h" 33 #include "kstack.h" 34 35 /* Two classes of sparc64 chips currently exist. All of which have 36 * 32-bit counters which can generate overflow interrupts on the 37 * transition from 0xffffffff to 0. 38 * 39 * All chips upto and including SPARC-T3 have two performance 40 * counters. The two 32-bit counters are accessed in one go using a 41 * single 64-bit register. 42 * 43 * On these older chips both counters are controlled using a single 44 * control register. The only way to stop all sampling is to clear 45 * all of the context (user, supervisor, hypervisor) sampling enable 46 * bits. But these bits apply to both counters, thus the two counters 47 * can't be enabled/disabled individually. 48 * 49 * Furthermore, the control register on these older chips have two 50 * event fields, one for each of the two counters. It's thus nearly 51 * impossible to have one counter going while keeping the other one 52 * stopped. Therefore it is possible to get overflow interrupts for 53 * counters not currently "in use" and that condition must be checked 54 * in the overflow interrupt handler. 55 * 56 * So we use a hack, in that we program inactive counters with the 57 * "sw_count0" and "sw_count1" events. These count how many times 58 * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an 59 * unusual way to encode a NOP and therefore will not trigger in 60 * normal code. 61 * 62 * Starting with SPARC-T4 we have one control register per counter. 63 * And the counters are stored in individual registers. The registers 64 * for the counters are 64-bit but only a 32-bit counter is 65 * implemented. The event selections on SPARC-T4 lack any 66 * restrictions, therefore we can elide all of the complicated 67 * conflict resolution code we have for SPARC-T3 and earlier chips. 68 */ 69 70 #define MAX_HWEVENTS 4 71 #define MAX_PCRS 4 72 #define MAX_PERIOD ((1UL << 32) - 1) 73 74 #define PIC_UPPER_INDEX 0 75 #define PIC_LOWER_INDEX 1 76 #define PIC_NO_INDEX -1 77 78 struct cpu_hw_events { 79 /* Number of events currently scheduled onto this cpu. 80 * This tells how many entries in the arrays below 81 * are valid. 82 */ 83 int n_events; 84 85 /* Number of new events added since the last hw_perf_disable(). 86 * This works because the perf event layer always adds new 87 * events inside of a perf_{disable,enable}() sequence. 88 */ 89 int n_added; 90 91 /* Array of events current scheduled on this cpu. */ 92 struct perf_event *event[MAX_HWEVENTS]; 93 94 /* Array of encoded longs, specifying the %pcr register 95 * encoding and the mask of PIC counters this even can 96 * be scheduled on. See perf_event_encode() et al. 97 */ 98 unsigned long events[MAX_HWEVENTS]; 99 100 /* The current counter index assigned to an event. When the 101 * event hasn't been programmed into the cpu yet, this will 102 * hold PIC_NO_INDEX. The event->hw.idx value tells us where 103 * we ought to schedule the event. 104 */ 105 int current_idx[MAX_HWEVENTS]; 106 107 /* Software copy of %pcr register(s) on this cpu. */ 108 u64 pcr[MAX_HWEVENTS]; 109 110 /* Enabled/disable state. */ 111 int enabled; 112 113 unsigned int txn_flags; 114 }; 115 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, }; 116 117 /* An event map describes the characteristics of a performance 118 * counter event. In particular it gives the encoding as well as 119 * a mask telling which counters the event can be measured on. 120 * 121 * The mask is unused on SPARC-T4 and later. 122 */ 123 struct perf_event_map { 124 u16 encoding; 125 u8 pic_mask; 126 #define PIC_NONE 0x00 127 #define PIC_UPPER 0x01 128 #define PIC_LOWER 0x02 129 }; 130 131 /* Encode a perf_event_map entry into a long. */ 132 static unsigned long perf_event_encode(const struct perf_event_map *pmap) 133 { 134 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask; 135 } 136 137 static u8 perf_event_get_msk(unsigned long val) 138 { 139 return val & 0xff; 140 } 141 142 static u64 perf_event_get_enc(unsigned long val) 143 { 144 return val >> 16; 145 } 146 147 #define C(x) PERF_COUNT_HW_CACHE_##x 148 149 #define CACHE_OP_UNSUPPORTED 0xfffe 150 #define CACHE_OP_NONSENSE 0xffff 151 152 typedef struct perf_event_map cache_map_t 153 [PERF_COUNT_HW_CACHE_MAX] 154 [PERF_COUNT_HW_CACHE_OP_MAX] 155 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 156 157 struct sparc_pmu { 158 const struct perf_event_map *(*event_map)(int); 159 const cache_map_t *cache_map; 160 int max_events; 161 u32 (*read_pmc)(int); 162 void (*write_pmc)(int, u64); 163 int upper_shift; 164 int lower_shift; 165 int event_mask; 166 int user_bit; 167 int priv_bit; 168 int hv_bit; 169 int irq_bit; 170 int upper_nop; 171 int lower_nop; 172 unsigned int flags; 173 #define SPARC_PMU_ALL_EXCLUDES_SAME 0x00000001 174 #define SPARC_PMU_HAS_CONFLICTS 0x00000002 175 int max_hw_events; 176 int num_pcrs; 177 int num_pic_regs; 178 }; 179 180 static u32 sparc_default_read_pmc(int idx) 181 { 182 u64 val; 183 184 val = pcr_ops->read_pic(0); 185 if (idx == PIC_UPPER_INDEX) 186 val >>= 32; 187 188 return val & 0xffffffff; 189 } 190 191 static void sparc_default_write_pmc(int idx, u64 val) 192 { 193 u64 shift, mask, pic; 194 195 shift = 0; 196 if (idx == PIC_UPPER_INDEX) 197 shift = 32; 198 199 mask = ((u64) 0xffffffff) << shift; 200 val <<= shift; 201 202 pic = pcr_ops->read_pic(0); 203 pic &= ~mask; 204 pic |= val; 205 pcr_ops->write_pic(0, pic); 206 } 207 208 static const struct perf_event_map ultra3_perfmon_event_map[] = { 209 [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER }, 210 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER }, 211 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER }, 212 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER }, 213 }; 214 215 static const struct perf_event_map *ultra3_event_map(int event_id) 216 { 217 return &ultra3_perfmon_event_map[event_id]; 218 } 219 220 static const cache_map_t ultra3_cache_map = { 221 [C(L1D)] = { 222 [C(OP_READ)] = { 223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, 224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, 225 }, 226 [C(OP_WRITE)] = { 227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER }, 228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER }, 229 }, 230 [C(OP_PREFETCH)] = { 231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 232 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 233 }, 234 }, 235 [C(L1I)] = { 236 [C(OP_READ)] = { 237 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, 238 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, 239 }, 240 [ C(OP_WRITE) ] = { 241 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, 242 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, 243 }, 244 [ C(OP_PREFETCH) ] = { 245 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 246 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 247 }, 248 }, 249 [C(LL)] = { 250 [C(OP_READ)] = { 251 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, }, 252 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, }, 253 }, 254 [C(OP_WRITE)] = { 255 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER }, 256 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER }, 257 }, 258 [C(OP_PREFETCH)] = { 259 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 260 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 261 }, 262 }, 263 [C(DTLB)] = { 264 [C(OP_READ)] = { 265 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 266 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, }, 267 }, 268 [ C(OP_WRITE) ] = { 269 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 270 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 271 }, 272 [ C(OP_PREFETCH) ] = { 273 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 274 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 275 }, 276 }, 277 [C(ITLB)] = { 278 [C(OP_READ)] = { 279 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 280 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, }, 281 }, 282 [ C(OP_WRITE) ] = { 283 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 284 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 285 }, 286 [ C(OP_PREFETCH) ] = { 287 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 288 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 289 }, 290 }, 291 [C(BPU)] = { 292 [C(OP_READ)] = { 293 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 294 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 295 }, 296 [ C(OP_WRITE) ] = { 297 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 298 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 299 }, 300 [ C(OP_PREFETCH) ] = { 301 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 302 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 303 }, 304 }, 305 [C(NODE)] = { 306 [C(OP_READ)] = { 307 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 308 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 309 }, 310 [ C(OP_WRITE) ] = { 311 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 312 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 313 }, 314 [ C(OP_PREFETCH) ] = { 315 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 316 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 317 }, 318 }, 319 }; 320 321 static const struct sparc_pmu ultra3_pmu = { 322 .event_map = ultra3_event_map, 323 .cache_map = &ultra3_cache_map, 324 .max_events = ARRAY_SIZE(ultra3_perfmon_event_map), 325 .read_pmc = sparc_default_read_pmc, 326 .write_pmc = sparc_default_write_pmc, 327 .upper_shift = 11, 328 .lower_shift = 4, 329 .event_mask = 0x3f, 330 .user_bit = PCR_UTRACE, 331 .priv_bit = PCR_STRACE, 332 .upper_nop = 0x1c, 333 .lower_nop = 0x14, 334 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | 335 SPARC_PMU_HAS_CONFLICTS), 336 .max_hw_events = 2, 337 .num_pcrs = 1, 338 .num_pic_regs = 1, 339 }; 340 341 /* Niagara1 is very limited. The upper PIC is hard-locked to count 342 * only instructions, so it is free running which creates all kinds of 343 * problems. Some hardware designs make one wonder if the creator 344 * even looked at how this stuff gets used by software. 345 */ 346 static const struct perf_event_map niagara1_perfmon_event_map[] = { 347 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER }, 348 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER }, 349 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE }, 350 [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER }, 351 }; 352 353 static const struct perf_event_map *niagara1_event_map(int event_id) 354 { 355 return &niagara1_perfmon_event_map[event_id]; 356 } 357 358 static const cache_map_t niagara1_cache_map = { 359 [C(L1D)] = { 360 [C(OP_READ)] = { 361 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 362 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, 363 }, 364 [C(OP_WRITE)] = { 365 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 366 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, 367 }, 368 [C(OP_PREFETCH)] = { 369 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 370 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 371 }, 372 }, 373 [C(L1I)] = { 374 [C(OP_READ)] = { 375 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER }, 376 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, }, 377 }, 378 [ C(OP_WRITE) ] = { 379 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, 380 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, 381 }, 382 [ C(OP_PREFETCH) ] = { 383 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 384 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 385 }, 386 }, 387 [C(LL)] = { 388 [C(OP_READ)] = { 389 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 390 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, 391 }, 392 [C(OP_WRITE)] = { 393 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 394 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, 395 }, 396 [C(OP_PREFETCH)] = { 397 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 398 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 399 }, 400 }, 401 [C(DTLB)] = { 402 [C(OP_READ)] = { 403 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 404 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, }, 405 }, 406 [ C(OP_WRITE) ] = { 407 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 408 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 409 }, 410 [ C(OP_PREFETCH) ] = { 411 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 412 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 413 }, 414 }, 415 [C(ITLB)] = { 416 [C(OP_READ)] = { 417 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 418 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, }, 419 }, 420 [ C(OP_WRITE) ] = { 421 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 422 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 423 }, 424 [ C(OP_PREFETCH) ] = { 425 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 426 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 427 }, 428 }, 429 [C(BPU)] = { 430 [C(OP_READ)] = { 431 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 432 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 433 }, 434 [ C(OP_WRITE) ] = { 435 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 436 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 437 }, 438 [ C(OP_PREFETCH) ] = { 439 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 440 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 441 }, 442 }, 443 [C(NODE)] = { 444 [C(OP_READ)] = { 445 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 446 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 447 }, 448 [ C(OP_WRITE) ] = { 449 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 450 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 451 }, 452 [ C(OP_PREFETCH) ] = { 453 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 454 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 455 }, 456 }, 457 }; 458 459 static const struct sparc_pmu niagara1_pmu = { 460 .event_map = niagara1_event_map, 461 .cache_map = &niagara1_cache_map, 462 .max_events = ARRAY_SIZE(niagara1_perfmon_event_map), 463 .read_pmc = sparc_default_read_pmc, 464 .write_pmc = sparc_default_write_pmc, 465 .upper_shift = 0, 466 .lower_shift = 4, 467 .event_mask = 0x7, 468 .user_bit = PCR_UTRACE, 469 .priv_bit = PCR_STRACE, 470 .upper_nop = 0x0, 471 .lower_nop = 0x0, 472 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | 473 SPARC_PMU_HAS_CONFLICTS), 474 .max_hw_events = 2, 475 .num_pcrs = 1, 476 .num_pic_regs = 1, 477 }; 478 479 static const struct perf_event_map niagara2_perfmon_event_map[] = { 480 [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER }, 481 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER }, 482 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER }, 483 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER }, 484 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER }, 485 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER }, 486 }; 487 488 static const struct perf_event_map *niagara2_event_map(int event_id) 489 { 490 return &niagara2_perfmon_event_map[event_id]; 491 } 492 493 static const cache_map_t niagara2_cache_map = { 494 [C(L1D)] = { 495 [C(OP_READ)] = { 496 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, 497 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, 498 }, 499 [C(OP_WRITE)] = { 500 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, 501 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, 502 }, 503 [C(OP_PREFETCH)] = { 504 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 505 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 506 }, 507 }, 508 [C(L1I)] = { 509 [C(OP_READ)] = { 510 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, }, 511 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, }, 512 }, 513 [ C(OP_WRITE) ] = { 514 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, 515 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, 516 }, 517 [ C(OP_PREFETCH) ] = { 518 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 519 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 520 }, 521 }, 522 [C(LL)] = { 523 [C(OP_READ)] = { 524 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, 525 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, }, 526 }, 527 [C(OP_WRITE)] = { 528 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, 529 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, }, 530 }, 531 [C(OP_PREFETCH)] = { 532 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 533 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 534 }, 535 }, 536 [C(DTLB)] = { 537 [C(OP_READ)] = { 538 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 539 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, }, 540 }, 541 [ C(OP_WRITE) ] = { 542 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 543 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 544 }, 545 [ C(OP_PREFETCH) ] = { 546 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 547 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 548 }, 549 }, 550 [C(ITLB)] = { 551 [C(OP_READ)] = { 552 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 553 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, }, 554 }, 555 [ C(OP_WRITE) ] = { 556 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 557 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 558 }, 559 [ C(OP_PREFETCH) ] = { 560 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 561 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 562 }, 563 }, 564 [C(BPU)] = { 565 [C(OP_READ)] = { 566 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 567 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 568 }, 569 [ C(OP_WRITE) ] = { 570 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 571 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 572 }, 573 [ C(OP_PREFETCH) ] = { 574 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 575 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 576 }, 577 }, 578 [C(NODE)] = { 579 [C(OP_READ)] = { 580 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 581 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 582 }, 583 [ C(OP_WRITE) ] = { 584 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 585 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 586 }, 587 [ C(OP_PREFETCH) ] = { 588 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 589 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 590 }, 591 }, 592 }; 593 594 static const struct sparc_pmu niagara2_pmu = { 595 .event_map = niagara2_event_map, 596 .cache_map = &niagara2_cache_map, 597 .max_events = ARRAY_SIZE(niagara2_perfmon_event_map), 598 .read_pmc = sparc_default_read_pmc, 599 .write_pmc = sparc_default_write_pmc, 600 .upper_shift = 19, 601 .lower_shift = 6, 602 .event_mask = 0xfff, 603 .user_bit = PCR_UTRACE, 604 .priv_bit = PCR_STRACE, 605 .hv_bit = PCR_N2_HTRACE, 606 .irq_bit = 0x30, 607 .upper_nop = 0x220, 608 .lower_nop = 0x220, 609 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | 610 SPARC_PMU_HAS_CONFLICTS), 611 .max_hw_events = 2, 612 .num_pcrs = 1, 613 .num_pic_regs = 1, 614 }; 615 616 static const struct perf_event_map niagara4_perfmon_event_map[] = { 617 [PERF_COUNT_HW_CPU_CYCLES] = { (26 << 6) }, 618 [PERF_COUNT_HW_INSTRUCTIONS] = { (3 << 6) | 0x3f }, 619 [PERF_COUNT_HW_CACHE_REFERENCES] = { (3 << 6) | 0x04 }, 620 [PERF_COUNT_HW_CACHE_MISSES] = { (16 << 6) | 0x07 }, 621 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { (4 << 6) | 0x01 }, 622 [PERF_COUNT_HW_BRANCH_MISSES] = { (25 << 6) | 0x0f }, 623 }; 624 625 static const struct perf_event_map *niagara4_event_map(int event_id) 626 { 627 return &niagara4_perfmon_event_map[event_id]; 628 } 629 630 static const cache_map_t niagara4_cache_map = { 631 [C(L1D)] = { 632 [C(OP_READ)] = { 633 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 }, 634 [C(RESULT_MISS)] = { (16 << 6) | 0x07 }, 635 }, 636 [C(OP_WRITE)] = { 637 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 }, 638 [C(RESULT_MISS)] = { (16 << 6) | 0x07 }, 639 }, 640 [C(OP_PREFETCH)] = { 641 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 642 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 643 }, 644 }, 645 [C(L1I)] = { 646 [C(OP_READ)] = { 647 [C(RESULT_ACCESS)] = { (3 << 6) | 0x3f }, 648 [C(RESULT_MISS)] = { (11 << 6) | 0x03 }, 649 }, 650 [ C(OP_WRITE) ] = { 651 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, 652 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, 653 }, 654 [ C(OP_PREFETCH) ] = { 655 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 656 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 657 }, 658 }, 659 [C(LL)] = { 660 [C(OP_READ)] = { 661 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 }, 662 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 663 }, 664 [C(OP_WRITE)] = { 665 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 }, 666 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 667 }, 668 [C(OP_PREFETCH)] = { 669 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 670 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 671 }, 672 }, 673 [C(DTLB)] = { 674 [C(OP_READ)] = { 675 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 676 [C(RESULT_MISS)] = { (17 << 6) | 0x3f }, 677 }, 678 [ C(OP_WRITE) ] = { 679 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 680 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 681 }, 682 [ C(OP_PREFETCH) ] = { 683 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 684 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 685 }, 686 }, 687 [C(ITLB)] = { 688 [C(OP_READ)] = { 689 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 690 [C(RESULT_MISS)] = { (6 << 6) | 0x3f }, 691 }, 692 [ C(OP_WRITE) ] = { 693 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 694 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 695 }, 696 [ C(OP_PREFETCH) ] = { 697 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 698 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 699 }, 700 }, 701 [C(BPU)] = { 702 [C(OP_READ)] = { 703 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 704 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, 705 }, 706 [ C(OP_WRITE) ] = { 707 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 708 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 709 }, 710 [ C(OP_PREFETCH) ] = { 711 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 712 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 713 }, 714 }, 715 [C(NODE)] = { 716 [C(OP_READ)] = { 717 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, 718 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 719 }, 720 [ C(OP_WRITE) ] = { 721 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 722 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 723 }, 724 [ C(OP_PREFETCH) ] = { 725 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, 726 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, 727 }, 728 }, 729 }; 730 731 static u32 sparc_vt_read_pmc(int idx) 732 { 733 u64 val = pcr_ops->read_pic(idx); 734 735 return val & 0xffffffff; 736 } 737 738 static void sparc_vt_write_pmc(int idx, u64 val) 739 { 740 u64 pcr; 741 742 pcr = pcr_ops->read_pcr(idx); 743 /* ensure ov and ntc are reset */ 744 pcr &= ~(PCR_N4_OV | PCR_N4_NTC); 745 746 pcr_ops->write_pic(idx, val & 0xffffffff); 747 748 pcr_ops->write_pcr(idx, pcr); 749 } 750 751 static const struct sparc_pmu niagara4_pmu = { 752 .event_map = niagara4_event_map, 753 .cache_map = &niagara4_cache_map, 754 .max_events = ARRAY_SIZE(niagara4_perfmon_event_map), 755 .read_pmc = sparc_vt_read_pmc, 756 .write_pmc = sparc_vt_write_pmc, 757 .upper_shift = 5, 758 .lower_shift = 5, 759 .event_mask = 0x7ff, 760 .user_bit = PCR_N4_UTRACE, 761 .priv_bit = PCR_N4_STRACE, 762 763 /* We explicitly don't support hypervisor tracing. The T4 764 * generates the overflow event for precise events via a trap 765 * which will not be generated (ie. it's completely lost) if 766 * we happen to be in the hypervisor when the event triggers. 767 * Essentially, the overflow event reporting is completely 768 * unusable when you have hypervisor mode tracing enabled. 769 */ 770 .hv_bit = 0, 771 772 .irq_bit = PCR_N4_TOE, 773 .upper_nop = 0, 774 .lower_nop = 0, 775 .flags = 0, 776 .max_hw_events = 4, 777 .num_pcrs = 4, 778 .num_pic_regs = 4, 779 }; 780 781 static const struct sparc_pmu sparc_m7_pmu = { 782 .event_map = niagara4_event_map, 783 .cache_map = &niagara4_cache_map, 784 .max_events = ARRAY_SIZE(niagara4_perfmon_event_map), 785 .read_pmc = sparc_vt_read_pmc, 786 .write_pmc = sparc_vt_write_pmc, 787 .upper_shift = 5, 788 .lower_shift = 5, 789 .event_mask = 0x7ff, 790 .user_bit = PCR_N4_UTRACE, 791 .priv_bit = PCR_N4_STRACE, 792 793 /* We explicitly don't support hypervisor tracing. */ 794 .hv_bit = 0, 795 796 .irq_bit = PCR_N4_TOE, 797 .upper_nop = 0, 798 .lower_nop = 0, 799 .flags = 0, 800 .max_hw_events = 4, 801 .num_pcrs = 4, 802 .num_pic_regs = 4, 803 }; 804 static const struct sparc_pmu *sparc_pmu __read_mostly; 805 806 static u64 event_encoding(u64 event_id, int idx) 807 { 808 if (idx == PIC_UPPER_INDEX) 809 event_id <<= sparc_pmu->upper_shift; 810 else 811 event_id <<= sparc_pmu->lower_shift; 812 return event_id; 813 } 814 815 static u64 mask_for_index(int idx) 816 { 817 return event_encoding(sparc_pmu->event_mask, idx); 818 } 819 820 static u64 nop_for_index(int idx) 821 { 822 return event_encoding(idx == PIC_UPPER_INDEX ? 823 sparc_pmu->upper_nop : 824 sparc_pmu->lower_nop, idx); 825 } 826 827 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) 828 { 829 u64 enc, val, mask = mask_for_index(idx); 830 int pcr_index = 0; 831 832 if (sparc_pmu->num_pcrs > 1) 833 pcr_index = idx; 834 835 enc = perf_event_get_enc(cpuc->events[idx]); 836 837 val = cpuc->pcr[pcr_index]; 838 val &= ~mask; 839 val |= event_encoding(enc, idx); 840 cpuc->pcr[pcr_index] = val; 841 842 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]); 843 } 844 845 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) 846 { 847 u64 mask = mask_for_index(idx); 848 u64 nop = nop_for_index(idx); 849 int pcr_index = 0; 850 u64 val; 851 852 if (sparc_pmu->num_pcrs > 1) 853 pcr_index = idx; 854 855 val = cpuc->pcr[pcr_index]; 856 val &= ~mask; 857 val |= nop; 858 cpuc->pcr[pcr_index] = val; 859 860 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]); 861 } 862 863 static u64 sparc_perf_event_update(struct perf_event *event, 864 struct hw_perf_event *hwc, int idx) 865 { 866 int shift = 64 - 32; 867 u64 prev_raw_count, new_raw_count; 868 s64 delta; 869 870 again: 871 prev_raw_count = local64_read(&hwc->prev_count); 872 new_raw_count = sparc_pmu->read_pmc(idx); 873 874 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 875 new_raw_count) != prev_raw_count) 876 goto again; 877 878 delta = (new_raw_count << shift) - (prev_raw_count << shift); 879 delta >>= shift; 880 881 local64_add(delta, &event->count); 882 local64_sub(delta, &hwc->period_left); 883 884 return new_raw_count; 885 } 886 887 static int sparc_perf_event_set_period(struct perf_event *event, 888 struct hw_perf_event *hwc, int idx) 889 { 890 s64 left = local64_read(&hwc->period_left); 891 s64 period = hwc->sample_period; 892 int ret = 0; 893 894 if (unlikely(left <= -period)) { 895 left = period; 896 local64_set(&hwc->period_left, left); 897 hwc->last_period = period; 898 ret = 1; 899 } 900 901 if (unlikely(left <= 0)) { 902 left += period; 903 local64_set(&hwc->period_left, left); 904 hwc->last_period = period; 905 ret = 1; 906 } 907 if (left > MAX_PERIOD) 908 left = MAX_PERIOD; 909 910 local64_set(&hwc->prev_count, (u64)-left); 911 912 sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff); 913 914 perf_event_update_userpage(event); 915 916 return ret; 917 } 918 919 static void read_in_all_counters(struct cpu_hw_events *cpuc) 920 { 921 int i; 922 923 for (i = 0; i < cpuc->n_events; i++) { 924 struct perf_event *cp = cpuc->event[i]; 925 926 if (cpuc->current_idx[i] != PIC_NO_INDEX && 927 cpuc->current_idx[i] != cp->hw.idx) { 928 sparc_perf_event_update(cp, &cp->hw, 929 cpuc->current_idx[i]); 930 cpuc->current_idx[i] = PIC_NO_INDEX; 931 if (cp->hw.state & PERF_HES_STOPPED) 932 cp->hw.state |= PERF_HES_ARCH; 933 } 934 } 935 } 936 937 /* On this PMU all PICs are programmed using a single PCR. Calculate 938 * the combined control register value. 939 * 940 * For such chips we require that all of the events have the same 941 * configuration, so just fetch the settings from the first entry. 942 */ 943 static void calculate_single_pcr(struct cpu_hw_events *cpuc) 944 { 945 int i; 946 947 if (!cpuc->n_added) 948 goto out; 949 950 /* Assign to counters all unassigned events. */ 951 for (i = 0; i < cpuc->n_events; i++) { 952 struct perf_event *cp = cpuc->event[i]; 953 struct hw_perf_event *hwc = &cp->hw; 954 int idx = hwc->idx; 955 u64 enc; 956 957 if (cpuc->current_idx[i] != PIC_NO_INDEX) 958 continue; 959 960 sparc_perf_event_set_period(cp, hwc, idx); 961 cpuc->current_idx[i] = idx; 962 963 enc = perf_event_get_enc(cpuc->events[i]); 964 cpuc->pcr[0] &= ~mask_for_index(idx); 965 if (hwc->state & PERF_HES_ARCH) { 966 cpuc->pcr[0] |= nop_for_index(idx); 967 } else { 968 cpuc->pcr[0] |= event_encoding(enc, idx); 969 hwc->state = 0; 970 } 971 } 972 out: 973 cpuc->pcr[0] |= cpuc->event[0]->hw.config_base; 974 } 975 976 static void sparc_pmu_start(struct perf_event *event, int flags); 977 978 /* On this PMU each PIC has it's own PCR control register. */ 979 static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc) 980 { 981 int i; 982 983 if (!cpuc->n_added) 984 goto out; 985 986 for (i = 0; i < cpuc->n_events; i++) { 987 struct perf_event *cp = cpuc->event[i]; 988 struct hw_perf_event *hwc = &cp->hw; 989 int idx = hwc->idx; 990 991 if (cpuc->current_idx[i] != PIC_NO_INDEX) 992 continue; 993 994 cpuc->current_idx[i] = idx; 995 996 if (cp->hw.state & PERF_HES_ARCH) 997 continue; 998 999 sparc_pmu_start(cp, PERF_EF_RELOAD); 1000 } 1001 out: 1002 for (i = 0; i < cpuc->n_events; i++) { 1003 struct perf_event *cp = cpuc->event[i]; 1004 int idx = cp->hw.idx; 1005 1006 cpuc->pcr[idx] |= cp->hw.config_base; 1007 } 1008 } 1009 1010 /* If performance event entries have been added, move existing events 1011 * around (if necessary) and then assign new entries to counters. 1012 */ 1013 static void update_pcrs_for_enable(struct cpu_hw_events *cpuc) 1014 { 1015 if (cpuc->n_added) 1016 read_in_all_counters(cpuc); 1017 1018 if (sparc_pmu->num_pcrs == 1) { 1019 calculate_single_pcr(cpuc); 1020 } else { 1021 calculate_multiple_pcrs(cpuc); 1022 } 1023 } 1024 1025 static void sparc_pmu_enable(struct pmu *pmu) 1026 { 1027 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1028 int i; 1029 1030 if (cpuc->enabled) 1031 return; 1032 1033 cpuc->enabled = 1; 1034 barrier(); 1035 1036 if (cpuc->n_events) 1037 update_pcrs_for_enable(cpuc); 1038 1039 for (i = 0; i < sparc_pmu->num_pcrs; i++) 1040 pcr_ops->write_pcr(i, cpuc->pcr[i]); 1041 } 1042 1043 static void sparc_pmu_disable(struct pmu *pmu) 1044 { 1045 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1046 int i; 1047 1048 if (!cpuc->enabled) 1049 return; 1050 1051 cpuc->enabled = 0; 1052 cpuc->n_added = 0; 1053 1054 for (i = 0; i < sparc_pmu->num_pcrs; i++) { 1055 u64 val = cpuc->pcr[i]; 1056 1057 val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit | 1058 sparc_pmu->hv_bit | sparc_pmu->irq_bit); 1059 cpuc->pcr[i] = val; 1060 pcr_ops->write_pcr(i, cpuc->pcr[i]); 1061 } 1062 } 1063 1064 static int active_event_index(struct cpu_hw_events *cpuc, 1065 struct perf_event *event) 1066 { 1067 int i; 1068 1069 for (i = 0; i < cpuc->n_events; i++) { 1070 if (cpuc->event[i] == event) 1071 break; 1072 } 1073 BUG_ON(i == cpuc->n_events); 1074 return cpuc->current_idx[i]; 1075 } 1076 1077 static void sparc_pmu_start(struct perf_event *event, int flags) 1078 { 1079 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1080 int idx = active_event_index(cpuc, event); 1081 1082 if (flags & PERF_EF_RELOAD) { 1083 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1084 sparc_perf_event_set_period(event, &event->hw, idx); 1085 } 1086 1087 event->hw.state = 0; 1088 1089 sparc_pmu_enable_event(cpuc, &event->hw, idx); 1090 1091 perf_event_update_userpage(event); 1092 } 1093 1094 static void sparc_pmu_stop(struct perf_event *event, int flags) 1095 { 1096 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1097 int idx = active_event_index(cpuc, event); 1098 1099 if (!(event->hw.state & PERF_HES_STOPPED)) { 1100 sparc_pmu_disable_event(cpuc, &event->hw, idx); 1101 event->hw.state |= PERF_HES_STOPPED; 1102 } 1103 1104 if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) { 1105 sparc_perf_event_update(event, &event->hw, idx); 1106 event->hw.state |= PERF_HES_UPTODATE; 1107 } 1108 } 1109 1110 static void sparc_pmu_del(struct perf_event *event, int _flags) 1111 { 1112 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1113 unsigned long flags; 1114 int i; 1115 1116 local_irq_save(flags); 1117 1118 for (i = 0; i < cpuc->n_events; i++) { 1119 if (event == cpuc->event[i]) { 1120 /* Absorb the final count and turn off the 1121 * event. 1122 */ 1123 sparc_pmu_stop(event, PERF_EF_UPDATE); 1124 1125 /* Shift remaining entries down into 1126 * the existing slot. 1127 */ 1128 while (++i < cpuc->n_events) { 1129 cpuc->event[i - 1] = cpuc->event[i]; 1130 cpuc->events[i - 1] = cpuc->events[i]; 1131 cpuc->current_idx[i - 1] = 1132 cpuc->current_idx[i]; 1133 } 1134 1135 perf_event_update_userpage(event); 1136 1137 cpuc->n_events--; 1138 break; 1139 } 1140 } 1141 1142 local_irq_restore(flags); 1143 } 1144 1145 static void sparc_pmu_read(struct perf_event *event) 1146 { 1147 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1148 int idx = active_event_index(cpuc, event); 1149 struct hw_perf_event *hwc = &event->hw; 1150 1151 sparc_perf_event_update(event, hwc, idx); 1152 } 1153 1154 static atomic_t active_events = ATOMIC_INIT(0); 1155 static DEFINE_MUTEX(pmc_grab_mutex); 1156 1157 static void perf_stop_nmi_watchdog(void *unused) 1158 { 1159 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1160 int i; 1161 1162 stop_nmi_watchdog(NULL); 1163 for (i = 0; i < sparc_pmu->num_pcrs; i++) 1164 cpuc->pcr[i] = pcr_ops->read_pcr(i); 1165 } 1166 1167 static void perf_event_grab_pmc(void) 1168 { 1169 if (atomic_inc_not_zero(&active_events)) 1170 return; 1171 1172 mutex_lock(&pmc_grab_mutex); 1173 if (atomic_read(&active_events) == 0) { 1174 if (atomic_read(&nmi_active) > 0) { 1175 on_each_cpu(perf_stop_nmi_watchdog, NULL, 1); 1176 BUG_ON(atomic_read(&nmi_active) != 0); 1177 } 1178 atomic_inc(&active_events); 1179 } 1180 mutex_unlock(&pmc_grab_mutex); 1181 } 1182 1183 static void perf_event_release_pmc(void) 1184 { 1185 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) { 1186 if (atomic_read(&nmi_active) == 0) 1187 on_each_cpu(start_nmi_watchdog, NULL, 1); 1188 mutex_unlock(&pmc_grab_mutex); 1189 } 1190 } 1191 1192 static const struct perf_event_map *sparc_map_cache_event(u64 config) 1193 { 1194 unsigned int cache_type, cache_op, cache_result; 1195 const struct perf_event_map *pmap; 1196 1197 if (!sparc_pmu->cache_map) 1198 return ERR_PTR(-ENOENT); 1199 1200 cache_type = (config >> 0) & 0xff; 1201 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 1202 return ERR_PTR(-EINVAL); 1203 1204 cache_op = (config >> 8) & 0xff; 1205 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 1206 return ERR_PTR(-EINVAL); 1207 1208 cache_result = (config >> 16) & 0xff; 1209 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1210 return ERR_PTR(-EINVAL); 1211 1212 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]); 1213 1214 if (pmap->encoding == CACHE_OP_UNSUPPORTED) 1215 return ERR_PTR(-ENOENT); 1216 1217 if (pmap->encoding == CACHE_OP_NONSENSE) 1218 return ERR_PTR(-EINVAL); 1219 1220 return pmap; 1221 } 1222 1223 static void hw_perf_event_destroy(struct perf_event *event) 1224 { 1225 perf_event_release_pmc(); 1226 } 1227 1228 /* Make sure all events can be scheduled into the hardware at 1229 * the same time. This is simplified by the fact that we only 1230 * need to support 2 simultaneous HW events. 1231 * 1232 * As a side effect, the evts[]->hw.idx values will be assigned 1233 * on success. These are pending indexes. When the events are 1234 * actually programmed into the chip, these values will propagate 1235 * to the per-cpu cpuc->current_idx[] slots, see the code in 1236 * maybe_change_configuration() for details. 1237 */ 1238 static int sparc_check_constraints(struct perf_event **evts, 1239 unsigned long *events, int n_ev) 1240 { 1241 u8 msk0 = 0, msk1 = 0; 1242 int idx0 = 0; 1243 1244 /* This case is possible when we are invoked from 1245 * hw_perf_group_sched_in(). 1246 */ 1247 if (!n_ev) 1248 return 0; 1249 1250 if (n_ev > sparc_pmu->max_hw_events) 1251 return -1; 1252 1253 if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) { 1254 int i; 1255 1256 for (i = 0; i < n_ev; i++) 1257 evts[i]->hw.idx = i; 1258 return 0; 1259 } 1260 1261 msk0 = perf_event_get_msk(events[0]); 1262 if (n_ev == 1) { 1263 if (msk0 & PIC_LOWER) 1264 idx0 = 1; 1265 goto success; 1266 } 1267 BUG_ON(n_ev != 2); 1268 msk1 = perf_event_get_msk(events[1]); 1269 1270 /* If both events can go on any counter, OK. */ 1271 if (msk0 == (PIC_UPPER | PIC_LOWER) && 1272 msk1 == (PIC_UPPER | PIC_LOWER)) 1273 goto success; 1274 1275 /* If one event is limited to a specific counter, 1276 * and the other can go on both, OK. 1277 */ 1278 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) && 1279 msk1 == (PIC_UPPER | PIC_LOWER)) { 1280 if (msk0 & PIC_LOWER) 1281 idx0 = 1; 1282 goto success; 1283 } 1284 1285 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) && 1286 msk0 == (PIC_UPPER | PIC_LOWER)) { 1287 if (msk1 & PIC_UPPER) 1288 idx0 = 1; 1289 goto success; 1290 } 1291 1292 /* If the events are fixed to different counters, OK. */ 1293 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) || 1294 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) { 1295 if (msk0 & PIC_LOWER) 1296 idx0 = 1; 1297 goto success; 1298 } 1299 1300 /* Otherwise, there is a conflict. */ 1301 return -1; 1302 1303 success: 1304 evts[0]->hw.idx = idx0; 1305 if (n_ev == 2) 1306 evts[1]->hw.idx = idx0 ^ 1; 1307 return 0; 1308 } 1309 1310 static int check_excludes(struct perf_event **evts, int n_prev, int n_new) 1311 { 1312 int eu = 0, ek = 0, eh = 0; 1313 struct perf_event *event; 1314 int i, n, first; 1315 1316 if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME)) 1317 return 0; 1318 1319 n = n_prev + n_new; 1320 if (n <= 1) 1321 return 0; 1322 1323 first = 1; 1324 for (i = 0; i < n; i++) { 1325 event = evts[i]; 1326 if (first) { 1327 eu = event->attr.exclude_user; 1328 ek = event->attr.exclude_kernel; 1329 eh = event->attr.exclude_hv; 1330 first = 0; 1331 } else if (event->attr.exclude_user != eu || 1332 event->attr.exclude_kernel != ek || 1333 event->attr.exclude_hv != eh) { 1334 return -EAGAIN; 1335 } 1336 } 1337 1338 return 0; 1339 } 1340 1341 static int collect_events(struct perf_event *group, int max_count, 1342 struct perf_event *evts[], unsigned long *events, 1343 int *current_idx) 1344 { 1345 struct perf_event *event; 1346 int n = 0; 1347 1348 if (!is_software_event(group)) { 1349 if (n >= max_count) 1350 return -1; 1351 evts[n] = group; 1352 events[n] = group->hw.event_base; 1353 current_idx[n++] = PIC_NO_INDEX; 1354 } 1355 for_each_sibling_event(event, group) { 1356 if (!is_software_event(event) && 1357 event->state != PERF_EVENT_STATE_OFF) { 1358 if (n >= max_count) 1359 return -1; 1360 evts[n] = event; 1361 events[n] = event->hw.event_base; 1362 current_idx[n++] = PIC_NO_INDEX; 1363 } 1364 } 1365 return n; 1366 } 1367 1368 static int sparc_pmu_add(struct perf_event *event, int ef_flags) 1369 { 1370 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1371 int n0, ret = -EAGAIN; 1372 unsigned long flags; 1373 1374 local_irq_save(flags); 1375 1376 n0 = cpuc->n_events; 1377 if (n0 >= sparc_pmu->max_hw_events) 1378 goto out; 1379 1380 cpuc->event[n0] = event; 1381 cpuc->events[n0] = event->hw.event_base; 1382 cpuc->current_idx[n0] = PIC_NO_INDEX; 1383 1384 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 1385 if (!(ef_flags & PERF_EF_START)) 1386 event->hw.state |= PERF_HES_ARCH; 1387 1388 /* 1389 * If group events scheduling transaction was started, 1390 * skip the schedulability test here, it will be performed 1391 * at commit time(->commit_txn) as a whole 1392 */ 1393 if (cpuc->txn_flags & PERF_PMU_TXN_ADD) 1394 goto nocheck; 1395 1396 if (check_excludes(cpuc->event, n0, 1)) 1397 goto out; 1398 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) 1399 goto out; 1400 1401 nocheck: 1402 cpuc->n_events++; 1403 cpuc->n_added++; 1404 1405 ret = 0; 1406 out: 1407 local_irq_restore(flags); 1408 return ret; 1409 } 1410 1411 static int sparc_pmu_event_init(struct perf_event *event) 1412 { 1413 struct perf_event_attr *attr = &event->attr; 1414 struct perf_event *evts[MAX_HWEVENTS]; 1415 struct hw_perf_event *hwc = &event->hw; 1416 unsigned long events[MAX_HWEVENTS]; 1417 int current_idx_dmy[MAX_HWEVENTS]; 1418 const struct perf_event_map *pmap; 1419 int n; 1420 1421 if (atomic_read(&nmi_active) < 0) 1422 return -ENODEV; 1423 1424 /* does not support taken branch sampling */ 1425 if (has_branch_stack(event)) 1426 return -EOPNOTSUPP; 1427 1428 switch (attr->type) { 1429 case PERF_TYPE_HARDWARE: 1430 if (attr->config >= sparc_pmu->max_events) 1431 return -EINVAL; 1432 pmap = sparc_pmu->event_map(attr->config); 1433 break; 1434 1435 case PERF_TYPE_HW_CACHE: 1436 pmap = sparc_map_cache_event(attr->config); 1437 if (IS_ERR(pmap)) 1438 return PTR_ERR(pmap); 1439 break; 1440 1441 case PERF_TYPE_RAW: 1442 pmap = NULL; 1443 break; 1444 1445 default: 1446 return -ENOENT; 1447 1448 } 1449 1450 if (pmap) { 1451 hwc->event_base = perf_event_encode(pmap); 1452 } else { 1453 /* 1454 * User gives us "(encoding << 16) | pic_mask" for 1455 * PERF_TYPE_RAW events. 1456 */ 1457 hwc->event_base = attr->config; 1458 } 1459 1460 /* We save the enable bits in the config_base. */ 1461 hwc->config_base = sparc_pmu->irq_bit; 1462 if (!attr->exclude_user) 1463 hwc->config_base |= sparc_pmu->user_bit; 1464 if (!attr->exclude_kernel) 1465 hwc->config_base |= sparc_pmu->priv_bit; 1466 if (!attr->exclude_hv) 1467 hwc->config_base |= sparc_pmu->hv_bit; 1468 1469 n = 0; 1470 if (event->group_leader != event) { 1471 n = collect_events(event->group_leader, 1472 sparc_pmu->max_hw_events - 1, 1473 evts, events, current_idx_dmy); 1474 if (n < 0) 1475 return -EINVAL; 1476 } 1477 events[n] = hwc->event_base; 1478 evts[n] = event; 1479 1480 if (check_excludes(evts, n, 1)) 1481 return -EINVAL; 1482 1483 if (sparc_check_constraints(evts, events, n + 1)) 1484 return -EINVAL; 1485 1486 hwc->idx = PIC_NO_INDEX; 1487 1488 /* Try to do all error checking before this point, as unwinding 1489 * state after grabbing the PMC is difficult. 1490 */ 1491 perf_event_grab_pmc(); 1492 event->destroy = hw_perf_event_destroy; 1493 1494 if (!hwc->sample_period) { 1495 hwc->sample_period = MAX_PERIOD; 1496 hwc->last_period = hwc->sample_period; 1497 local64_set(&hwc->period_left, hwc->sample_period); 1498 } 1499 1500 return 0; 1501 } 1502 1503 /* 1504 * Start group events scheduling transaction 1505 * Set the flag to make pmu::enable() not perform the 1506 * schedulability test, it will be performed at commit time 1507 */ 1508 static void sparc_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1509 { 1510 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1511 1512 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 1513 1514 cpuhw->txn_flags = txn_flags; 1515 if (txn_flags & ~PERF_PMU_TXN_ADD) 1516 return; 1517 1518 perf_pmu_disable(pmu); 1519 } 1520 1521 /* 1522 * Stop group events scheduling transaction 1523 * Clear the flag and pmu::enable() will perform the 1524 * schedulability test. 1525 */ 1526 static void sparc_pmu_cancel_txn(struct pmu *pmu) 1527 { 1528 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1529 unsigned int txn_flags; 1530 1531 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1532 1533 txn_flags = cpuhw->txn_flags; 1534 cpuhw->txn_flags = 0; 1535 if (txn_flags & ~PERF_PMU_TXN_ADD) 1536 return; 1537 1538 perf_pmu_enable(pmu); 1539 } 1540 1541 /* 1542 * Commit group events scheduling transaction 1543 * Perform the group schedulability test as a whole 1544 * Return 0 if success 1545 */ 1546 static int sparc_pmu_commit_txn(struct pmu *pmu) 1547 { 1548 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1549 int n; 1550 1551 if (!sparc_pmu) 1552 return -EINVAL; 1553 1554 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ 1555 1556 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { 1557 cpuc->txn_flags = 0; 1558 return 0; 1559 } 1560 1561 n = cpuc->n_events; 1562 if (check_excludes(cpuc->event, 0, n)) 1563 return -EINVAL; 1564 if (sparc_check_constraints(cpuc->event, cpuc->events, n)) 1565 return -EAGAIN; 1566 1567 cpuc->txn_flags = 0; 1568 perf_pmu_enable(pmu); 1569 return 0; 1570 } 1571 1572 static struct pmu pmu = { 1573 .pmu_enable = sparc_pmu_enable, 1574 .pmu_disable = sparc_pmu_disable, 1575 .event_init = sparc_pmu_event_init, 1576 .add = sparc_pmu_add, 1577 .del = sparc_pmu_del, 1578 .start = sparc_pmu_start, 1579 .stop = sparc_pmu_stop, 1580 .read = sparc_pmu_read, 1581 .start_txn = sparc_pmu_start_txn, 1582 .cancel_txn = sparc_pmu_cancel_txn, 1583 .commit_txn = sparc_pmu_commit_txn, 1584 }; 1585 1586 void perf_event_print_debug(void) 1587 { 1588 unsigned long flags; 1589 int cpu, i; 1590 1591 if (!sparc_pmu) 1592 return; 1593 1594 local_irq_save(flags); 1595 1596 cpu = smp_processor_id(); 1597 1598 pr_info("\n"); 1599 for (i = 0; i < sparc_pmu->num_pcrs; i++) 1600 pr_info("CPU#%d: PCR%d[%016llx]\n", 1601 cpu, i, pcr_ops->read_pcr(i)); 1602 for (i = 0; i < sparc_pmu->num_pic_regs; i++) 1603 pr_info("CPU#%d: PIC%d[%016llx]\n", 1604 cpu, i, pcr_ops->read_pic(i)); 1605 1606 local_irq_restore(flags); 1607 } 1608 1609 static int __kprobes perf_event_nmi_handler(struct notifier_block *self, 1610 unsigned long cmd, void *__args) 1611 { 1612 struct die_args *args = __args; 1613 struct perf_sample_data data; 1614 struct cpu_hw_events *cpuc; 1615 struct pt_regs *regs; 1616 u64 finish_clock; 1617 u64 start_clock; 1618 int i; 1619 1620 if (!atomic_read(&active_events)) 1621 return NOTIFY_DONE; 1622 1623 switch (cmd) { 1624 case DIE_NMI: 1625 break; 1626 1627 default: 1628 return NOTIFY_DONE; 1629 } 1630 1631 start_clock = sched_clock(); 1632 1633 regs = args->regs; 1634 1635 cpuc = this_cpu_ptr(&cpu_hw_events); 1636 1637 /* If the PMU has the TOE IRQ enable bits, we need to do a 1638 * dummy write to the %pcr to clear the overflow bits and thus 1639 * the interrupt. 1640 * 1641 * Do this before we peek at the counters to determine 1642 * overflow so we don't lose any events. 1643 */ 1644 if (sparc_pmu->irq_bit && 1645 sparc_pmu->num_pcrs == 1) 1646 pcr_ops->write_pcr(0, cpuc->pcr[0]); 1647 1648 for (i = 0; i < cpuc->n_events; i++) { 1649 struct perf_event *event = cpuc->event[i]; 1650 int idx = cpuc->current_idx[i]; 1651 struct hw_perf_event *hwc; 1652 u64 val; 1653 1654 if (sparc_pmu->irq_bit && 1655 sparc_pmu->num_pcrs > 1) 1656 pcr_ops->write_pcr(idx, cpuc->pcr[idx]); 1657 1658 hwc = &event->hw; 1659 val = sparc_perf_event_update(event, hwc, idx); 1660 if (val & (1ULL << 31)) 1661 continue; 1662 1663 perf_sample_data_init(&data, 0, hwc->last_period); 1664 if (!sparc_perf_event_set_period(event, hwc, idx)) 1665 continue; 1666 1667 if (perf_event_overflow(event, &data, regs)) 1668 sparc_pmu_stop(event, 0); 1669 } 1670 1671 finish_clock = sched_clock(); 1672 1673 perf_sample_event_took(finish_clock - start_clock); 1674 1675 return NOTIFY_STOP; 1676 } 1677 1678 static __read_mostly struct notifier_block perf_event_nmi_notifier = { 1679 .notifier_call = perf_event_nmi_handler, 1680 }; 1681 1682 static bool __init supported_pmu(void) 1683 { 1684 if (!strcmp(sparc_pmu_type, "ultra3") || 1685 !strcmp(sparc_pmu_type, "ultra3+") || 1686 !strcmp(sparc_pmu_type, "ultra3i") || 1687 !strcmp(sparc_pmu_type, "ultra4+")) { 1688 sparc_pmu = &ultra3_pmu; 1689 return true; 1690 } 1691 if (!strcmp(sparc_pmu_type, "niagara")) { 1692 sparc_pmu = &niagara1_pmu; 1693 return true; 1694 } 1695 if (!strcmp(sparc_pmu_type, "niagara2") || 1696 !strcmp(sparc_pmu_type, "niagara3")) { 1697 sparc_pmu = &niagara2_pmu; 1698 return true; 1699 } 1700 if (!strcmp(sparc_pmu_type, "niagara4") || 1701 !strcmp(sparc_pmu_type, "niagara5")) { 1702 sparc_pmu = &niagara4_pmu; 1703 return true; 1704 } 1705 if (!strcmp(sparc_pmu_type, "sparc-m7")) { 1706 sparc_pmu = &sparc_m7_pmu; 1707 return true; 1708 } 1709 return false; 1710 } 1711 1712 static int __init init_hw_perf_events(void) 1713 { 1714 int err; 1715 1716 pr_info("Performance events: "); 1717 1718 err = pcr_arch_init(); 1719 if (err || !supported_pmu()) { 1720 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type); 1721 return 0; 1722 } 1723 1724 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type); 1725 1726 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 1727 register_die_notifier(&perf_event_nmi_notifier); 1728 1729 return 0; 1730 } 1731 pure_initcall(init_hw_perf_events); 1732 1733 void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, 1734 struct pt_regs *regs) 1735 { 1736 unsigned long ksp, fp; 1737 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1738 int graph = 0; 1739 #endif 1740 1741 stack_trace_flush(); 1742 1743 perf_callchain_store(entry, regs->tpc); 1744 1745 ksp = regs->u_regs[UREG_I6]; 1746 fp = ksp + STACK_BIAS; 1747 do { 1748 struct sparc_stackf *sf; 1749 struct pt_regs *regs; 1750 unsigned long pc; 1751 1752 if (!kstack_valid(current_thread_info(), fp)) 1753 break; 1754 1755 sf = (struct sparc_stackf *) fp; 1756 regs = (struct pt_regs *) (sf + 1); 1757 1758 if (kstack_is_trap_frame(current_thread_info(), regs)) { 1759 if (user_mode(regs)) 1760 break; 1761 pc = regs->tpc; 1762 fp = regs->u_regs[UREG_I6] + STACK_BIAS; 1763 } else { 1764 pc = sf->callers_pc; 1765 fp = (unsigned long)sf->fp + STACK_BIAS; 1766 } 1767 perf_callchain_store(entry, pc); 1768 #ifdef CONFIG_FUNCTION_GRAPH_TRACER 1769 if ((pc + 8UL) == (unsigned long) &return_to_handler) { 1770 struct ftrace_ret_stack *ret_stack; 1771 ret_stack = ftrace_graph_get_ret_stack(current, 1772 graph); 1773 if (ret_stack) { 1774 pc = ret_stack->ret; 1775 perf_callchain_store(entry, pc); 1776 graph++; 1777 } 1778 } 1779 #endif 1780 } while (entry->nr < entry->max_stack); 1781 } 1782 1783 static inline int 1784 valid_user_frame(const void __user *fp, unsigned long size) 1785 { 1786 /* addresses should be at least 4-byte aligned */ 1787 if (((unsigned long) fp) & 3) 1788 return 0; 1789 1790 return (__range_not_ok(fp, size, TASK_SIZE) == 0); 1791 } 1792 1793 static void perf_callchain_user_64(struct perf_callchain_entry_ctx *entry, 1794 struct pt_regs *regs) 1795 { 1796 unsigned long ufp; 1797 1798 ufp = regs->u_regs[UREG_FP] + STACK_BIAS; 1799 do { 1800 struct sparc_stackf __user *usf; 1801 struct sparc_stackf sf; 1802 unsigned long pc; 1803 1804 usf = (struct sparc_stackf __user *)ufp; 1805 if (!valid_user_frame(usf, sizeof(sf))) 1806 break; 1807 1808 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) 1809 break; 1810 1811 pc = sf.callers_pc; 1812 ufp = (unsigned long)sf.fp + STACK_BIAS; 1813 perf_callchain_store(entry, pc); 1814 } while (entry->nr < entry->max_stack); 1815 } 1816 1817 static void perf_callchain_user_32(struct perf_callchain_entry_ctx *entry, 1818 struct pt_regs *regs) 1819 { 1820 unsigned long ufp; 1821 1822 ufp = regs->u_regs[UREG_FP] & 0xffffffffUL; 1823 do { 1824 unsigned long pc; 1825 1826 if (thread32_stack_is_64bit(ufp)) { 1827 struct sparc_stackf __user *usf; 1828 struct sparc_stackf sf; 1829 1830 ufp += STACK_BIAS; 1831 usf = (struct sparc_stackf __user *)ufp; 1832 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) 1833 break; 1834 pc = sf.callers_pc & 0xffffffff; 1835 ufp = ((unsigned long) sf.fp) & 0xffffffff; 1836 } else { 1837 struct sparc_stackf32 __user *usf; 1838 struct sparc_stackf32 sf; 1839 usf = (struct sparc_stackf32 __user *)ufp; 1840 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) 1841 break; 1842 pc = sf.callers_pc; 1843 ufp = (unsigned long)sf.fp; 1844 } 1845 perf_callchain_store(entry, pc); 1846 } while (entry->nr < entry->max_stack); 1847 } 1848 1849 void 1850 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) 1851 { 1852 u64 saved_fault_address = current_thread_info()->fault_address; 1853 u8 saved_fault_code = get_thread_fault_code(); 1854 1855 perf_callchain_store(entry, regs->tpc); 1856 1857 if (!current->mm) 1858 return; 1859 1860 flushw_user(); 1861 1862 pagefault_disable(); 1863 1864 if (test_thread_flag(TIF_32BIT)) 1865 perf_callchain_user_32(entry, regs); 1866 else 1867 perf_callchain_user_64(entry, regs); 1868 1869 pagefault_enable(); 1870 1871 set_thread_fault_code(saved_fault_code); 1872 current_thread_info()->fault_address = saved_fault_address; 1873 } 1874