xref: /openbmc/linux/arch/sparc/kernel/pcic.c (revision e23feb16)
1 /*
2  * pcic.c: MicroSPARC-IIep PCI controller support
3  *
4  * Copyright (C) 1998 V. Roganov and G. Raiko
5  *
6  * Code is derived from Ultra/PCI PSYCHO controller support, see that
7  * for author info.
8  *
9  * Support for diverse IIep based platforms by Pete Zaitcev.
10  * CP-1200 by Eric Brower.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/init.h>
16 #include <linux/mm.h>
17 #include <linux/slab.h>
18 #include <linux/jiffies.h>
19 
20 #include <asm/swift.h> /* for cache flushing. */
21 #include <asm/io.h>
22 
23 #include <linux/ctype.h>
24 #include <linux/pci.h>
25 #include <linux/time.h>
26 #include <linux/timex.h>
27 #include <linux/interrupt.h>
28 #include <linux/export.h>
29 
30 #include <asm/irq.h>
31 #include <asm/oplib.h>
32 #include <asm/prom.h>
33 #include <asm/pcic.h>
34 #include <asm/timex.h>
35 #include <asm/timer.h>
36 #include <asm/uaccess.h>
37 #include <asm/irq_regs.h>
38 
39 #include "irq.h"
40 
41 /*
42  * I studied different documents and many live PROMs both from 2.30
43  * family and 3.xx versions. I came to the amazing conclusion: there is
44  * absolutely no way to route interrupts in IIep systems relying on
45  * information which PROM presents. We must hardcode interrupt routing
46  * schematics. And this actually sucks.   -- zaitcev 1999/05/12
47  *
48  * To find irq for a device we determine which routing map
49  * is in effect or, in other words, on which machine we are running.
50  * We use PROM name for this although other techniques may be used
51  * in special cases (Gleb reports a PROMless IIep based system).
52  * Once we know the map we take device configuration address and
53  * find PCIC pin number where INT line goes. Then we may either program
54  * preferred irq into the PCIC or supply the preexisting irq to the device.
55  */
56 struct pcic_ca2irq {
57 	unsigned char busno;		/* PCI bus number */
58 	unsigned char devfn;		/* Configuration address */
59 	unsigned char pin;		/* PCIC external interrupt pin */
60 	unsigned char irq;		/* Preferred IRQ (mappable in PCIC) */
61 	unsigned int force;		/* Enforce preferred IRQ */
62 };
63 
64 struct pcic_sn2list {
65 	char *sysname;
66 	struct pcic_ca2irq *intmap;
67 	int mapdim;
68 };
69 
70 /*
71  * JavaEngine-1 apparently has different versions.
72  *
73  * According to communications with Sun folks, for P2 build 501-4628-03:
74  * pin 0 - parallel, audio;
75  * pin 1 - Ethernet;
76  * pin 2 - su;
77  * pin 3 - PS/2 kbd and mouse.
78  *
79  * OEM manual (805-1486):
80  * pin 0: Ethernet
81  * pin 1: All EBus
82  * pin 2: IGA (unused)
83  * pin 3: Not connected
84  * OEM manual says that 501-4628 & 501-4811 are the same thing,
85  * only the latter has NAND flash in place.
86  *
87  * So far unofficial Sun wins over the OEM manual. Poor OEMs...
88  */
89 static struct pcic_ca2irq pcic_i_je1a[] = {	/* 501-4811-03 */
90 	{ 0, 0x00, 2, 12, 0 },		/* EBus: hogs all */
91 	{ 0, 0x01, 1,  6, 1 },		/* Happy Meal */
92 	{ 0, 0x80, 0,  7, 0 },		/* IGA (unused) */
93 };
94 
95 /* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
96 static struct pcic_ca2irq pcic_i_jse[] = {
97 	{ 0, 0x00, 0, 13, 0 },		/* Ebus - serial and keyboard */
98 	{ 0, 0x01, 1,  6, 0 },		/* hme */
99 	{ 0, 0x08, 2,  9, 0 },		/* VGA - we hope not used :) */
100 	{ 0, 0x10, 6,  8, 0 },		/* PCI INTA# in Slot 1 */
101 	{ 0, 0x18, 7, 12, 0 },		/* PCI INTA# in Slot 2, shared w. RTC */
102 	{ 0, 0x38, 4,  9, 0 },		/* All ISA devices. Read 8259. */
103 	{ 0, 0x80, 5, 11, 0 },		/* EIDE */
104 	/* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
105 	{ 0, 0xA0, 4,  9, 0 },		/* USB */
106 	/*
107 	 * Some pins belong to non-PCI devices, we hardcode them in drivers.
108 	 * sun4m timers - irq 10, 14
109 	 * PC style RTC - pin 7, irq 4 ?
110 	 * Smart card, Parallel - pin 4 shared with USB, ISA
111 	 * audio - pin 3, irq 5 ?
112 	 */
113 };
114 
115 /* SPARCengine-6 was the original release name of CP1200.
116  * The documentation differs between the two versions
117  */
118 static struct pcic_ca2irq pcic_i_se6[] = {
119 	{ 0, 0x08, 0,  2, 0 },		/* SCSI	*/
120 	{ 0, 0x01, 1,  6, 0 },		/* HME	*/
121 	{ 0, 0x00, 3, 13, 0 },		/* EBus	*/
122 };
123 
124 /*
125  * Krups (courtesy of Varol Kaptan)
126  * No documentation available, but it was easy to guess
127  * because it was very similar to Espresso.
128  *
129  * pin 0 - kbd, mouse, serial;
130  * pin 1 - Ethernet;
131  * pin 2 - igs (we do not use it);
132  * pin 3 - audio;
133  * pin 4,5,6 - unused;
134  * pin 7 - RTC (from P2 onwards as David B. says).
135  */
136 static struct pcic_ca2irq pcic_i_jk[] = {
137 	{ 0, 0x00, 0, 13, 0 },		/* Ebus - serial and keyboard */
138 	{ 0, 0x01, 1,  6, 0 },		/* hme */
139 };
140 
141 /*
142  * Several entries in this list may point to the same routing map
143  * as several PROMs may be installed on the same physical board.
144  */
145 #define SN2L_INIT(name, map)	\
146   { name, map, ARRAY_SIZE(map) }
147 
148 static struct pcic_sn2list pcic_known_sysnames[] = {
149 	SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a),	/* JE1, PROM 2.32 */
150 	SN2L_INIT("SUNW,JS-E", pcic_i_jse),	/* PROLL JavaStation-E */
151 	SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
152 	SN2L_INIT("SUNW,JS-NC", pcic_i_jk),	/* PROLL JavaStation-NC */
153 	SN2L_INIT("SUNW,JSIIep", pcic_i_jk),	/* OBP JavaStation-NC */
154 	{ NULL, NULL, 0 }
155 };
156 
157 /*
158  * Only one PCIC per IIep,
159  * and since we have no SMP IIep, only one per system.
160  */
161 static int pcic0_up;
162 static struct linux_pcic pcic0;
163 
164 void __iomem *pcic_regs;
165 volatile int pcic_speculative;
166 volatile int pcic_trapped;
167 
168 /* forward */
169 unsigned int pcic_build_device_irq(struct platform_device *op,
170                                    unsigned int real_irq);
171 
172 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
173 
174 static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
175     int where, u32 *value)
176 {
177 	struct linux_pcic *pcic;
178 	unsigned long flags;
179 
180 	pcic = &pcic0;
181 
182 	local_irq_save(flags);
183 #if 0 /* does not fail here */
184 	pcic_speculative = 1;
185 	pcic_trapped = 0;
186 #endif
187 	writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
188 #if 0 /* does not fail here */
189 	nop();
190 	if (pcic_trapped) {
191 		local_irq_restore(flags);
192 		*value = ~0;
193 		return 0;
194 	}
195 #endif
196 	pcic_speculative = 2;
197 	pcic_trapped = 0;
198 	*value = readl(pcic->pcic_config_space_data + (where&4));
199 	nop();
200 	if (pcic_trapped) {
201 		pcic_speculative = 0;
202 		local_irq_restore(flags);
203 		*value = ~0;
204 		return 0;
205 	}
206 	pcic_speculative = 0;
207 	local_irq_restore(flags);
208 	return 0;
209 }
210 
211 static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
212    int where, int size, u32 *val)
213 {
214 	unsigned int v;
215 
216 	if (bus->number != 0) return -EINVAL;
217 	switch (size) {
218 	case 1:
219 		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
220 		*val = 0xff & (v >> (8*(where & 3)));
221 		return 0;
222 	case 2:
223 		if (where&1) return -EINVAL;
224 		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
225 		*val = 0xffff & (v >> (8*(where & 3)));
226 		return 0;
227 	case 4:
228 		if (where&3) return -EINVAL;
229 		pcic_read_config_dword(bus->number, devfn, where&~3, val);
230 		return 0;
231 	}
232 	return -EINVAL;
233 }
234 
235 static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
236     int where, u32 value)
237 {
238 	struct linux_pcic *pcic;
239 	unsigned long flags;
240 
241 	pcic = &pcic0;
242 
243 	local_irq_save(flags);
244 	writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
245 	writel(value, pcic->pcic_config_space_data + (where&4));
246 	local_irq_restore(flags);
247 	return 0;
248 }
249 
250 static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
251    int where, int size, u32 val)
252 {
253 	unsigned int v;
254 
255 	if (bus->number != 0) return -EINVAL;
256 	switch (size) {
257 	case 1:
258 		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
259 		v = (v & ~(0xff << (8*(where&3)))) |
260 		    ((0xff&val) << (8*(where&3)));
261 		return pcic_write_config_dword(bus->number, devfn, where&~3, v);
262 	case 2:
263 		if (where&1) return -EINVAL;
264 		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
265 		v = (v & ~(0xffff << (8*(where&3)))) |
266 		    ((0xffff&val) << (8*(where&3)));
267 		return pcic_write_config_dword(bus->number, devfn, where&~3, v);
268 	case 4:
269 		if (where&3) return -EINVAL;
270 		return pcic_write_config_dword(bus->number, devfn, where, val);
271 	}
272 	return -EINVAL;
273 }
274 
275 static struct pci_ops pcic_ops = {
276 	.read =		pcic_read_config,
277 	.write =	pcic_write_config,
278 };
279 
280 /*
281  * On sparc64 pcibios_init() calls pci_controller_probe().
282  * We want PCIC probed little ahead so that interrupt controller
283  * would be operational.
284  */
285 int __init pcic_probe(void)
286 {
287 	struct linux_pcic *pcic;
288 	struct linux_prom_registers regs[PROMREG_MAX];
289 	struct linux_pbm_info* pbm;
290 	char namebuf[64];
291 	phandle node;
292 	int err;
293 
294 	if (pcic0_up) {
295 		prom_printf("PCIC: called twice!\n");
296 		prom_halt();
297 	}
298 	pcic = &pcic0;
299 
300 	node = prom_getchild (prom_root_node);
301 	node = prom_searchsiblings (node, "pci");
302 	if (node == 0)
303 		return -ENODEV;
304 	/*
305 	 * Map in PCIC register set, config space, and IO base
306 	 */
307 	err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
308 	if (err == 0 || err == -1) {
309 		prom_printf("PCIC: Error, cannot get PCIC registers "
310 			    "from PROM.\n");
311 		prom_halt();
312 	}
313 
314 	pcic0_up = 1;
315 
316 	pcic->pcic_res_regs.name = "pcic_registers";
317 	pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
318 	if (!pcic->pcic_regs) {
319 		prom_printf("PCIC: Error, cannot map PCIC registers.\n");
320 		prom_halt();
321 	}
322 
323 	pcic->pcic_res_io.name = "pcic_io";
324 	if ((pcic->pcic_io = (unsigned long)
325 	    ioremap(regs[1].phys_addr, 0x10000)) == 0) {
326 		prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
327 		prom_halt();
328 	}
329 
330 	pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
331 	if ((pcic->pcic_config_space_addr =
332 	    ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == 0) {
333 		prom_printf("PCIC: Error, cannot map "
334 			    "PCI Configuration Space Address.\n");
335 		prom_halt();
336 	}
337 
338 	/*
339 	 * Docs say three least significant bits in address and data
340 	 * must be the same. Thus, we need adjust size of data.
341 	 */
342 	pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
343 	if ((pcic->pcic_config_space_data =
344 	    ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == 0) {
345 		prom_printf("PCIC: Error, cannot map "
346 			    "PCI Configuration Space Data.\n");
347 		prom_halt();
348 	}
349 
350 	pbm = &pcic->pbm;
351 	pbm->prom_node = node;
352 	prom_getstring(node, "name", namebuf, 63);  namebuf[63] = 0;
353 	strcpy(pbm->prom_name, namebuf);
354 
355 	{
356 		extern volatile int t_nmi[4];
357 		extern int pcic_nmi_trap_patch[4];
358 
359 		t_nmi[0] = pcic_nmi_trap_patch[0];
360 		t_nmi[1] = pcic_nmi_trap_patch[1];
361 		t_nmi[2] = pcic_nmi_trap_patch[2];
362 		t_nmi[3] = pcic_nmi_trap_patch[3];
363 		swift_flush_dcache();
364 		pcic_regs = pcic->pcic_regs;
365 	}
366 
367 	prom_getstring(prom_root_node, "name", namebuf, 63);  namebuf[63] = 0;
368 	{
369 		struct pcic_sn2list *p;
370 
371 		for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
372 			if (strcmp(namebuf, p->sysname) == 0)
373 				break;
374 		}
375 		pcic->pcic_imap = p->intmap;
376 		pcic->pcic_imdim = p->mapdim;
377 	}
378 	if (pcic->pcic_imap == NULL) {
379 		/*
380 		 * We do not panic here for the sake of embedded systems.
381 		 */
382 		printk("PCIC: System %s is unknown, cannot route interrupts\n",
383 		    namebuf);
384 	}
385 
386 	return 0;
387 }
388 
389 static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
390 {
391 	struct linux_pbm_info *pbm = &pcic->pbm;
392 
393 	pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
394 #if 0 /* deadwood transplanted from sparc64 */
395 	pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
396 	pci_record_assignments(pbm, pbm->pci_bus);
397 	pci_assign_unassigned(pbm, pbm->pci_bus);
398 	pci_fixup_irq(pbm, pbm->pci_bus);
399 #endif
400 }
401 
402 /*
403  * Main entry point from the PCI subsystem.
404  */
405 static int __init pcic_init(void)
406 {
407 	struct linux_pcic *pcic;
408 
409 	/*
410 	 * PCIC should be initialized at start of the timer.
411 	 * So, here we report the presence of PCIC and do some magic passes.
412 	 */
413 	if(!pcic0_up)
414 		return 0;
415 	pcic = &pcic0;
416 
417 	/*
418 	 *      Switch off IOTLB translation.
419 	 */
420 	writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
421 	       pcic->pcic_regs+PCI_DVMA_CONTROL);
422 
423 	/*
424 	 *      Increase mapped size for PCI memory space (DMA access).
425 	 *      Should be done in that order (size first, address second).
426 	 *      Why we couldn't set up 4GB and forget about it? XXX
427 	 */
428 	writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
429 	writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
430 	       pcic->pcic_regs+PCI_BASE_ADDRESS_0);
431 
432 	pcic_pbm_scan_bus(pcic);
433 
434 	return 0;
435 }
436 
437 int pcic_present(void)
438 {
439 	return pcic0_up;
440 }
441 
442 static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
443 {
444 	struct linux_prom_pci_registers regs[PROMREG_MAX];
445 	int err;
446 	phandle node = prom_getchild(pbm->prom_node);
447 
448 	while(node) {
449 		err = prom_getproperty(node, "reg",
450 				       (char *)&regs[0], sizeof(regs));
451 		if(err != 0 && err != -1) {
452 			unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
453 			if(devfn == pdev->devfn)
454 				return node;
455 		}
456 		node = prom_getsibling(node);
457 	}
458 	return 0;
459 }
460 
461 static inline struct pcidev_cookie *pci_devcookie_alloc(void)
462 {
463 	return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
464 }
465 
466 static void pcic_map_pci_device(struct linux_pcic *pcic,
467     struct pci_dev *dev, int node)
468 {
469 	char namebuf[64];
470 	unsigned long address;
471 	unsigned long flags;
472 	int j;
473 
474 	if (node == 0 || node == -1) {
475 		strcpy(namebuf, "???");
476 	} else {
477 		prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
478 	}
479 
480 	for (j = 0; j < 6; j++) {
481 		address = dev->resource[j].start;
482 		if (address == 0) break;	/* are sequential */
483 		flags = dev->resource[j].flags;
484 		if ((flags & IORESOURCE_IO) != 0) {
485 			if (address < 0x10000) {
486 				/*
487 				 * A device responds to I/O cycles on PCI.
488 				 * We generate these cycles with memory
489 				 * access into the fixed map (phys 0x30000000).
490 				 *
491 				 * Since a device driver does not want to
492 				 * do ioremap() before accessing PC-style I/O,
493 				 * we supply virtual, ready to access address.
494 				 *
495 				 * Note that request_region()
496 				 * works for these devices.
497 				 *
498 				 * XXX Neat trick, but it's a *bad* idea
499 				 * to shit into regions like that.
500 				 * What if we want to allocate one more
501 				 * PCI base address...
502 				 */
503 				dev->resource[j].start =
504 				    pcic->pcic_io + address;
505 				dev->resource[j].end = 1;  /* XXX */
506 				dev->resource[j].flags =
507 				    (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
508 			} else {
509 				/*
510 				 * OOPS... PCI Spec allows this. Sun does
511 				 * not have any devices getting above 64K
512 				 * so it must be user with a weird I/O
513 				 * board in a PCI slot. We must remap it
514 				 * under 64K but it is not done yet. XXX
515 				 */
516 				printk("PCIC: Skipping I/O space at 0x%lx, "
517 				    "this will Oops if a driver attaches "
518 				    "device '%s' at %02x:%02x)\n", address,
519 				    namebuf, dev->bus->number, dev->devfn);
520 			}
521 		}
522 	}
523 }
524 
525 static void
526 pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
527 {
528 	struct pcic_ca2irq *p;
529 	unsigned int real_irq;
530 	int i, ivec;
531 	char namebuf[64];
532 
533 	if (node == 0 || node == -1) {
534 		strcpy(namebuf, "???");
535 	} else {
536 		prom_getstring(node, "name", namebuf, sizeof(namebuf));
537 	}
538 
539 	if ((p = pcic->pcic_imap) == 0) {
540 		dev->irq = 0;
541 		return;
542 	}
543 	for (i = 0; i < pcic->pcic_imdim; i++) {
544 		if (p->busno == dev->bus->number && p->devfn == dev->devfn)
545 			break;
546 		p++;
547 	}
548 	if (i >= pcic->pcic_imdim) {
549 		printk("PCIC: device %s devfn %02x:%02x not found in %d\n",
550 		    namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim);
551 		dev->irq = 0;
552 		return;
553 	}
554 
555 	i = p->pin;
556 	if (i >= 0 && i < 4) {
557 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
558 		real_irq = ivec >> (i << 2) & 0xF;
559 	} else if (i >= 4 && i < 8) {
560 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
561 		real_irq = ivec >> ((i-4) << 2) & 0xF;
562 	} else {					/* Corrupted map */
563 		printk("PCIC: BAD PIN %d\n", i); for (;;) {}
564 	}
565 /* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
566 
567 	/* real_irq means PROM did not bother to program the upper
568 	 * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
569 	 */
570 	if (real_irq == 0 || p->force) {
571 		if (p->irq == 0 || p->irq >= 15) {	/* Corrupted map */
572 			printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
573 		}
574 		printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n",
575 		    p->irq, p->pin, dev->bus->number, dev->devfn);
576 		real_irq = p->irq;
577 
578 		i = p->pin;
579 		if (i >= 4) {
580 			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
581 			ivec &= ~(0xF << ((i - 4) << 2));
582 			ivec |= p->irq << ((i - 4) << 2);
583 			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
584 		} else {
585 			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
586 			ivec &= ~(0xF << (i << 2));
587 			ivec |= p->irq << (i << 2);
588 			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
589 		}
590 	}
591 	dev->irq = pcic_build_device_irq(NULL, real_irq);
592 }
593 
594 /*
595  * Normally called from {do_}pci_scan_bus...
596  */
597 void pcibios_fixup_bus(struct pci_bus *bus)
598 {
599 	struct pci_dev *dev;
600 	int i, has_io, has_mem;
601 	unsigned int cmd;
602 	struct linux_pcic *pcic;
603 	/* struct linux_pbm_info* pbm = &pcic->pbm; */
604 	int node;
605 	struct pcidev_cookie *pcp;
606 
607 	if (!pcic0_up) {
608 		printk("pcibios_fixup_bus: no PCIC\n");
609 		return;
610 	}
611 	pcic = &pcic0;
612 
613 	/*
614 	 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
615 	 */
616 	if (bus->number != 0) {
617 		printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number);
618 		return;
619 	}
620 
621 	list_for_each_entry(dev, &bus->devices, bus_list) {
622 
623 		/*
624 		 * Comment from i386 branch:
625 		 *     There are buggy BIOSes that forget to enable I/O and memory
626 		 *     access to PCI devices. We try to fix this, but we need to
627 		 *     be sure that the BIOS didn't forget to assign an address
628 		 *     to the device. [mj]
629 		 * OBP is a case of such BIOS :-)
630 		 */
631 		has_io = has_mem = 0;
632 		for(i=0; i<6; i++) {
633 			unsigned long f = dev->resource[i].flags;
634 			if (f & IORESOURCE_IO) {
635 				has_io = 1;
636 			} else if (f & IORESOURCE_MEM)
637 				has_mem = 1;
638 		}
639 		pcic_read_config(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
640 		if (has_io && !(cmd & PCI_COMMAND_IO)) {
641 			printk("PCIC: Enabling I/O for device %02x:%02x\n",
642 				dev->bus->number, dev->devfn);
643 			cmd |= PCI_COMMAND_IO;
644 			pcic_write_config(dev->bus, dev->devfn,
645 			    PCI_COMMAND, 2, cmd);
646 		}
647 		if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
648 			printk("PCIC: Enabling memory for device %02x:%02x\n",
649 				dev->bus->number, dev->devfn);
650 			cmd |= PCI_COMMAND_MEMORY;
651 			pcic_write_config(dev->bus, dev->devfn,
652 			    PCI_COMMAND, 2, cmd);
653 		}
654 
655 		node = pdev_to_pnode(&pcic->pbm, dev);
656 		if(node == 0)
657 			node = -1;
658 
659 		/* cookies */
660 		pcp = pci_devcookie_alloc();
661 		pcp->pbm = &pcic->pbm;
662 		pcp->prom_node = of_find_node_by_phandle(node);
663 		dev->sysdata = pcp;
664 
665 		/* fixing I/O to look like memory */
666 		if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
667 			pcic_map_pci_device(pcic, dev, node);
668 
669 		pcic_fill_irq(pcic, dev, node);
670 	}
671 }
672 
673 /*
674  * pcic_pin_to_irq() is exported to bus probing code
675  */
676 unsigned int
677 pcic_pin_to_irq(unsigned int pin, const char *name)
678 {
679 	struct linux_pcic *pcic = &pcic0;
680 	unsigned int irq;
681 	unsigned int ivec;
682 
683 	if (pin < 4) {
684 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
685 		irq = ivec >> (pin << 2) & 0xF;
686 	} else if (pin < 8) {
687 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
688 		irq = ivec >> ((pin-4) << 2) & 0xF;
689 	} else {					/* Corrupted map */
690 		printk("PCIC: BAD PIN %d FOR %s\n", pin, name);
691 		for (;;) {}	/* XXX Cannot panic properly in case of PROLL */
692 	}
693 /* P3 */ /* printk("PCIC: dev %s pin %d ivec 0x%x irq %x\n", name, pin, ivec, irq); */
694 	return irq;
695 }
696 
697 /* Makes compiler happy */
698 static volatile int pcic_timer_dummy;
699 
700 static void pcic_clear_clock_irq(void)
701 {
702 	pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
703 }
704 
705 /* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
706 #define USECS_PER_JIFFY  (1000000 / HZ)
707 #define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
708 
709 static unsigned int pcic_cycles_offset(void)
710 {
711 	u32 value, count;
712 
713 	value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
714 	count = value & ~PCI_SYS_COUNTER_OVERFLOW;
715 
716 	if (value & PCI_SYS_COUNTER_OVERFLOW)
717 		count += TICK_TIMER_LIMIT;
718 	/*
719 	 * We divide all by HZ
720 	 * to have microsecond resolution and to avoid overflow
721 	 */
722 	count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
723 
724 	/* Coordinate with the sparc_config.clock_rate setting */
725 	return count * 2;
726 }
727 
728 void __init pci_time_init(void)
729 {
730 	struct linux_pcic *pcic = &pcic0;
731 	unsigned long v;
732 	int timer_irq, irq;
733 	int err;
734 
735 #ifndef CONFIG_SMP
736 	/*
737 	 * The clock_rate is in SBUS dimension.
738 	 * We take into account this in pcic_cycles_offset()
739 	 */
740 	sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
741 	sparc_config.features |= FEAT_L10_CLOCKEVENT;
742 #endif
743 	sparc_config.features |= FEAT_L10_CLOCKSOURCE;
744 	sparc_config.get_cycles_offset = pcic_cycles_offset;
745 
746 	writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
747 	/* PROM should set appropriate irq */
748 	v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
749 	timer_irq = PCI_COUNTER_IRQ_SYS(v);
750 	writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
751 		pcic->pcic_regs+PCI_COUNTER_IRQ);
752 	irq = pcic_build_device_irq(NULL, timer_irq);
753 	err = request_irq(irq, timer_interrupt,
754 			  IRQF_TIMER, "timer", NULL);
755 	if (err) {
756 		prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
757 		prom_halt();
758 	}
759 	local_irq_enable();
760 }
761 
762 
763 #if 0
764 static void watchdog_reset() {
765 	writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
766 }
767 #endif
768 
769 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
770 				resource_size_t size, resource_size_t align)
771 {
772 	return res->start;
773 }
774 
775 int pcibios_enable_device(struct pci_dev *pdev, int mask)
776 {
777 	return 0;
778 }
779 
780 /*
781  * NMI
782  */
783 void pcic_nmi(unsigned int pend, struct pt_regs *regs)
784 {
785 
786 	pend = flip_dword(pend);
787 
788 	if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
789 		/*
790 		 * XXX On CP-1200 PCI #SERR may happen, we do not know
791 		 * what to do about it yet.
792 		 */
793 		printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
794 		    pend, (int)regs->pc, pcic_speculative);
795 		for (;;) { }
796 	}
797 	pcic_speculative = 0;
798 	pcic_trapped = 1;
799 	regs->pc = regs->npc;
800 	regs->npc += 4;
801 }
802 
803 static inline unsigned long get_irqmask(int irq_nr)
804 {
805 	return 1 << irq_nr;
806 }
807 
808 static void pcic_mask_irq(struct irq_data *data)
809 {
810 	unsigned long mask, flags;
811 
812 	mask = (unsigned long)data->chip_data;
813 	local_irq_save(flags);
814 	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
815 	local_irq_restore(flags);
816 }
817 
818 static void pcic_unmask_irq(struct irq_data *data)
819 {
820 	unsigned long mask, flags;
821 
822 	mask = (unsigned long)data->chip_data;
823 	local_irq_save(flags);
824 	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
825 	local_irq_restore(flags);
826 }
827 
828 static unsigned int pcic_startup_irq(struct irq_data *data)
829 {
830 	irq_link(data->irq);
831 	pcic_unmask_irq(data);
832 	return 0;
833 }
834 
835 static struct irq_chip pcic_irq = {
836 	.name		= "pcic",
837 	.irq_startup	= pcic_startup_irq,
838 	.irq_mask	= pcic_mask_irq,
839 	.irq_unmask	= pcic_unmask_irq,
840 };
841 
842 unsigned int pcic_build_device_irq(struct platform_device *op,
843                                    unsigned int real_irq)
844 {
845 	unsigned int irq;
846 	unsigned long mask;
847 
848 	irq = 0;
849 	mask = get_irqmask(real_irq);
850 	if (mask == 0)
851 		goto out;
852 
853 	irq = irq_alloc(real_irq, real_irq);
854 	if (irq == 0)
855 		goto out;
856 
857 	irq_set_chip_and_handler_name(irq, &pcic_irq,
858 	                              handle_level_irq, "PCIC");
859 	irq_set_chip_data(irq, (void *)mask);
860 
861 out:
862 	return irq;
863 }
864 
865 
866 static void pcic_load_profile_irq(int cpu, unsigned int limit)
867 {
868 	printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
869 }
870 
871 void __init sun4m_pci_init_IRQ(void)
872 {
873 	sparc_config.build_device_irq = pcic_build_device_irq;
874 	sparc_config.clear_clock_irq  = pcic_clear_clock_irq;
875 	sparc_config.load_profile_irq = pcic_load_profile_irq;
876 }
877 
878 /*
879  * This probably belongs here rather than ioport.c because
880  * we do not want this crud linked into SBus kernels.
881  * Also, think for a moment about likes of floppy.c that
882  * include architecture specific parts. They may want to redefine ins/outs.
883  *
884  * We do not use horrible macros here because we want to
885  * advance pointer by sizeof(size).
886  */
887 void outsb(unsigned long addr, const void *src, unsigned long count)
888 {
889 	while (count) {
890 		count -= 1;
891 		outb(*(const char *)src, addr);
892 		src += 1;
893 		/* addr += 1; */
894 	}
895 }
896 EXPORT_SYMBOL(outsb);
897 
898 void outsw(unsigned long addr, const void *src, unsigned long count)
899 {
900 	while (count) {
901 		count -= 2;
902 		outw(*(const short *)src, addr);
903 		src += 2;
904 		/* addr += 2; */
905 	}
906 }
907 EXPORT_SYMBOL(outsw);
908 
909 void outsl(unsigned long addr, const void *src, unsigned long count)
910 {
911 	while (count) {
912 		count -= 4;
913 		outl(*(const long *)src, addr);
914 		src += 4;
915 		/* addr += 4; */
916 	}
917 }
918 EXPORT_SYMBOL(outsl);
919 
920 void insb(unsigned long addr, void *dst, unsigned long count)
921 {
922 	while (count) {
923 		count -= 1;
924 		*(unsigned char *)dst = inb(addr);
925 		dst += 1;
926 		/* addr += 1; */
927 	}
928 }
929 EXPORT_SYMBOL(insb);
930 
931 void insw(unsigned long addr, void *dst, unsigned long count)
932 {
933 	while (count) {
934 		count -= 2;
935 		*(unsigned short *)dst = inw(addr);
936 		dst += 2;
937 		/* addr += 2; */
938 	}
939 }
940 EXPORT_SYMBOL(insw);
941 
942 void insl(unsigned long addr, void *dst, unsigned long count)
943 {
944 	while (count) {
945 		count -= 4;
946 		/*
947 		 * XXX I am sure we are in for an unaligned trap here.
948 		 */
949 		*(unsigned long *)dst = inl(addr);
950 		dst += 4;
951 		/* addr += 4; */
952 	}
953 }
954 EXPORT_SYMBOL(insl);
955 
956 subsys_initcall(pcic_init);
957