xref: /openbmc/linux/arch/sparc/kernel/pcic.c (revision 32d0572a)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * pcic.c: MicroSPARC-IIep PCI controller support
4  *
5  * Copyright (C) 1998 V. Roganov and G. Raiko
6  *
7  * Code is derived from Ultra/PCI PSYCHO controller support, see that
8  * for author info.
9  *
10  * Support for diverse IIep based platforms by Pete Zaitcev.
11  * CP-1200 by Eric Brower.
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 
21 #include <asm/swift.h> /* for cache flushing. */
22 #include <asm/io.h>
23 
24 #include <linux/ctype.h>
25 #include <linux/pci.h>
26 #include <linux/time.h>
27 #include <linux/timex.h>
28 #include <linux/interrupt.h>
29 #include <linux/export.h>
30 
31 #include <asm/irq.h>
32 #include <asm/oplib.h>
33 #include <asm/prom.h>
34 #include <asm/pcic.h>
35 #include <asm/timex.h>
36 #include <asm/timer.h>
37 #include <linux/uaccess.h>
38 #include <asm/irq_regs.h>
39 
40 #include "kernel.h"
41 #include "irq.h"
42 
43 /*
44  * I studied different documents and many live PROMs both from 2.30
45  * family and 3.xx versions. I came to the amazing conclusion: there is
46  * absolutely no way to route interrupts in IIep systems relying on
47  * information which PROM presents. We must hardcode interrupt routing
48  * schematics. And this actually sucks.   -- zaitcev 1999/05/12
49  *
50  * To find irq for a device we determine which routing map
51  * is in effect or, in other words, on which machine we are running.
52  * We use PROM name for this although other techniques may be used
53  * in special cases (Gleb reports a PROMless IIep based system).
54  * Once we know the map we take device configuration address and
55  * find PCIC pin number where INT line goes. Then we may either program
56  * preferred irq into the PCIC or supply the preexisting irq to the device.
57  */
58 struct pcic_ca2irq {
59 	unsigned char busno;		/* PCI bus number */
60 	unsigned char devfn;		/* Configuration address */
61 	unsigned char pin;		/* PCIC external interrupt pin */
62 	unsigned char irq;		/* Preferred IRQ (mappable in PCIC) */
63 	unsigned int force;		/* Enforce preferred IRQ */
64 };
65 
66 struct pcic_sn2list {
67 	char *sysname;
68 	struct pcic_ca2irq *intmap;
69 	int mapdim;
70 };
71 
72 /*
73  * JavaEngine-1 apparently has different versions.
74  *
75  * According to communications with Sun folks, for P2 build 501-4628-03:
76  * pin 0 - parallel, audio;
77  * pin 1 - Ethernet;
78  * pin 2 - su;
79  * pin 3 - PS/2 kbd and mouse.
80  *
81  * OEM manual (805-1486):
82  * pin 0: Ethernet
83  * pin 1: All EBus
84  * pin 2: IGA (unused)
85  * pin 3: Not connected
86  * OEM manual says that 501-4628 & 501-4811 are the same thing,
87  * only the latter has NAND flash in place.
88  *
89  * So far unofficial Sun wins over the OEM manual. Poor OEMs...
90  */
91 static struct pcic_ca2irq pcic_i_je1a[] = {	/* 501-4811-03 */
92 	{ 0, 0x00, 2, 12, 0 },		/* EBus: hogs all */
93 	{ 0, 0x01, 1,  6, 1 },		/* Happy Meal */
94 	{ 0, 0x80, 0,  7, 0 },		/* IGA (unused) */
95 };
96 
97 /* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
98 static struct pcic_ca2irq pcic_i_jse[] = {
99 	{ 0, 0x00, 0, 13, 0 },		/* Ebus - serial and keyboard */
100 	{ 0, 0x01, 1,  6, 0 },		/* hme */
101 	{ 0, 0x08, 2,  9, 0 },		/* VGA - we hope not used :) */
102 	{ 0, 0x10, 6,  8, 0 },		/* PCI INTA# in Slot 1 */
103 	{ 0, 0x18, 7, 12, 0 },		/* PCI INTA# in Slot 2, shared w. RTC */
104 	{ 0, 0x38, 4,  9, 0 },		/* All ISA devices. Read 8259. */
105 	{ 0, 0x80, 5, 11, 0 },		/* EIDE */
106 	/* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
107 	{ 0, 0xA0, 4,  9, 0 },		/* USB */
108 	/*
109 	 * Some pins belong to non-PCI devices, we hardcode them in drivers.
110 	 * sun4m timers - irq 10, 14
111 	 * PC style RTC - pin 7, irq 4 ?
112 	 * Smart card, Parallel - pin 4 shared with USB, ISA
113 	 * audio - pin 3, irq 5 ?
114 	 */
115 };
116 
117 /* SPARCengine-6 was the original release name of CP1200.
118  * The documentation differs between the two versions
119  */
120 static struct pcic_ca2irq pcic_i_se6[] = {
121 	{ 0, 0x08, 0,  2, 0 },		/* SCSI	*/
122 	{ 0, 0x01, 1,  6, 0 },		/* HME	*/
123 	{ 0, 0x00, 3, 13, 0 },		/* EBus	*/
124 };
125 
126 /*
127  * Krups (courtesy of Varol Kaptan)
128  * No documentation available, but it was easy to guess
129  * because it was very similar to Espresso.
130  *
131  * pin 0 - kbd, mouse, serial;
132  * pin 1 - Ethernet;
133  * pin 2 - igs (we do not use it);
134  * pin 3 - audio;
135  * pin 4,5,6 - unused;
136  * pin 7 - RTC (from P2 onwards as David B. says).
137  */
138 static struct pcic_ca2irq pcic_i_jk[] = {
139 	{ 0, 0x00, 0, 13, 0 },		/* Ebus - serial and keyboard */
140 	{ 0, 0x01, 1,  6, 0 },		/* hme */
141 };
142 
143 /*
144  * Several entries in this list may point to the same routing map
145  * as several PROMs may be installed on the same physical board.
146  */
147 #define SN2L_INIT(name, map)	\
148   { name, map, ARRAY_SIZE(map) }
149 
150 static struct pcic_sn2list pcic_known_sysnames[] = {
151 	SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a),	/* JE1, PROM 2.32 */
152 	SN2L_INIT("SUNW,JS-E", pcic_i_jse),	/* PROLL JavaStation-E */
153 	SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
154 	SN2L_INIT("SUNW,JS-NC", pcic_i_jk),	/* PROLL JavaStation-NC */
155 	SN2L_INIT("SUNW,JSIIep", pcic_i_jk),	/* OBP JavaStation-NC */
156 	{ NULL, NULL, 0 }
157 };
158 
159 /*
160  * Only one PCIC per IIep,
161  * and since we have no SMP IIep, only one per system.
162  */
163 static int pcic0_up;
164 static struct linux_pcic pcic0;
165 
166 void __iomem *pcic_regs;
167 static volatile int pcic_speculative;
168 static volatile int pcic_trapped;
169 
170 /* forward */
171 unsigned int pcic_build_device_irq(struct platform_device *op,
172                                    unsigned int real_irq);
173 
174 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
175 
176 static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
177     int where, u32 *value)
178 {
179 	struct linux_pcic *pcic;
180 	unsigned long flags;
181 
182 	pcic = &pcic0;
183 
184 	local_irq_save(flags);
185 #if 0 /* does not fail here */
186 	pcic_speculative = 1;
187 	pcic_trapped = 0;
188 #endif
189 	writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
190 #if 0 /* does not fail here */
191 	nop();
192 	if (pcic_trapped) {
193 		local_irq_restore(flags);
194 		*value = ~0;
195 		return 0;
196 	}
197 #endif
198 	pcic_speculative = 2;
199 	pcic_trapped = 0;
200 	*value = readl(pcic->pcic_config_space_data + (where&4));
201 	nop();
202 	if (pcic_trapped) {
203 		pcic_speculative = 0;
204 		local_irq_restore(flags);
205 		*value = ~0;
206 		return 0;
207 	}
208 	pcic_speculative = 0;
209 	local_irq_restore(flags);
210 	return 0;
211 }
212 
213 static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
214    int where, int size, u32 *val)
215 {
216 	unsigned int v;
217 
218 	if (bus->number != 0) return -EINVAL;
219 	switch (size) {
220 	case 1:
221 		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
222 		*val = 0xff & (v >> (8*(where & 3)));
223 		return 0;
224 	case 2:
225 		if (where&1) return -EINVAL;
226 		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
227 		*val = 0xffff & (v >> (8*(where & 3)));
228 		return 0;
229 	case 4:
230 		if (where&3) return -EINVAL;
231 		pcic_read_config_dword(bus->number, devfn, where&~3, val);
232 		return 0;
233 	}
234 	return -EINVAL;
235 }
236 
237 static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
238     int where, u32 value)
239 {
240 	struct linux_pcic *pcic;
241 	unsigned long flags;
242 
243 	pcic = &pcic0;
244 
245 	local_irq_save(flags);
246 	writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
247 	writel(value, pcic->pcic_config_space_data + (where&4));
248 	local_irq_restore(flags);
249 	return 0;
250 }
251 
252 static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
253    int where, int size, u32 val)
254 {
255 	unsigned int v;
256 
257 	if (bus->number != 0) return -EINVAL;
258 	switch (size) {
259 	case 1:
260 		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
261 		v = (v & ~(0xff << (8*(where&3)))) |
262 		    ((0xff&val) << (8*(where&3)));
263 		return pcic_write_config_dword(bus->number, devfn, where&~3, v);
264 	case 2:
265 		if (where&1) return -EINVAL;
266 		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
267 		v = (v & ~(0xffff << (8*(where&3)))) |
268 		    ((0xffff&val) << (8*(where&3)));
269 		return pcic_write_config_dword(bus->number, devfn, where&~3, v);
270 	case 4:
271 		if (where&3) return -EINVAL;
272 		return pcic_write_config_dword(bus->number, devfn, where, val);
273 	}
274 	return -EINVAL;
275 }
276 
277 static struct pci_ops pcic_ops = {
278 	.read =		pcic_read_config,
279 	.write =	pcic_write_config,
280 };
281 
282 /*
283  * On sparc64 pcibios_init() calls pci_controller_probe().
284  * We want PCIC probed little ahead so that interrupt controller
285  * would be operational.
286  */
287 int __init pcic_probe(void)
288 {
289 	struct linux_pcic *pcic;
290 	struct linux_prom_registers regs[PROMREG_MAX];
291 	struct linux_pbm_info* pbm;
292 	char namebuf[64];
293 	phandle node;
294 	int err;
295 
296 	if (pcic0_up) {
297 		prom_printf("PCIC: called twice!\n");
298 		prom_halt();
299 	}
300 	pcic = &pcic0;
301 
302 	node = prom_getchild (prom_root_node);
303 	node = prom_searchsiblings (node, "pci");
304 	if (node == 0)
305 		return -ENODEV;
306 	/*
307 	 * Map in PCIC register set, config space, and IO base
308 	 */
309 	err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
310 	if (err == 0 || err == -1) {
311 		prom_printf("PCIC: Error, cannot get PCIC registers "
312 			    "from PROM.\n");
313 		prom_halt();
314 	}
315 
316 	pcic0_up = 1;
317 
318 	pcic->pcic_res_regs.name = "pcic_registers";
319 	pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
320 	if (!pcic->pcic_regs) {
321 		prom_printf("PCIC: Error, cannot map PCIC registers.\n");
322 		prom_halt();
323 	}
324 
325 	pcic->pcic_res_io.name = "pcic_io";
326 	if ((pcic->pcic_io = (unsigned long)
327 	    ioremap(regs[1].phys_addr, 0x10000)) == 0) {
328 		prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
329 		prom_halt();
330 	}
331 
332 	pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
333 	if ((pcic->pcic_config_space_addr =
334 	    ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) {
335 		prom_printf("PCIC: Error, cannot map "
336 			    "PCI Configuration Space Address.\n");
337 		prom_halt();
338 	}
339 
340 	/*
341 	 * Docs say three least significant bits in address and data
342 	 * must be the same. Thus, we need adjust size of data.
343 	 */
344 	pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
345 	if ((pcic->pcic_config_space_data =
346 	    ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) {
347 		prom_printf("PCIC: Error, cannot map "
348 			    "PCI Configuration Space Data.\n");
349 		prom_halt();
350 	}
351 
352 	pbm = &pcic->pbm;
353 	pbm->prom_node = node;
354 	prom_getstring(node, "name", namebuf, 63);  namebuf[63] = 0;
355 	strcpy(pbm->prom_name, namebuf);
356 
357 	{
358 		extern int pcic_nmi_trap_patch[4];
359 
360 		t_nmi[0] = pcic_nmi_trap_patch[0];
361 		t_nmi[1] = pcic_nmi_trap_patch[1];
362 		t_nmi[2] = pcic_nmi_trap_patch[2];
363 		t_nmi[3] = pcic_nmi_trap_patch[3];
364 		swift_flush_dcache();
365 		pcic_regs = pcic->pcic_regs;
366 	}
367 
368 	prom_getstring(prom_root_node, "name", namebuf, 63);  namebuf[63] = 0;
369 	{
370 		struct pcic_sn2list *p;
371 
372 		for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
373 			if (strcmp(namebuf, p->sysname) == 0)
374 				break;
375 		}
376 		pcic->pcic_imap = p->intmap;
377 		pcic->pcic_imdim = p->mapdim;
378 	}
379 	if (pcic->pcic_imap == NULL) {
380 		/*
381 		 * We do not panic here for the sake of embedded systems.
382 		 */
383 		printk("PCIC: System %s is unknown, cannot route interrupts\n",
384 		    namebuf);
385 	}
386 
387 	return 0;
388 }
389 
390 static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
391 {
392 	struct linux_pbm_info *pbm = &pcic->pbm;
393 
394 	pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
395 	if (!pbm->pci_bus)
396 		return;
397 
398 #if 0 /* deadwood transplanted from sparc64 */
399 	pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
400 	pci_record_assignments(pbm, pbm->pci_bus);
401 	pci_assign_unassigned(pbm, pbm->pci_bus);
402 	pci_fixup_irq(pbm, pbm->pci_bus);
403 #endif
404 	pci_bus_add_devices(pbm->pci_bus);
405 }
406 
407 /*
408  * Main entry point from the PCI subsystem.
409  */
410 static int __init pcic_init(void)
411 {
412 	struct linux_pcic *pcic;
413 
414 	/*
415 	 * PCIC should be initialized at start of the timer.
416 	 * So, here we report the presence of PCIC and do some magic passes.
417 	 */
418 	if(!pcic0_up)
419 		return 0;
420 	pcic = &pcic0;
421 
422 	/*
423 	 *      Switch off IOTLB translation.
424 	 */
425 	writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
426 	       pcic->pcic_regs+PCI_DVMA_CONTROL);
427 
428 	/*
429 	 *      Increase mapped size for PCI memory space (DMA access).
430 	 *      Should be done in that order (size first, address second).
431 	 *      Why we couldn't set up 4GB and forget about it? XXX
432 	 */
433 	writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
434 	writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
435 	       pcic->pcic_regs+PCI_BASE_ADDRESS_0);
436 
437 	pcic_pbm_scan_bus(pcic);
438 
439 	return 0;
440 }
441 
442 int pcic_present(void)
443 {
444 	return pcic0_up;
445 }
446 
447 static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
448 {
449 	struct linux_prom_pci_registers regs[PROMREG_MAX];
450 	int err;
451 	phandle node = prom_getchild(pbm->prom_node);
452 
453 	while(node) {
454 		err = prom_getproperty(node, "reg",
455 				       (char *)&regs[0], sizeof(regs));
456 		if(err != 0 && err != -1) {
457 			unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
458 			if(devfn == pdev->devfn)
459 				return node;
460 		}
461 		node = prom_getsibling(node);
462 	}
463 	return 0;
464 }
465 
466 static inline struct pcidev_cookie *pci_devcookie_alloc(void)
467 {
468 	return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
469 }
470 
471 static void pcic_map_pci_device(struct linux_pcic *pcic,
472     struct pci_dev *dev, int node)
473 {
474 	char namebuf[64];
475 	unsigned long address;
476 	unsigned long flags;
477 	int j;
478 
479 	if (node == 0 || node == -1) {
480 		strcpy(namebuf, "???");
481 	} else {
482 		prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
483 	}
484 
485 	for (j = 0; j < 6; j++) {
486 		address = dev->resource[j].start;
487 		if (address == 0) break;	/* are sequential */
488 		flags = dev->resource[j].flags;
489 		if ((flags & IORESOURCE_IO) != 0) {
490 			if (address < 0x10000) {
491 				/*
492 				 * A device responds to I/O cycles on PCI.
493 				 * We generate these cycles with memory
494 				 * access into the fixed map (phys 0x30000000).
495 				 *
496 				 * Since a device driver does not want to
497 				 * do ioremap() before accessing PC-style I/O,
498 				 * we supply virtual, ready to access address.
499 				 *
500 				 * Note that request_region()
501 				 * works for these devices.
502 				 *
503 				 * XXX Neat trick, but it's a *bad* idea
504 				 * to shit into regions like that.
505 				 * What if we want to allocate one more
506 				 * PCI base address...
507 				 */
508 				dev->resource[j].start =
509 				    pcic->pcic_io + address;
510 				dev->resource[j].end = 1;  /* XXX */
511 				dev->resource[j].flags =
512 				    (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
513 			} else {
514 				/*
515 				 * OOPS... PCI Spec allows this. Sun does
516 				 * not have any devices getting above 64K
517 				 * so it must be user with a weird I/O
518 				 * board in a PCI slot. We must remap it
519 				 * under 64K but it is not done yet. XXX
520 				 */
521 				printk("PCIC: Skipping I/O space at 0x%lx, "
522 				    "this will Oops if a driver attaches "
523 				    "device '%s' at %02x:%02x)\n", address,
524 				    namebuf, dev->bus->number, dev->devfn);
525 			}
526 		}
527 	}
528 }
529 
530 static void
531 pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
532 {
533 	struct pcic_ca2irq *p;
534 	unsigned int real_irq;
535 	int i, ivec;
536 	char namebuf[64];
537 
538 	if (node == 0 || node == -1) {
539 		strcpy(namebuf, "???");
540 	} else {
541 		prom_getstring(node, "name", namebuf, sizeof(namebuf));
542 	}
543 
544 	if ((p = pcic->pcic_imap) == NULL) {
545 		dev->irq = 0;
546 		return;
547 	}
548 	for (i = 0; i < pcic->pcic_imdim; i++) {
549 		if (p->busno == dev->bus->number && p->devfn == dev->devfn)
550 			break;
551 		p++;
552 	}
553 	if (i >= pcic->pcic_imdim) {
554 		printk("PCIC: device %s devfn %02x:%02x not found in %d\n",
555 		    namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim);
556 		dev->irq = 0;
557 		return;
558 	}
559 
560 	i = p->pin;
561 	if (i >= 0 && i < 4) {
562 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
563 		real_irq = ivec >> (i << 2) & 0xF;
564 	} else if (i >= 4 && i < 8) {
565 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
566 		real_irq = ivec >> ((i-4) << 2) & 0xF;
567 	} else {					/* Corrupted map */
568 		printk("PCIC: BAD PIN %d\n", i); for (;;) {}
569 	}
570 /* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
571 
572 	/* real_irq means PROM did not bother to program the upper
573 	 * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
574 	 */
575 	if (real_irq == 0 || p->force) {
576 		if (p->irq == 0 || p->irq >= 15) {	/* Corrupted map */
577 			printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
578 		}
579 		printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n",
580 		    p->irq, p->pin, dev->bus->number, dev->devfn);
581 		real_irq = p->irq;
582 
583 		i = p->pin;
584 		if (i >= 4) {
585 			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
586 			ivec &= ~(0xF << ((i - 4) << 2));
587 			ivec |= p->irq << ((i - 4) << 2);
588 			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
589 		} else {
590 			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
591 			ivec &= ~(0xF << (i << 2));
592 			ivec |= p->irq << (i << 2);
593 			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
594 		}
595 	}
596 	dev->irq = pcic_build_device_irq(NULL, real_irq);
597 }
598 
599 /*
600  * Normally called from {do_}pci_scan_bus...
601  */
602 void pcibios_fixup_bus(struct pci_bus *bus)
603 {
604 	struct pci_dev *dev;
605 	int i, has_io, has_mem;
606 	unsigned int cmd = 0;
607 	struct linux_pcic *pcic;
608 	/* struct linux_pbm_info* pbm = &pcic->pbm; */
609 	int node;
610 	struct pcidev_cookie *pcp;
611 
612 	if (!pcic0_up) {
613 		printk("pcibios_fixup_bus: no PCIC\n");
614 		return;
615 	}
616 	pcic = &pcic0;
617 
618 	/*
619 	 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
620 	 */
621 	if (bus->number != 0) {
622 		printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number);
623 		return;
624 	}
625 
626 	list_for_each_entry(dev, &bus->devices, bus_list) {
627 
628 		/*
629 		 * Comment from i386 branch:
630 		 *     There are buggy BIOSes that forget to enable I/O and memory
631 		 *     access to PCI devices. We try to fix this, but we need to
632 		 *     be sure that the BIOS didn't forget to assign an address
633 		 *     to the device. [mj]
634 		 * OBP is a case of such BIOS :-)
635 		 */
636 		has_io = has_mem = 0;
637 		for(i=0; i<6; i++) {
638 			unsigned long f = dev->resource[i].flags;
639 			if (f & IORESOURCE_IO) {
640 				has_io = 1;
641 			} else if (f & IORESOURCE_MEM)
642 				has_mem = 1;
643 		}
644 		pcic_read_config(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
645 		if (has_io && !(cmd & PCI_COMMAND_IO)) {
646 			printk("PCIC: Enabling I/O for device %02x:%02x\n",
647 				dev->bus->number, dev->devfn);
648 			cmd |= PCI_COMMAND_IO;
649 			pcic_write_config(dev->bus, dev->devfn,
650 			    PCI_COMMAND, 2, cmd);
651 		}
652 		if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
653 			printk("PCIC: Enabling memory for device %02x:%02x\n",
654 				dev->bus->number, dev->devfn);
655 			cmd |= PCI_COMMAND_MEMORY;
656 			pcic_write_config(dev->bus, dev->devfn,
657 			    PCI_COMMAND, 2, cmd);
658 		}
659 
660 		node = pdev_to_pnode(&pcic->pbm, dev);
661 		if(node == 0)
662 			node = -1;
663 
664 		/* cookies */
665 		pcp = pci_devcookie_alloc();
666 		pcp->pbm = &pcic->pbm;
667 		pcp->prom_node = of_find_node_by_phandle(node);
668 		dev->sysdata = pcp;
669 
670 		/* fixing I/O to look like memory */
671 		if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
672 			pcic_map_pci_device(pcic, dev, node);
673 
674 		pcic_fill_irq(pcic, dev, node);
675 	}
676 }
677 
678 /* Makes compiler happy */
679 static volatile int pcic_timer_dummy;
680 
681 static void pcic_clear_clock_irq(void)
682 {
683 	pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
684 }
685 
686 /* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
687 #define USECS_PER_JIFFY  (1000000 / HZ)
688 #define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
689 
690 static unsigned int pcic_cycles_offset(void)
691 {
692 	u32 value, count;
693 
694 	value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
695 	count = value & ~PCI_SYS_COUNTER_OVERFLOW;
696 
697 	if (value & PCI_SYS_COUNTER_OVERFLOW)
698 		count += TICK_TIMER_LIMIT;
699 	/*
700 	 * We divide all by HZ
701 	 * to have microsecond resolution and to avoid overflow
702 	 */
703 	count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
704 
705 	/* Coordinate with the sparc_config.clock_rate setting */
706 	return count * 2;
707 }
708 
709 void __init pci_time_init(void)
710 {
711 	struct linux_pcic *pcic = &pcic0;
712 	unsigned long v;
713 	int timer_irq, irq;
714 	int err;
715 
716 #ifndef CONFIG_SMP
717 	/*
718 	 * The clock_rate is in SBUS dimension.
719 	 * We take into account this in pcic_cycles_offset()
720 	 */
721 	sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
722 	sparc_config.features |= FEAT_L10_CLOCKEVENT;
723 #endif
724 	sparc_config.features |= FEAT_L10_CLOCKSOURCE;
725 	sparc_config.get_cycles_offset = pcic_cycles_offset;
726 
727 	writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
728 	/* PROM should set appropriate irq */
729 	v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
730 	timer_irq = PCI_COUNTER_IRQ_SYS(v);
731 	writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
732 		pcic->pcic_regs+PCI_COUNTER_IRQ);
733 	irq = pcic_build_device_irq(NULL, timer_irq);
734 	err = request_irq(irq, timer_interrupt,
735 			  IRQF_TIMER, "timer", NULL);
736 	if (err) {
737 		prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
738 		prom_halt();
739 	}
740 	local_irq_enable();
741 }
742 
743 
744 #if 0
745 static void watchdog_reset() {
746 	writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
747 }
748 #endif
749 
750 int pcibios_enable_device(struct pci_dev *pdev, int mask)
751 {
752 	return 0;
753 }
754 
755 /*
756  * NMI
757  */
758 void pcic_nmi(unsigned int pend, struct pt_regs *regs)
759 {
760 
761 	pend = swab32(pend);
762 
763 	if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
764 		/*
765 		 * XXX On CP-1200 PCI #SERR may happen, we do not know
766 		 * what to do about it yet.
767 		 */
768 		printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
769 		    pend, (int)regs->pc, pcic_speculative);
770 		for (;;) { }
771 	}
772 	pcic_speculative = 0;
773 	pcic_trapped = 1;
774 	regs->pc = regs->npc;
775 	regs->npc += 4;
776 }
777 
778 static inline unsigned long get_irqmask(int irq_nr)
779 {
780 	return 1 << irq_nr;
781 }
782 
783 static void pcic_mask_irq(struct irq_data *data)
784 {
785 	unsigned long mask, flags;
786 
787 	mask = (unsigned long)data->chip_data;
788 	local_irq_save(flags);
789 	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
790 	local_irq_restore(flags);
791 }
792 
793 static void pcic_unmask_irq(struct irq_data *data)
794 {
795 	unsigned long mask, flags;
796 
797 	mask = (unsigned long)data->chip_data;
798 	local_irq_save(flags);
799 	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
800 	local_irq_restore(flags);
801 }
802 
803 static unsigned int pcic_startup_irq(struct irq_data *data)
804 {
805 	irq_link(data->irq);
806 	pcic_unmask_irq(data);
807 	return 0;
808 }
809 
810 static struct irq_chip pcic_irq = {
811 	.name		= "pcic",
812 	.irq_startup	= pcic_startup_irq,
813 	.irq_mask	= pcic_mask_irq,
814 	.irq_unmask	= pcic_unmask_irq,
815 };
816 
817 unsigned int pcic_build_device_irq(struct platform_device *op,
818                                    unsigned int real_irq)
819 {
820 	unsigned int irq;
821 	unsigned long mask;
822 
823 	irq = 0;
824 	mask = get_irqmask(real_irq);
825 	if (mask == 0)
826 		goto out;
827 
828 	irq = irq_alloc(real_irq, real_irq);
829 	if (irq == 0)
830 		goto out;
831 
832 	irq_set_chip_and_handler_name(irq, &pcic_irq,
833 	                              handle_level_irq, "PCIC");
834 	irq_set_chip_data(irq, (void *)mask);
835 
836 out:
837 	return irq;
838 }
839 
840 
841 static void pcic_load_profile_irq(int cpu, unsigned int limit)
842 {
843 	printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
844 }
845 
846 void __init sun4m_pci_init_IRQ(void)
847 {
848 	sparc_config.build_device_irq = pcic_build_device_irq;
849 	sparc_config.clear_clock_irq  = pcic_clear_clock_irq;
850 	sparc_config.load_profile_irq = pcic_load_profile_irq;
851 }
852 
853 subsys_initcall(pcic_init);
854