1 /* pci_sun4v.c: SUN4V specific PCI controller support. 2 * 3 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/types.h> 8 #include <linux/pci.h> 9 #include <linux/init.h> 10 #include <linux/slab.h> 11 #include <linux/interrupt.h> 12 #include <linux/percpu.h> 13 #include <linux/irq.h> 14 #include <linux/msi.h> 15 #include <linux/export.h> 16 #include <linux/log2.h> 17 #include <linux/of_device.h> 18 #include <linux/iommu-common.h> 19 20 #include <asm/iommu.h> 21 #include <asm/irq.h> 22 #include <asm/hypervisor.h> 23 #include <asm/prom.h> 24 25 #include "pci_impl.h" 26 #include "iommu_common.h" 27 28 #include "pci_sun4v.h" 29 30 #define DRIVER_NAME "pci_sun4v" 31 #define PFX DRIVER_NAME ": " 32 33 static unsigned long vpci_major; 34 static unsigned long vpci_minor; 35 36 struct vpci_version { 37 unsigned long major; 38 unsigned long minor; 39 }; 40 41 /* Ordered from largest major to lowest */ 42 static struct vpci_version vpci_versions[] = { 43 { .major = 2, .minor = 0 }, 44 { .major = 1, .minor = 1 }, 45 }; 46 47 static unsigned long vatu_major = 1; 48 static unsigned long vatu_minor = 1; 49 50 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64)) 51 52 struct iommu_batch { 53 struct device *dev; /* Device mapping is for. */ 54 unsigned long prot; /* IOMMU page protections */ 55 unsigned long entry; /* Index into IOTSB. */ 56 u64 *pglist; /* List of physical pages */ 57 unsigned long npages; /* Number of pages in list. */ 58 }; 59 60 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch); 61 static int iommu_batch_initialized; 62 63 /* Interrupts must be disabled. */ 64 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry) 65 { 66 struct iommu_batch *p = this_cpu_ptr(&iommu_batch); 67 68 p->dev = dev; 69 p->prot = prot; 70 p->entry = entry; 71 p->npages = 0; 72 } 73 74 /* Interrupts must be disabled. */ 75 static long iommu_batch_flush(struct iommu_batch *p, u64 mask) 76 { 77 struct pci_pbm_info *pbm = p->dev->archdata.host_controller; 78 u64 *pglist = p->pglist; 79 u64 index_count; 80 unsigned long devhandle = pbm->devhandle; 81 unsigned long prot = p->prot; 82 unsigned long entry = p->entry; 83 unsigned long npages = p->npages; 84 unsigned long iotsb_num; 85 unsigned long ret; 86 long num; 87 88 /* VPCI maj=1, min=[0,1] only supports read and write */ 89 if (vpci_major < 2) 90 prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE); 91 92 while (npages != 0) { 93 if (mask <= DMA_BIT_MASK(32)) { 94 num = pci_sun4v_iommu_map(devhandle, 95 HV_PCI_TSBID(0, entry), 96 npages, 97 prot, 98 __pa(pglist)); 99 if (unlikely(num < 0)) { 100 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n", 101 __func__, 102 devhandle, 103 HV_PCI_TSBID(0, entry), 104 npages, prot, __pa(pglist), 105 num); 106 return -1; 107 } 108 } else { 109 index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry), 110 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; 111 ret = pci_sun4v_iotsb_map(devhandle, 112 iotsb_num, 113 index_count, 114 prot, 115 __pa(pglist), 116 &num); 117 if (unlikely(ret != HV_EOK)) { 118 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n", 119 __func__, 120 devhandle, iotsb_num, 121 index_count, prot, 122 __pa(pglist), ret); 123 return -1; 124 } 125 } 126 entry += num; 127 npages -= num; 128 pglist += num; 129 } 130 131 p->entry = entry; 132 p->npages = 0; 133 134 return 0; 135 } 136 137 static inline void iommu_batch_new_entry(unsigned long entry, u64 mask) 138 { 139 struct iommu_batch *p = this_cpu_ptr(&iommu_batch); 140 141 if (p->entry + p->npages == entry) 142 return; 143 if (p->entry != ~0UL) 144 iommu_batch_flush(p, mask); 145 p->entry = entry; 146 } 147 148 /* Interrupts must be disabled. */ 149 static inline long iommu_batch_add(u64 phys_page, u64 mask) 150 { 151 struct iommu_batch *p = this_cpu_ptr(&iommu_batch); 152 153 BUG_ON(p->npages >= PGLIST_NENTS); 154 155 p->pglist[p->npages++] = phys_page; 156 if (p->npages == PGLIST_NENTS) 157 return iommu_batch_flush(p, mask); 158 159 return 0; 160 } 161 162 /* Interrupts must be disabled. */ 163 static inline long iommu_batch_end(u64 mask) 164 { 165 struct iommu_batch *p = this_cpu_ptr(&iommu_batch); 166 167 BUG_ON(p->npages >= PGLIST_NENTS); 168 169 return iommu_batch_flush(p, mask); 170 } 171 172 static void *dma_4v_alloc_coherent(struct device *dev, size_t size, 173 dma_addr_t *dma_addrp, gfp_t gfp, 174 unsigned long attrs) 175 { 176 u64 mask; 177 unsigned long flags, order, first_page, npages, n; 178 unsigned long prot = 0; 179 struct iommu *iommu; 180 struct atu *atu; 181 struct iommu_map_table *tbl; 182 struct page *page; 183 void *ret; 184 long entry; 185 int nid; 186 187 size = IO_PAGE_ALIGN(size); 188 order = get_order(size); 189 if (unlikely(order >= MAX_ORDER)) 190 return NULL; 191 192 npages = size >> IO_PAGE_SHIFT; 193 194 if (attrs & DMA_ATTR_WEAK_ORDERING) 195 prot = HV_PCI_MAP_ATTR_RELAXED_ORDER; 196 197 nid = dev->archdata.numa_node; 198 page = alloc_pages_node(nid, gfp, order); 199 if (unlikely(!page)) 200 return NULL; 201 202 first_page = (unsigned long) page_address(page); 203 memset((char *)first_page, 0, PAGE_SIZE << order); 204 205 iommu = dev->archdata.iommu; 206 atu = iommu->atu; 207 208 mask = dev->coherent_dma_mask; 209 if (mask <= DMA_BIT_MASK(32)) 210 tbl = &iommu->tbl; 211 else 212 tbl = &atu->tbl; 213 214 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL, 215 (unsigned long)(-1), 0); 216 217 if (unlikely(entry == IOMMU_ERROR_CODE)) 218 goto range_alloc_fail; 219 220 *dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT)); 221 ret = (void *) first_page; 222 first_page = __pa(first_page); 223 224 local_irq_save(flags); 225 226 iommu_batch_start(dev, 227 (HV_PCI_MAP_ATTR_READ | prot | 228 HV_PCI_MAP_ATTR_WRITE), 229 entry); 230 231 for (n = 0; n < npages; n++) { 232 long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask); 233 if (unlikely(err < 0L)) 234 goto iommu_map_fail; 235 } 236 237 if (unlikely(iommu_batch_end(mask) < 0L)) 238 goto iommu_map_fail; 239 240 local_irq_restore(flags); 241 242 return ret; 243 244 iommu_map_fail: 245 local_irq_restore(flags); 246 iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE); 247 248 range_alloc_fail: 249 free_pages(first_page, order); 250 return NULL; 251 } 252 253 unsigned long dma_4v_iotsb_bind(unsigned long devhandle, 254 unsigned long iotsb_num, 255 struct pci_bus *bus_dev) 256 { 257 struct pci_dev *pdev; 258 unsigned long err; 259 unsigned int bus; 260 unsigned int device; 261 unsigned int fun; 262 263 list_for_each_entry(pdev, &bus_dev->devices, bus_list) { 264 if (pdev->subordinate) { 265 /* No need to bind pci bridge */ 266 dma_4v_iotsb_bind(devhandle, iotsb_num, 267 pdev->subordinate); 268 } else { 269 bus = bus_dev->number; 270 device = PCI_SLOT(pdev->devfn); 271 fun = PCI_FUNC(pdev->devfn); 272 err = pci_sun4v_iotsb_bind(devhandle, iotsb_num, 273 HV_PCI_DEVICE_BUILD(bus, 274 device, 275 fun)); 276 277 /* If bind fails for one device it is going to fail 278 * for rest of the devices because we are sharing 279 * IOTSB. So in case of failure simply return with 280 * error. 281 */ 282 if (err) 283 return err; 284 } 285 } 286 287 return 0; 288 } 289 290 static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle, 291 dma_addr_t dvma, unsigned long iotsb_num, 292 unsigned long entry, unsigned long npages) 293 { 294 unsigned long num, flags; 295 unsigned long ret; 296 297 local_irq_save(flags); 298 do { 299 if (dvma <= DMA_BIT_MASK(32)) { 300 num = pci_sun4v_iommu_demap(devhandle, 301 HV_PCI_TSBID(0, entry), 302 npages); 303 } else { 304 ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num, 305 entry, npages, &num); 306 if (unlikely(ret != HV_EOK)) { 307 pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n", 308 ret); 309 } 310 } 311 entry += num; 312 npages -= num; 313 } while (npages != 0); 314 local_irq_restore(flags); 315 } 316 317 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu, 318 dma_addr_t dvma, unsigned long attrs) 319 { 320 struct pci_pbm_info *pbm; 321 struct iommu *iommu; 322 struct atu *atu; 323 struct iommu_map_table *tbl; 324 unsigned long order, npages, entry; 325 unsigned long iotsb_num; 326 u32 devhandle; 327 328 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; 329 iommu = dev->archdata.iommu; 330 pbm = dev->archdata.host_controller; 331 atu = iommu->atu; 332 devhandle = pbm->devhandle; 333 334 if (dvma <= DMA_BIT_MASK(32)) { 335 tbl = &iommu->tbl; 336 iotsb_num = 0; /* we don't care for legacy iommu */ 337 } else { 338 tbl = &atu->tbl; 339 iotsb_num = atu->iotsb->iotsb_num; 340 } 341 entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT); 342 dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages); 343 iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE); 344 order = get_order(size); 345 if (order < 10) 346 free_pages((unsigned long)cpu, order); 347 } 348 349 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page, 350 unsigned long offset, size_t sz, 351 enum dma_data_direction direction, 352 unsigned long attrs) 353 { 354 struct iommu *iommu; 355 struct atu *atu; 356 struct iommu_map_table *tbl; 357 u64 mask; 358 unsigned long flags, npages, oaddr; 359 unsigned long i, base_paddr; 360 unsigned long prot; 361 dma_addr_t bus_addr, ret; 362 long entry; 363 364 iommu = dev->archdata.iommu; 365 atu = iommu->atu; 366 367 if (unlikely(direction == DMA_NONE)) 368 goto bad; 369 370 oaddr = (unsigned long)(page_address(page) + offset); 371 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); 372 npages >>= IO_PAGE_SHIFT; 373 374 mask = *dev->dma_mask; 375 if (mask <= DMA_BIT_MASK(32)) 376 tbl = &iommu->tbl; 377 else 378 tbl = &atu->tbl; 379 380 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL, 381 (unsigned long)(-1), 0); 382 383 if (unlikely(entry == IOMMU_ERROR_CODE)) 384 goto bad; 385 386 bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT)); 387 ret = bus_addr | (oaddr & ~IO_PAGE_MASK); 388 base_paddr = __pa(oaddr & IO_PAGE_MASK); 389 prot = HV_PCI_MAP_ATTR_READ; 390 if (direction != DMA_TO_DEVICE) 391 prot |= HV_PCI_MAP_ATTR_WRITE; 392 393 if (attrs & DMA_ATTR_WEAK_ORDERING) 394 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER; 395 396 local_irq_save(flags); 397 398 iommu_batch_start(dev, prot, entry); 399 400 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) { 401 long err = iommu_batch_add(base_paddr, mask); 402 if (unlikely(err < 0L)) 403 goto iommu_map_fail; 404 } 405 if (unlikely(iommu_batch_end(mask) < 0L)) 406 goto iommu_map_fail; 407 408 local_irq_restore(flags); 409 410 return ret; 411 412 bad: 413 if (printk_ratelimit()) 414 WARN_ON(1); 415 return DMA_ERROR_CODE; 416 417 iommu_map_fail: 418 local_irq_restore(flags); 419 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE); 420 return DMA_ERROR_CODE; 421 } 422 423 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr, 424 size_t sz, enum dma_data_direction direction, 425 unsigned long attrs) 426 { 427 struct pci_pbm_info *pbm; 428 struct iommu *iommu; 429 struct atu *atu; 430 struct iommu_map_table *tbl; 431 unsigned long npages; 432 unsigned long iotsb_num; 433 long entry; 434 u32 devhandle; 435 436 if (unlikely(direction == DMA_NONE)) { 437 if (printk_ratelimit()) 438 WARN_ON(1); 439 return; 440 } 441 442 iommu = dev->archdata.iommu; 443 pbm = dev->archdata.host_controller; 444 atu = iommu->atu; 445 devhandle = pbm->devhandle; 446 447 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); 448 npages >>= IO_PAGE_SHIFT; 449 bus_addr &= IO_PAGE_MASK; 450 451 if (bus_addr <= DMA_BIT_MASK(32)) { 452 iotsb_num = 0; /* we don't care for legacy iommu */ 453 tbl = &iommu->tbl; 454 } else { 455 iotsb_num = atu->iotsb->iotsb_num; 456 tbl = &atu->tbl; 457 } 458 entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT; 459 dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages); 460 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE); 461 } 462 463 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist, 464 int nelems, enum dma_data_direction direction, 465 unsigned long attrs) 466 { 467 struct scatterlist *s, *outs, *segstart; 468 unsigned long flags, handle, prot; 469 dma_addr_t dma_next = 0, dma_addr; 470 unsigned int max_seg_size; 471 unsigned long seg_boundary_size; 472 int outcount, incount, i; 473 struct iommu *iommu; 474 struct atu *atu; 475 struct iommu_map_table *tbl; 476 u64 mask; 477 unsigned long base_shift; 478 long err; 479 480 BUG_ON(direction == DMA_NONE); 481 482 iommu = dev->archdata.iommu; 483 if (nelems == 0 || !iommu) 484 return 0; 485 atu = iommu->atu; 486 487 prot = HV_PCI_MAP_ATTR_READ; 488 if (direction != DMA_TO_DEVICE) 489 prot |= HV_PCI_MAP_ATTR_WRITE; 490 491 if (attrs & DMA_ATTR_WEAK_ORDERING) 492 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER; 493 494 outs = s = segstart = &sglist[0]; 495 outcount = 1; 496 incount = nelems; 497 handle = 0; 498 499 /* Init first segment length for backout at failure */ 500 outs->dma_length = 0; 501 502 local_irq_save(flags); 503 504 iommu_batch_start(dev, prot, ~0UL); 505 506 max_seg_size = dma_get_max_seg_size(dev); 507 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, 508 IO_PAGE_SIZE) >> IO_PAGE_SHIFT; 509 510 mask = *dev->dma_mask; 511 if (mask <= DMA_BIT_MASK(32)) 512 tbl = &iommu->tbl; 513 else 514 tbl = &atu->tbl; 515 516 base_shift = tbl->table_map_base >> IO_PAGE_SHIFT; 517 518 for_each_sg(sglist, s, nelems, i) { 519 unsigned long paddr, npages, entry, out_entry = 0, slen; 520 521 slen = s->length; 522 /* Sanity check */ 523 if (slen == 0) { 524 dma_next = 0; 525 continue; 526 } 527 /* Allocate iommu entries for that segment */ 528 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s); 529 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE); 530 entry = iommu_tbl_range_alloc(dev, tbl, npages, 531 &handle, (unsigned long)(-1), 0); 532 533 /* Handle failure */ 534 if (unlikely(entry == IOMMU_ERROR_CODE)) { 535 pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n", 536 tbl, paddr, npages); 537 goto iommu_map_failed; 538 } 539 540 iommu_batch_new_entry(entry, mask); 541 542 /* Convert entry to a dma_addr_t */ 543 dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT); 544 dma_addr |= (s->offset & ~IO_PAGE_MASK); 545 546 /* Insert into HW table */ 547 paddr &= IO_PAGE_MASK; 548 while (npages--) { 549 err = iommu_batch_add(paddr, mask); 550 if (unlikely(err < 0L)) 551 goto iommu_map_failed; 552 paddr += IO_PAGE_SIZE; 553 } 554 555 /* If we are in an open segment, try merging */ 556 if (segstart != s) { 557 /* We cannot merge if: 558 * - allocated dma_addr isn't contiguous to previous allocation 559 */ 560 if ((dma_addr != dma_next) || 561 (outs->dma_length + s->length > max_seg_size) || 562 (is_span_boundary(out_entry, base_shift, 563 seg_boundary_size, outs, s))) { 564 /* Can't merge: create a new segment */ 565 segstart = s; 566 outcount++; 567 outs = sg_next(outs); 568 } else { 569 outs->dma_length += s->length; 570 } 571 } 572 573 if (segstart == s) { 574 /* This is a new segment, fill entries */ 575 outs->dma_address = dma_addr; 576 outs->dma_length = slen; 577 out_entry = entry; 578 } 579 580 /* Calculate next page pointer for contiguous check */ 581 dma_next = dma_addr + slen; 582 } 583 584 err = iommu_batch_end(mask); 585 586 if (unlikely(err < 0L)) 587 goto iommu_map_failed; 588 589 local_irq_restore(flags); 590 591 if (outcount < incount) { 592 outs = sg_next(outs); 593 outs->dma_address = DMA_ERROR_CODE; 594 outs->dma_length = 0; 595 } 596 597 return outcount; 598 599 iommu_map_failed: 600 for_each_sg(sglist, s, nelems, i) { 601 if (s->dma_length != 0) { 602 unsigned long vaddr, npages; 603 604 vaddr = s->dma_address & IO_PAGE_MASK; 605 npages = iommu_num_pages(s->dma_address, s->dma_length, 606 IO_PAGE_SIZE); 607 iommu_tbl_range_free(tbl, vaddr, npages, 608 IOMMU_ERROR_CODE); 609 /* XXX demap? XXX */ 610 s->dma_address = DMA_ERROR_CODE; 611 s->dma_length = 0; 612 } 613 if (s == outs) 614 break; 615 } 616 local_irq_restore(flags); 617 618 return 0; 619 } 620 621 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist, 622 int nelems, enum dma_data_direction direction, 623 unsigned long attrs) 624 { 625 struct pci_pbm_info *pbm; 626 struct scatterlist *sg; 627 struct iommu *iommu; 628 struct atu *atu; 629 unsigned long flags, entry; 630 unsigned long iotsb_num; 631 u32 devhandle; 632 633 BUG_ON(direction == DMA_NONE); 634 635 iommu = dev->archdata.iommu; 636 pbm = dev->archdata.host_controller; 637 atu = iommu->atu; 638 devhandle = pbm->devhandle; 639 640 local_irq_save(flags); 641 642 sg = sglist; 643 while (nelems--) { 644 dma_addr_t dma_handle = sg->dma_address; 645 unsigned int len = sg->dma_length; 646 unsigned long npages; 647 struct iommu_map_table *tbl; 648 unsigned long shift = IO_PAGE_SHIFT; 649 650 if (!len) 651 break; 652 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE); 653 654 if (dma_handle <= DMA_BIT_MASK(32)) { 655 iotsb_num = 0; /* we don't care for legacy iommu */ 656 tbl = &iommu->tbl; 657 } else { 658 iotsb_num = atu->iotsb->iotsb_num; 659 tbl = &atu->tbl; 660 } 661 entry = ((dma_handle - tbl->table_map_base) >> shift); 662 dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num, 663 entry, npages); 664 iommu_tbl_range_free(tbl, dma_handle, npages, 665 IOMMU_ERROR_CODE); 666 sg = sg_next(sg); 667 } 668 669 local_irq_restore(flags); 670 } 671 672 static const struct dma_map_ops sun4v_dma_ops = { 673 .alloc = dma_4v_alloc_coherent, 674 .free = dma_4v_free_coherent, 675 .map_page = dma_4v_map_page, 676 .unmap_page = dma_4v_unmap_page, 677 .map_sg = dma_4v_map_sg, 678 .unmap_sg = dma_4v_unmap_sg, 679 }; 680 681 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent) 682 { 683 struct property *prop; 684 struct device_node *dp; 685 686 dp = pbm->op->dev.of_node; 687 prop = of_find_property(dp, "66mhz-capable", NULL); 688 pbm->is_66mhz_capable = (prop != NULL); 689 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 690 691 /* XXX register error interrupt handlers XXX */ 692 } 693 694 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm, 695 struct iommu_map_table *iommu) 696 { 697 struct iommu_pool *pool; 698 unsigned long i, pool_nr, cnt = 0; 699 u32 devhandle; 700 701 devhandle = pbm->devhandle; 702 for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) { 703 pool = &(iommu->pools[pool_nr]); 704 for (i = pool->start; i <= pool->end; i++) { 705 unsigned long ret, io_attrs, ra; 706 707 ret = pci_sun4v_iommu_getmap(devhandle, 708 HV_PCI_TSBID(0, i), 709 &io_attrs, &ra); 710 if (ret == HV_EOK) { 711 if (page_in_phys_avail(ra)) { 712 pci_sun4v_iommu_demap(devhandle, 713 HV_PCI_TSBID(0, 714 i), 1); 715 } else { 716 cnt++; 717 __set_bit(i, iommu->map); 718 } 719 } 720 } 721 } 722 return cnt; 723 } 724 725 static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm) 726 { 727 struct atu *atu = pbm->iommu->atu; 728 struct atu_iotsb *iotsb; 729 void *table; 730 u64 table_size; 731 u64 iotsb_num; 732 unsigned long order; 733 unsigned long err; 734 735 iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL); 736 if (!iotsb) { 737 err = -ENOMEM; 738 goto out_err; 739 } 740 atu->iotsb = iotsb; 741 742 /* calculate size of IOTSB */ 743 table_size = (atu->size / IO_PAGE_SIZE) * 8; 744 order = get_order(table_size); 745 table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); 746 if (!table) { 747 err = -ENOMEM; 748 goto table_failed; 749 } 750 iotsb->table = table; 751 iotsb->ra = __pa(table); 752 iotsb->dvma_size = atu->size; 753 iotsb->dvma_base = atu->base; 754 iotsb->table_size = table_size; 755 iotsb->page_size = IO_PAGE_SIZE; 756 757 /* configure and register IOTSB with HV */ 758 err = pci_sun4v_iotsb_conf(pbm->devhandle, 759 iotsb->ra, 760 iotsb->table_size, 761 iotsb->page_size, 762 iotsb->dvma_base, 763 &iotsb_num); 764 if (err) { 765 pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err); 766 goto iotsb_conf_failed; 767 } 768 iotsb->iotsb_num = iotsb_num; 769 770 err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus); 771 if (err) { 772 pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err); 773 goto iotsb_conf_failed; 774 } 775 776 return 0; 777 778 iotsb_conf_failed: 779 free_pages((unsigned long)table, order); 780 table_failed: 781 kfree(iotsb); 782 out_err: 783 return err; 784 } 785 786 static int pci_sun4v_atu_init(struct pci_pbm_info *pbm) 787 { 788 struct atu *atu = pbm->iommu->atu; 789 unsigned long err; 790 const u64 *ranges; 791 u64 map_size, num_iotte; 792 u64 dma_mask; 793 const u32 *page_size; 794 int len; 795 796 ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges", 797 &len); 798 if (!ranges) { 799 pr_err(PFX "No iommu-address-ranges\n"); 800 return -EINVAL; 801 } 802 803 page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes", 804 NULL); 805 if (!page_size) { 806 pr_err(PFX "No iommu-pagesizes\n"); 807 return -EINVAL; 808 } 809 810 /* There are 4 iommu-address-ranges supported. Each range is pair of 811 * {base, size}. The ranges[0] and ranges[1] are 32bit address space 812 * while ranges[2] and ranges[3] are 64bit space. We want to use 64bit 813 * address ranges to support 64bit addressing. Because 'size' for 814 * address ranges[2] and ranges[3] are same we can select either of 815 * ranges[2] or ranges[3] for mapping. However due to 'size' is too 816 * large for OS to allocate IOTSB we are using fix size 32G 817 * (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices 818 * to share. 819 */ 820 atu->ranges = (struct atu_ranges *)ranges; 821 atu->base = atu->ranges[3].base; 822 atu->size = ATU_64_SPACE_SIZE; 823 824 /* Create IOTSB */ 825 err = pci_sun4v_atu_alloc_iotsb(pbm); 826 if (err) { 827 pr_err(PFX "Error creating ATU IOTSB\n"); 828 return err; 829 } 830 831 /* Create ATU iommu map. 832 * One bit represents one iotte in IOTSB table. 833 */ 834 dma_mask = (roundup_pow_of_two(atu->size) - 1UL); 835 num_iotte = atu->size / IO_PAGE_SIZE; 836 map_size = num_iotte / 8; 837 atu->tbl.table_map_base = atu->base; 838 atu->dma_addr_mask = dma_mask; 839 atu->tbl.map = kzalloc(map_size, GFP_KERNEL); 840 if (!atu->tbl.map) 841 return -ENOMEM; 842 843 iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT, 844 NULL, false /* no large_pool */, 845 0 /* default npools */, 846 false /* want span boundary checking */); 847 848 return 0; 849 } 850 851 static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm) 852 { 853 static const u32 vdma_default[] = { 0x80000000, 0x80000000 }; 854 struct iommu *iommu = pbm->iommu; 855 unsigned long num_tsb_entries, sz; 856 u32 dma_mask, dma_offset; 857 const u32 *vdma; 858 859 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); 860 if (!vdma) 861 vdma = vdma_default; 862 863 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) { 864 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n", 865 vdma[0], vdma[1]); 866 return -EINVAL; 867 } 868 869 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL); 870 num_tsb_entries = vdma[1] / IO_PAGE_SIZE; 871 872 dma_offset = vdma[0]; 873 874 /* Setup initial software IOMMU state. */ 875 spin_lock_init(&iommu->lock); 876 iommu->ctx_lowest_free = 1; 877 iommu->tbl.table_map_base = dma_offset; 878 iommu->dma_addr_mask = dma_mask; 879 880 /* Allocate and initialize the free area map. */ 881 sz = (num_tsb_entries + 7) / 8; 882 sz = (sz + 7UL) & ~7UL; 883 iommu->tbl.map = kzalloc(sz, GFP_KERNEL); 884 if (!iommu->tbl.map) { 885 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n"); 886 return -ENOMEM; 887 } 888 iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT, 889 NULL, false /* no large_pool */, 890 0 /* default npools */, 891 false /* want span boundary checking */); 892 sz = probe_existing_entries(pbm, &iommu->tbl); 893 if (sz) 894 printk("%s: Imported %lu TSB entries from OBP\n", 895 pbm->name, sz); 896 897 return 0; 898 } 899 900 #ifdef CONFIG_PCI_MSI 901 struct pci_sun4v_msiq_entry { 902 u64 version_type; 903 #define MSIQ_VERSION_MASK 0xffffffff00000000UL 904 #define MSIQ_VERSION_SHIFT 32 905 #define MSIQ_TYPE_MASK 0x00000000000000ffUL 906 #define MSIQ_TYPE_SHIFT 0 907 #define MSIQ_TYPE_NONE 0x00 908 #define MSIQ_TYPE_MSG 0x01 909 #define MSIQ_TYPE_MSI32 0x02 910 #define MSIQ_TYPE_MSI64 0x03 911 #define MSIQ_TYPE_INTX 0x08 912 #define MSIQ_TYPE_NONE2 0xff 913 914 u64 intx_sysino; 915 u64 reserved1; 916 u64 stick; 917 u64 req_id; /* bus/device/func */ 918 #define MSIQ_REQID_BUS_MASK 0xff00UL 919 #define MSIQ_REQID_BUS_SHIFT 8 920 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL 921 #define MSIQ_REQID_DEVICE_SHIFT 3 922 #define MSIQ_REQID_FUNC_MASK 0x0007UL 923 #define MSIQ_REQID_FUNC_SHIFT 0 924 925 u64 msi_address; 926 927 /* The format of this value is message type dependent. 928 * For MSI bits 15:0 are the data from the MSI packet. 929 * For MSI-X bits 31:0 are the data from the MSI packet. 930 * For MSG, the message code and message routing code where: 931 * bits 39:32 is the bus/device/fn of the msg target-id 932 * bits 18:16 is the message routing code 933 * bits 7:0 is the message code 934 * For INTx the low order 2-bits are: 935 * 00 - INTA 936 * 01 - INTB 937 * 10 - INTC 938 * 11 - INTD 939 */ 940 u64 msi_data; 941 942 u64 reserved2; 943 }; 944 945 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid, 946 unsigned long *head) 947 { 948 unsigned long err, limit; 949 950 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head); 951 if (unlikely(err)) 952 return -ENXIO; 953 954 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); 955 if (unlikely(*head >= limit)) 956 return -EFBIG; 957 958 return 0; 959 } 960 961 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm, 962 unsigned long msiqid, unsigned long *head, 963 unsigned long *msi) 964 { 965 struct pci_sun4v_msiq_entry *ep; 966 unsigned long err, type; 967 968 /* Note: void pointer arithmetic, 'head' is a byte offset */ 969 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 970 (pbm->msiq_ent_count * 971 sizeof(struct pci_sun4v_msiq_entry))) + 972 *head); 973 974 if ((ep->version_type & MSIQ_TYPE_MASK) == 0) 975 return 0; 976 977 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT; 978 if (unlikely(type != MSIQ_TYPE_MSI32 && 979 type != MSIQ_TYPE_MSI64)) 980 return -EINVAL; 981 982 *msi = ep->msi_data; 983 984 err = pci_sun4v_msi_setstate(pbm->devhandle, 985 ep->msi_data /* msi_num */, 986 HV_MSISTATE_IDLE); 987 if (unlikely(err)) 988 return -ENXIO; 989 990 /* Clear the entry. */ 991 ep->version_type &= ~MSIQ_TYPE_MASK; 992 993 (*head) += sizeof(struct pci_sun4v_msiq_entry); 994 if (*head >= 995 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))) 996 *head = 0; 997 998 return 1; 999 } 1000 1001 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid, 1002 unsigned long head) 1003 { 1004 unsigned long err; 1005 1006 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head); 1007 if (unlikely(err)) 1008 return -EINVAL; 1009 1010 return 0; 1011 } 1012 1013 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid, 1014 unsigned long msi, int is_msi64) 1015 { 1016 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid, 1017 (is_msi64 ? 1018 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32))) 1019 return -ENXIO; 1020 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE)) 1021 return -ENXIO; 1022 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID)) 1023 return -ENXIO; 1024 return 0; 1025 } 1026 1027 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi) 1028 { 1029 unsigned long err, msiqid; 1030 1031 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid); 1032 if (err) 1033 return -ENXIO; 1034 1035 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID); 1036 1037 return 0; 1038 } 1039 1040 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm) 1041 { 1042 unsigned long q_size, alloc_size, pages, order; 1043 int i; 1044 1045 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); 1046 alloc_size = (pbm->msiq_num * q_size); 1047 order = get_order(alloc_size); 1048 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order); 1049 if (pages == 0UL) { 1050 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n", 1051 order); 1052 return -ENOMEM; 1053 } 1054 memset((char *)pages, 0, PAGE_SIZE << order); 1055 pbm->msi_queues = (void *) pages; 1056 1057 for (i = 0; i < pbm->msiq_num; i++) { 1058 unsigned long err, base = __pa(pages + (i * q_size)); 1059 unsigned long ret1, ret2; 1060 1061 err = pci_sun4v_msiq_conf(pbm->devhandle, 1062 pbm->msiq_first + i, 1063 base, pbm->msiq_ent_count); 1064 if (err) { 1065 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n", 1066 err); 1067 goto h_error; 1068 } 1069 1070 err = pci_sun4v_msiq_info(pbm->devhandle, 1071 pbm->msiq_first + i, 1072 &ret1, &ret2); 1073 if (err) { 1074 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n", 1075 err); 1076 goto h_error; 1077 } 1078 if (ret1 != base || ret2 != pbm->msiq_ent_count) { 1079 printk(KERN_ERR "MSI: Bogus qconf " 1080 "expected[%lx:%x] got[%lx:%lx]\n", 1081 base, pbm->msiq_ent_count, 1082 ret1, ret2); 1083 goto h_error; 1084 } 1085 } 1086 1087 return 0; 1088 1089 h_error: 1090 free_pages(pages, order); 1091 return -EINVAL; 1092 } 1093 1094 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm) 1095 { 1096 unsigned long q_size, alloc_size, pages, order; 1097 int i; 1098 1099 for (i = 0; i < pbm->msiq_num; i++) { 1100 unsigned long msiqid = pbm->msiq_first + i; 1101 1102 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0); 1103 } 1104 1105 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry); 1106 alloc_size = (pbm->msiq_num * q_size); 1107 order = get_order(alloc_size); 1108 1109 pages = (unsigned long) pbm->msi_queues; 1110 1111 free_pages(pages, order); 1112 1113 pbm->msi_queues = NULL; 1114 } 1115 1116 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm, 1117 unsigned long msiqid, 1118 unsigned long devino) 1119 { 1120 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino); 1121 1122 if (!irq) 1123 return -ENOMEM; 1124 1125 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID)) 1126 return -EINVAL; 1127 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE)) 1128 return -EINVAL; 1129 1130 return irq; 1131 } 1132 1133 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = { 1134 .get_head = pci_sun4v_get_head, 1135 .dequeue_msi = pci_sun4v_dequeue_msi, 1136 .set_head = pci_sun4v_set_head, 1137 .msi_setup = pci_sun4v_msi_setup, 1138 .msi_teardown = pci_sun4v_msi_teardown, 1139 .msiq_alloc = pci_sun4v_msiq_alloc, 1140 .msiq_free = pci_sun4v_msiq_free, 1141 .msiq_build_irq = pci_sun4v_msiq_build_irq, 1142 }; 1143 1144 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) 1145 { 1146 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops); 1147 } 1148 #else /* CONFIG_PCI_MSI */ 1149 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm) 1150 { 1151 } 1152 #endif /* !(CONFIG_PCI_MSI) */ 1153 1154 static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm, 1155 struct platform_device *op, u32 devhandle) 1156 { 1157 struct device_node *dp = op->dev.of_node; 1158 int err; 1159 1160 pbm->numa_node = of_node_to_nid(dp); 1161 1162 pbm->pci_ops = &sun4v_pci_ops; 1163 pbm->config_space_reg_bits = 12; 1164 1165 pbm->index = pci_num_pbms++; 1166 1167 pbm->op = op; 1168 1169 pbm->devhandle = devhandle; 1170 1171 pbm->name = dp->full_name; 1172 1173 printk("%s: SUN4V PCI Bus Module\n", pbm->name); 1174 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node); 1175 1176 pci_determine_mem_io_space(pbm); 1177 1178 pci_get_pbm_props(pbm); 1179 1180 err = pci_sun4v_iommu_init(pbm); 1181 if (err) 1182 return err; 1183 1184 pci_sun4v_msi_init(pbm); 1185 1186 pci_sun4v_scan_bus(pbm, &op->dev); 1187 1188 /* if atu_init fails its not complete failure. 1189 * we can still continue using legacy iommu. 1190 */ 1191 if (pbm->iommu->atu) { 1192 err = pci_sun4v_atu_init(pbm); 1193 if (err) { 1194 kfree(pbm->iommu->atu); 1195 pbm->iommu->atu = NULL; 1196 pr_err(PFX "ATU init failed, err=%d\n", err); 1197 } 1198 } 1199 1200 pbm->next = pci_pbm_root; 1201 pci_pbm_root = pbm; 1202 1203 return 0; 1204 } 1205 1206 static int pci_sun4v_probe(struct platform_device *op) 1207 { 1208 const struct linux_prom64_registers *regs; 1209 static int hvapi_negotiated = 0; 1210 struct pci_pbm_info *pbm; 1211 struct device_node *dp; 1212 struct iommu *iommu; 1213 struct atu *atu; 1214 u32 devhandle; 1215 int i, err = -ENODEV; 1216 static bool hv_atu = true; 1217 1218 dp = op->dev.of_node; 1219 1220 if (!hvapi_negotiated++) { 1221 for (i = 0; i < ARRAY_SIZE(vpci_versions); i++) { 1222 vpci_major = vpci_versions[i].major; 1223 vpci_minor = vpci_versions[i].minor; 1224 1225 err = sun4v_hvapi_register(HV_GRP_PCI, vpci_major, 1226 &vpci_minor); 1227 if (!err) 1228 break; 1229 } 1230 1231 if (err) { 1232 pr_err(PFX "Could not register hvapi, err=%d\n", err); 1233 return err; 1234 } 1235 pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n", 1236 vpci_major, vpci_minor); 1237 1238 err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor); 1239 if (err) { 1240 /* don't return an error if we fail to register the 1241 * ATU group, but ATU hcalls won't be available. 1242 */ 1243 hv_atu = false; 1244 pr_err(PFX "Could not register hvapi ATU err=%d\n", 1245 err); 1246 } else { 1247 pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n", 1248 vatu_major, vatu_minor); 1249 } 1250 1251 dma_ops = &sun4v_dma_ops; 1252 } 1253 1254 regs = of_get_property(dp, "reg", NULL); 1255 err = -ENODEV; 1256 if (!regs) { 1257 printk(KERN_ERR PFX "Could not find config registers\n"); 1258 goto out_err; 1259 } 1260 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff; 1261 1262 err = -ENOMEM; 1263 if (!iommu_batch_initialized) { 1264 for_each_possible_cpu(i) { 1265 unsigned long page = get_zeroed_page(GFP_KERNEL); 1266 1267 if (!page) 1268 goto out_err; 1269 1270 per_cpu(iommu_batch, i).pglist = (u64 *) page; 1271 } 1272 iommu_batch_initialized = 1; 1273 } 1274 1275 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 1276 if (!pbm) { 1277 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n"); 1278 goto out_err; 1279 } 1280 1281 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); 1282 if (!iommu) { 1283 printk(KERN_ERR PFX "Could not allocate pbm iommu\n"); 1284 goto out_free_controller; 1285 } 1286 1287 pbm->iommu = iommu; 1288 iommu->atu = NULL; 1289 if (hv_atu) { 1290 atu = kzalloc(sizeof(*atu), GFP_KERNEL); 1291 if (!atu) 1292 pr_err(PFX "Could not allocate atu\n"); 1293 else 1294 iommu->atu = atu; 1295 } 1296 1297 err = pci_sun4v_pbm_init(pbm, op, devhandle); 1298 if (err) 1299 goto out_free_iommu; 1300 1301 dev_set_drvdata(&op->dev, pbm); 1302 1303 return 0; 1304 1305 out_free_iommu: 1306 kfree(iommu->atu); 1307 kfree(pbm->iommu); 1308 1309 out_free_controller: 1310 kfree(pbm); 1311 1312 out_err: 1313 return err; 1314 } 1315 1316 static const struct of_device_id pci_sun4v_match[] = { 1317 { 1318 .name = "pci", 1319 .compatible = "SUNW,sun4v-pci", 1320 }, 1321 {}, 1322 }; 1323 1324 static struct platform_driver pci_sun4v_driver = { 1325 .driver = { 1326 .name = DRIVER_NAME, 1327 .of_match_table = pci_sun4v_match, 1328 }, 1329 .probe = pci_sun4v_probe, 1330 }; 1331 1332 static int __init pci_sun4v_init(void) 1333 { 1334 return platform_driver_register(&pci_sun4v_driver); 1335 } 1336 1337 subsys_initcall(pci_sun4v_init); 1338