xref: /openbmc/linux/arch/sparc/kernel/pci_sun4v.c (revision 5d0e4d78)
1 /* pci_sun4v.c: SUN4V specific PCI controller support.
2  *
3  * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/export.h>
16 #include <linux/log2.h>
17 #include <linux/of_device.h>
18 #include <linux/iommu-common.h>
19 
20 #include <asm/iommu.h>
21 #include <asm/irq.h>
22 #include <asm/hypervisor.h>
23 #include <asm/prom.h>
24 
25 #include "pci_impl.h"
26 #include "iommu_common.h"
27 #include "kernel.h"
28 
29 #include "pci_sun4v.h"
30 
31 #define DRIVER_NAME	"pci_sun4v"
32 #define PFX		DRIVER_NAME ": "
33 
34 static unsigned long vpci_major;
35 static unsigned long vpci_minor;
36 
37 struct vpci_version {
38 	unsigned long major;
39 	unsigned long minor;
40 };
41 
42 /* Ordered from largest major to lowest */
43 static struct vpci_version vpci_versions[] = {
44 	{ .major = 2, .minor = 0 },
45 	{ .major = 1, .minor = 1 },
46 };
47 
48 static unsigned long vatu_major = 1;
49 static unsigned long vatu_minor = 1;
50 
51 #define PGLIST_NENTS	(PAGE_SIZE / sizeof(u64))
52 
53 struct iommu_batch {
54 	struct device	*dev;		/* Device mapping is for.	*/
55 	unsigned long	prot;		/* IOMMU page protections	*/
56 	unsigned long	entry;		/* Index into IOTSB.		*/
57 	u64		*pglist;	/* List of physical pages	*/
58 	unsigned long	npages;		/* Number of pages in list.	*/
59 };
60 
61 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
62 static int iommu_batch_initialized;
63 
64 /* Interrupts must be disabled.  */
65 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
66 {
67 	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
68 
69 	p->dev		= dev;
70 	p->prot		= prot;
71 	p->entry	= entry;
72 	p->npages	= 0;
73 }
74 
75 /* Interrupts must be disabled.  */
76 static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
77 {
78 	struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
79 	u64 *pglist = p->pglist;
80 	u64 index_count;
81 	unsigned long devhandle = pbm->devhandle;
82 	unsigned long prot = p->prot;
83 	unsigned long entry = p->entry;
84 	unsigned long npages = p->npages;
85 	unsigned long iotsb_num;
86 	unsigned long ret;
87 	long num;
88 
89 	/* VPCI maj=1, min=[0,1] only supports read and write */
90 	if (vpci_major < 2)
91 		prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
92 
93 	while (npages != 0) {
94 		if (mask <= DMA_BIT_MASK(32)) {
95 			num = pci_sun4v_iommu_map(devhandle,
96 						  HV_PCI_TSBID(0, entry),
97 						  npages,
98 						  prot,
99 						  __pa(pglist));
100 			if (unlikely(num < 0)) {
101 				pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
102 						   __func__,
103 						   devhandle,
104 						   HV_PCI_TSBID(0, entry),
105 						   npages, prot, __pa(pglist),
106 						   num);
107 				return -1;
108 			}
109 		} else {
110 			index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
111 			iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
112 			ret = pci_sun4v_iotsb_map(devhandle,
113 						  iotsb_num,
114 						  index_count,
115 						  prot,
116 						  __pa(pglist),
117 						  &num);
118 			if (unlikely(ret != HV_EOK)) {
119 				pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
120 						   __func__,
121 						   devhandle, iotsb_num,
122 						   index_count, prot,
123 						   __pa(pglist), ret);
124 				return -1;
125 			}
126 		}
127 		entry += num;
128 		npages -= num;
129 		pglist += num;
130 	}
131 
132 	p->entry = entry;
133 	p->npages = 0;
134 
135 	return 0;
136 }
137 
138 static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
139 {
140 	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
141 
142 	if (p->entry + p->npages == entry)
143 		return;
144 	if (p->entry != ~0UL)
145 		iommu_batch_flush(p, mask);
146 	p->entry = entry;
147 }
148 
149 /* Interrupts must be disabled.  */
150 static inline long iommu_batch_add(u64 phys_page, u64 mask)
151 {
152 	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
153 
154 	BUG_ON(p->npages >= PGLIST_NENTS);
155 
156 	p->pglist[p->npages++] = phys_page;
157 	if (p->npages == PGLIST_NENTS)
158 		return iommu_batch_flush(p, mask);
159 
160 	return 0;
161 }
162 
163 /* Interrupts must be disabled.  */
164 static inline long iommu_batch_end(u64 mask)
165 {
166 	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
167 
168 	BUG_ON(p->npages >= PGLIST_NENTS);
169 
170 	return iommu_batch_flush(p, mask);
171 }
172 
173 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
174 				   dma_addr_t *dma_addrp, gfp_t gfp,
175 				   unsigned long attrs)
176 {
177 	u64 mask;
178 	unsigned long flags, order, first_page, npages, n;
179 	unsigned long prot = 0;
180 	struct iommu *iommu;
181 	struct atu *atu;
182 	struct iommu_map_table *tbl;
183 	struct page *page;
184 	void *ret;
185 	long entry;
186 	int nid;
187 
188 	size = IO_PAGE_ALIGN(size);
189 	order = get_order(size);
190 	if (unlikely(order >= MAX_ORDER))
191 		return NULL;
192 
193 	npages = size >> IO_PAGE_SHIFT;
194 
195 	if (attrs & DMA_ATTR_WEAK_ORDERING)
196 		prot = HV_PCI_MAP_ATTR_RELAXED_ORDER;
197 
198 	nid = dev->archdata.numa_node;
199 	page = alloc_pages_node(nid, gfp, order);
200 	if (unlikely(!page))
201 		return NULL;
202 
203 	first_page = (unsigned long) page_address(page);
204 	memset((char *)first_page, 0, PAGE_SIZE << order);
205 
206 	iommu = dev->archdata.iommu;
207 	atu = iommu->atu;
208 
209 	mask = dev->coherent_dma_mask;
210 	if (mask <= DMA_BIT_MASK(32))
211 		tbl = &iommu->tbl;
212 	else
213 		tbl = &atu->tbl;
214 
215 	entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
216 				      (unsigned long)(-1), 0);
217 
218 	if (unlikely(entry == IOMMU_ERROR_CODE))
219 		goto range_alloc_fail;
220 
221 	*dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
222 	ret = (void *) first_page;
223 	first_page = __pa(first_page);
224 
225 	local_irq_save(flags);
226 
227 	iommu_batch_start(dev,
228 			  (HV_PCI_MAP_ATTR_READ | prot |
229 			   HV_PCI_MAP_ATTR_WRITE),
230 			  entry);
231 
232 	for (n = 0; n < npages; n++) {
233 		long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
234 		if (unlikely(err < 0L))
235 			goto iommu_map_fail;
236 	}
237 
238 	if (unlikely(iommu_batch_end(mask) < 0L))
239 		goto iommu_map_fail;
240 
241 	local_irq_restore(flags);
242 
243 	return ret;
244 
245 iommu_map_fail:
246 	local_irq_restore(flags);
247 	iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
248 
249 range_alloc_fail:
250 	free_pages(first_page, order);
251 	return NULL;
252 }
253 
254 unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
255 				unsigned long iotsb_num,
256 				struct pci_bus *bus_dev)
257 {
258 	struct pci_dev *pdev;
259 	unsigned long err;
260 	unsigned int bus;
261 	unsigned int device;
262 	unsigned int fun;
263 
264 	list_for_each_entry(pdev, &bus_dev->devices, bus_list) {
265 		if (pdev->subordinate) {
266 			/* No need to bind pci bridge */
267 			dma_4v_iotsb_bind(devhandle, iotsb_num,
268 					  pdev->subordinate);
269 		} else {
270 			bus = bus_dev->number;
271 			device = PCI_SLOT(pdev->devfn);
272 			fun = PCI_FUNC(pdev->devfn);
273 			err = pci_sun4v_iotsb_bind(devhandle, iotsb_num,
274 						   HV_PCI_DEVICE_BUILD(bus,
275 								       device,
276 								       fun));
277 
278 			/* If bind fails for one device it is going to fail
279 			 * for rest of the devices because we are sharing
280 			 * IOTSB. So in case of failure simply return with
281 			 * error.
282 			 */
283 			if (err)
284 				return err;
285 		}
286 	}
287 
288 	return 0;
289 }
290 
291 static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
292 			       dma_addr_t dvma, unsigned long iotsb_num,
293 			       unsigned long entry, unsigned long npages)
294 {
295 	unsigned long num, flags;
296 	unsigned long ret;
297 
298 	local_irq_save(flags);
299 	do {
300 		if (dvma <= DMA_BIT_MASK(32)) {
301 			num = pci_sun4v_iommu_demap(devhandle,
302 						    HV_PCI_TSBID(0, entry),
303 						    npages);
304 		} else {
305 			ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
306 						    entry, npages, &num);
307 			if (unlikely(ret != HV_EOK)) {
308 				pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
309 						   ret);
310 			}
311 		}
312 		entry += num;
313 		npages -= num;
314 	} while (npages != 0);
315 	local_irq_restore(flags);
316 }
317 
318 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
319 				 dma_addr_t dvma, unsigned long attrs)
320 {
321 	struct pci_pbm_info *pbm;
322 	struct iommu *iommu;
323 	struct atu *atu;
324 	struct iommu_map_table *tbl;
325 	unsigned long order, npages, entry;
326 	unsigned long iotsb_num;
327 	u32 devhandle;
328 
329 	npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
330 	iommu = dev->archdata.iommu;
331 	pbm = dev->archdata.host_controller;
332 	atu = iommu->atu;
333 	devhandle = pbm->devhandle;
334 
335 	if (dvma <= DMA_BIT_MASK(32)) {
336 		tbl = &iommu->tbl;
337 		iotsb_num = 0; /* we don't care for legacy iommu */
338 	} else {
339 		tbl = &atu->tbl;
340 		iotsb_num = atu->iotsb->iotsb_num;
341 	}
342 	entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
343 	dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
344 	iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
345 	order = get_order(size);
346 	if (order < 10)
347 		free_pages((unsigned long)cpu, order);
348 }
349 
350 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
351 				  unsigned long offset, size_t sz,
352 				  enum dma_data_direction direction,
353 				  unsigned long attrs)
354 {
355 	struct iommu *iommu;
356 	struct atu *atu;
357 	struct iommu_map_table *tbl;
358 	u64 mask;
359 	unsigned long flags, npages, oaddr;
360 	unsigned long i, base_paddr;
361 	unsigned long prot;
362 	dma_addr_t bus_addr, ret;
363 	long entry;
364 
365 	iommu = dev->archdata.iommu;
366 	atu = iommu->atu;
367 
368 	if (unlikely(direction == DMA_NONE))
369 		goto bad;
370 
371 	oaddr = (unsigned long)(page_address(page) + offset);
372 	npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
373 	npages >>= IO_PAGE_SHIFT;
374 
375 	mask = *dev->dma_mask;
376 	if (mask <= DMA_BIT_MASK(32))
377 		tbl = &iommu->tbl;
378 	else
379 		tbl = &atu->tbl;
380 
381 	entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
382 				      (unsigned long)(-1), 0);
383 
384 	if (unlikely(entry == IOMMU_ERROR_CODE))
385 		goto bad;
386 
387 	bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
388 	ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
389 	base_paddr = __pa(oaddr & IO_PAGE_MASK);
390 	prot = HV_PCI_MAP_ATTR_READ;
391 	if (direction != DMA_TO_DEVICE)
392 		prot |= HV_PCI_MAP_ATTR_WRITE;
393 
394 	if (attrs & DMA_ATTR_WEAK_ORDERING)
395 		prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
396 
397 	local_irq_save(flags);
398 
399 	iommu_batch_start(dev, prot, entry);
400 
401 	for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
402 		long err = iommu_batch_add(base_paddr, mask);
403 		if (unlikely(err < 0L))
404 			goto iommu_map_fail;
405 	}
406 	if (unlikely(iommu_batch_end(mask) < 0L))
407 		goto iommu_map_fail;
408 
409 	local_irq_restore(flags);
410 
411 	return ret;
412 
413 bad:
414 	if (printk_ratelimit())
415 		WARN_ON(1);
416 	return SPARC_MAPPING_ERROR;
417 
418 iommu_map_fail:
419 	local_irq_restore(flags);
420 	iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
421 	return SPARC_MAPPING_ERROR;
422 }
423 
424 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
425 			      size_t sz, enum dma_data_direction direction,
426 			      unsigned long attrs)
427 {
428 	struct pci_pbm_info *pbm;
429 	struct iommu *iommu;
430 	struct atu *atu;
431 	struct iommu_map_table *tbl;
432 	unsigned long npages;
433 	unsigned long iotsb_num;
434 	long entry;
435 	u32 devhandle;
436 
437 	if (unlikely(direction == DMA_NONE)) {
438 		if (printk_ratelimit())
439 			WARN_ON(1);
440 		return;
441 	}
442 
443 	iommu = dev->archdata.iommu;
444 	pbm = dev->archdata.host_controller;
445 	atu = iommu->atu;
446 	devhandle = pbm->devhandle;
447 
448 	npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
449 	npages >>= IO_PAGE_SHIFT;
450 	bus_addr &= IO_PAGE_MASK;
451 
452 	if (bus_addr <= DMA_BIT_MASK(32)) {
453 		iotsb_num = 0; /* we don't care for legacy iommu */
454 		tbl = &iommu->tbl;
455 	} else {
456 		iotsb_num = atu->iotsb->iotsb_num;
457 		tbl = &atu->tbl;
458 	}
459 	entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
460 	dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
461 	iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
462 }
463 
464 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
465 			 int nelems, enum dma_data_direction direction,
466 			 unsigned long attrs)
467 {
468 	struct scatterlist *s, *outs, *segstart;
469 	unsigned long flags, handle, prot;
470 	dma_addr_t dma_next = 0, dma_addr;
471 	unsigned int max_seg_size;
472 	unsigned long seg_boundary_size;
473 	int outcount, incount, i;
474 	struct iommu *iommu;
475 	struct atu *atu;
476 	struct iommu_map_table *tbl;
477 	u64 mask;
478 	unsigned long base_shift;
479 	long err;
480 
481 	BUG_ON(direction == DMA_NONE);
482 
483 	iommu = dev->archdata.iommu;
484 	if (nelems == 0 || !iommu)
485 		return 0;
486 	atu = iommu->atu;
487 
488 	prot = HV_PCI_MAP_ATTR_READ;
489 	if (direction != DMA_TO_DEVICE)
490 		prot |= HV_PCI_MAP_ATTR_WRITE;
491 
492 	if (attrs & DMA_ATTR_WEAK_ORDERING)
493 		prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
494 
495 	outs = s = segstart = &sglist[0];
496 	outcount = 1;
497 	incount = nelems;
498 	handle = 0;
499 
500 	/* Init first segment length for backout at failure */
501 	outs->dma_length = 0;
502 
503 	local_irq_save(flags);
504 
505 	iommu_batch_start(dev, prot, ~0UL);
506 
507 	max_seg_size = dma_get_max_seg_size(dev);
508 	seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
509 				  IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
510 
511 	mask = *dev->dma_mask;
512 	if (mask <= DMA_BIT_MASK(32))
513 		tbl = &iommu->tbl;
514 	else
515 		tbl = &atu->tbl;
516 
517 	base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
518 
519 	for_each_sg(sglist, s, nelems, i) {
520 		unsigned long paddr, npages, entry, out_entry = 0, slen;
521 
522 		slen = s->length;
523 		/* Sanity check */
524 		if (slen == 0) {
525 			dma_next = 0;
526 			continue;
527 		}
528 		/* Allocate iommu entries for that segment */
529 		paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
530 		npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
531 		entry = iommu_tbl_range_alloc(dev, tbl, npages,
532 					      &handle, (unsigned long)(-1), 0);
533 
534 		/* Handle failure */
535 		if (unlikely(entry == IOMMU_ERROR_CODE)) {
536 			pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
537 					   tbl, paddr, npages);
538 			goto iommu_map_failed;
539 		}
540 
541 		iommu_batch_new_entry(entry, mask);
542 
543 		/* Convert entry to a dma_addr_t */
544 		dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
545 		dma_addr |= (s->offset & ~IO_PAGE_MASK);
546 
547 		/* Insert into HW table */
548 		paddr &= IO_PAGE_MASK;
549 		while (npages--) {
550 			err = iommu_batch_add(paddr, mask);
551 			if (unlikely(err < 0L))
552 				goto iommu_map_failed;
553 			paddr += IO_PAGE_SIZE;
554 		}
555 
556 		/* If we are in an open segment, try merging */
557 		if (segstart != s) {
558 			/* We cannot merge if:
559 			 * - allocated dma_addr isn't contiguous to previous allocation
560 			 */
561 			if ((dma_addr != dma_next) ||
562 			    (outs->dma_length + s->length > max_seg_size) ||
563 			    (is_span_boundary(out_entry, base_shift,
564 					      seg_boundary_size, outs, s))) {
565 				/* Can't merge: create a new segment */
566 				segstart = s;
567 				outcount++;
568 				outs = sg_next(outs);
569 			} else {
570 				outs->dma_length += s->length;
571 			}
572 		}
573 
574 		if (segstart == s) {
575 			/* This is a new segment, fill entries */
576 			outs->dma_address = dma_addr;
577 			outs->dma_length = slen;
578 			out_entry = entry;
579 		}
580 
581 		/* Calculate next page pointer for contiguous check */
582 		dma_next = dma_addr + slen;
583 	}
584 
585 	err = iommu_batch_end(mask);
586 
587 	if (unlikely(err < 0L))
588 		goto iommu_map_failed;
589 
590 	local_irq_restore(flags);
591 
592 	if (outcount < incount) {
593 		outs = sg_next(outs);
594 		outs->dma_address = SPARC_MAPPING_ERROR;
595 		outs->dma_length = 0;
596 	}
597 
598 	return outcount;
599 
600 iommu_map_failed:
601 	for_each_sg(sglist, s, nelems, i) {
602 		if (s->dma_length != 0) {
603 			unsigned long vaddr, npages;
604 
605 			vaddr = s->dma_address & IO_PAGE_MASK;
606 			npages = iommu_num_pages(s->dma_address, s->dma_length,
607 						 IO_PAGE_SIZE);
608 			iommu_tbl_range_free(tbl, vaddr, npages,
609 					     IOMMU_ERROR_CODE);
610 			/* XXX demap? XXX */
611 			s->dma_address = SPARC_MAPPING_ERROR;
612 			s->dma_length = 0;
613 		}
614 		if (s == outs)
615 			break;
616 	}
617 	local_irq_restore(flags);
618 
619 	return 0;
620 }
621 
622 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
623 			    int nelems, enum dma_data_direction direction,
624 			    unsigned long attrs)
625 {
626 	struct pci_pbm_info *pbm;
627 	struct scatterlist *sg;
628 	struct iommu *iommu;
629 	struct atu *atu;
630 	unsigned long flags, entry;
631 	unsigned long iotsb_num;
632 	u32 devhandle;
633 
634 	BUG_ON(direction == DMA_NONE);
635 
636 	iommu = dev->archdata.iommu;
637 	pbm = dev->archdata.host_controller;
638 	atu = iommu->atu;
639 	devhandle = pbm->devhandle;
640 
641 	local_irq_save(flags);
642 
643 	sg = sglist;
644 	while (nelems--) {
645 		dma_addr_t dma_handle = sg->dma_address;
646 		unsigned int len = sg->dma_length;
647 		unsigned long npages;
648 		struct iommu_map_table *tbl;
649 		unsigned long shift = IO_PAGE_SHIFT;
650 
651 		if (!len)
652 			break;
653 		npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
654 
655 		if (dma_handle <= DMA_BIT_MASK(32)) {
656 			iotsb_num = 0; /* we don't care for legacy iommu */
657 			tbl = &iommu->tbl;
658 		} else {
659 			iotsb_num = atu->iotsb->iotsb_num;
660 			tbl = &atu->tbl;
661 		}
662 		entry = ((dma_handle - tbl->table_map_base) >> shift);
663 		dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
664 				   entry, npages);
665 		iommu_tbl_range_free(tbl, dma_handle, npages,
666 				     IOMMU_ERROR_CODE);
667 		sg = sg_next(sg);
668 	}
669 
670 	local_irq_restore(flags);
671 }
672 
673 static int dma_4v_supported(struct device *dev, u64 device_mask)
674 {
675 	struct iommu *iommu = dev->archdata.iommu;
676 	u64 dma_addr_mask = iommu->dma_addr_mask;
677 
678 	if (device_mask > DMA_BIT_MASK(32)) {
679 		if (iommu->atu)
680 			dma_addr_mask = iommu->atu->dma_addr_mask;
681 		else
682 			return 0;
683 	}
684 
685 	if ((device_mask & dma_addr_mask) == dma_addr_mask)
686 		return 1;
687 	return pci64_dma_supported(to_pci_dev(dev), device_mask);
688 }
689 
690 static int dma_4v_mapping_error(struct device *dev, dma_addr_t dma_addr)
691 {
692 	return dma_addr == SPARC_MAPPING_ERROR;
693 }
694 
695 static const struct dma_map_ops sun4v_dma_ops = {
696 	.alloc				= dma_4v_alloc_coherent,
697 	.free				= dma_4v_free_coherent,
698 	.map_page			= dma_4v_map_page,
699 	.unmap_page			= dma_4v_unmap_page,
700 	.map_sg				= dma_4v_map_sg,
701 	.unmap_sg			= dma_4v_unmap_sg,
702 	.dma_supported			= dma_4v_supported,
703 	.mapping_error			= dma_4v_mapping_error,
704 };
705 
706 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
707 {
708 	struct property *prop;
709 	struct device_node *dp;
710 
711 	dp = pbm->op->dev.of_node;
712 	prop = of_find_property(dp, "66mhz-capable", NULL);
713 	pbm->is_66mhz_capable = (prop != NULL);
714 	pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
715 
716 	/* XXX register error interrupt handlers XXX */
717 }
718 
719 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
720 					    struct iommu_map_table *iommu)
721 {
722 	struct iommu_pool *pool;
723 	unsigned long i, pool_nr, cnt = 0;
724 	u32 devhandle;
725 
726 	devhandle = pbm->devhandle;
727 	for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
728 		pool = &(iommu->pools[pool_nr]);
729 		for (i = pool->start; i <= pool->end; i++) {
730 			unsigned long ret, io_attrs, ra;
731 
732 			ret = pci_sun4v_iommu_getmap(devhandle,
733 						     HV_PCI_TSBID(0, i),
734 						     &io_attrs, &ra);
735 			if (ret == HV_EOK) {
736 				if (page_in_phys_avail(ra)) {
737 					pci_sun4v_iommu_demap(devhandle,
738 							      HV_PCI_TSBID(0,
739 							      i), 1);
740 				} else {
741 					cnt++;
742 					__set_bit(i, iommu->map);
743 				}
744 			}
745 		}
746 	}
747 	return cnt;
748 }
749 
750 static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm)
751 {
752 	struct atu *atu = pbm->iommu->atu;
753 	struct atu_iotsb *iotsb;
754 	void *table;
755 	u64 table_size;
756 	u64 iotsb_num;
757 	unsigned long order;
758 	unsigned long err;
759 
760 	iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL);
761 	if (!iotsb) {
762 		err = -ENOMEM;
763 		goto out_err;
764 	}
765 	atu->iotsb = iotsb;
766 
767 	/* calculate size of IOTSB */
768 	table_size = (atu->size / IO_PAGE_SIZE) * 8;
769 	order = get_order(table_size);
770 	table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
771 	if (!table) {
772 		err = -ENOMEM;
773 		goto table_failed;
774 	}
775 	iotsb->table = table;
776 	iotsb->ra = __pa(table);
777 	iotsb->dvma_size = atu->size;
778 	iotsb->dvma_base = atu->base;
779 	iotsb->table_size = table_size;
780 	iotsb->page_size = IO_PAGE_SIZE;
781 
782 	/* configure and register IOTSB with HV */
783 	err = pci_sun4v_iotsb_conf(pbm->devhandle,
784 				   iotsb->ra,
785 				   iotsb->table_size,
786 				   iotsb->page_size,
787 				   iotsb->dvma_base,
788 				   &iotsb_num);
789 	if (err) {
790 		pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err);
791 		goto iotsb_conf_failed;
792 	}
793 	iotsb->iotsb_num = iotsb_num;
794 
795 	err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus);
796 	if (err) {
797 		pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err);
798 		goto iotsb_conf_failed;
799 	}
800 
801 	return 0;
802 
803 iotsb_conf_failed:
804 	free_pages((unsigned long)table, order);
805 table_failed:
806 	kfree(iotsb);
807 out_err:
808 	return err;
809 }
810 
811 static int pci_sun4v_atu_init(struct pci_pbm_info *pbm)
812 {
813 	struct atu *atu = pbm->iommu->atu;
814 	unsigned long err;
815 	const u64 *ranges;
816 	u64 map_size, num_iotte;
817 	u64 dma_mask;
818 	const u32 *page_size;
819 	int len;
820 
821 	ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges",
822 				 &len);
823 	if (!ranges) {
824 		pr_err(PFX "No iommu-address-ranges\n");
825 		return -EINVAL;
826 	}
827 
828 	page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes",
829 				    NULL);
830 	if (!page_size) {
831 		pr_err(PFX "No iommu-pagesizes\n");
832 		return -EINVAL;
833 	}
834 
835 	/* There are 4 iommu-address-ranges supported. Each range is pair of
836 	 * {base, size}. The ranges[0] and ranges[1] are 32bit address space
837 	 * while ranges[2] and ranges[3] are 64bit space.  We want to use 64bit
838 	 * address ranges to support 64bit addressing. Because 'size' for
839 	 * address ranges[2] and ranges[3] are same we can select either of
840 	 * ranges[2] or ranges[3] for mapping. However due to 'size' is too
841 	 * large for OS to allocate IOTSB we are using fix size 32G
842 	 * (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices
843 	 * to share.
844 	 */
845 	atu->ranges = (struct atu_ranges *)ranges;
846 	atu->base = atu->ranges[3].base;
847 	atu->size = ATU_64_SPACE_SIZE;
848 
849 	/* Create IOTSB */
850 	err = pci_sun4v_atu_alloc_iotsb(pbm);
851 	if (err) {
852 		pr_err(PFX "Error creating ATU IOTSB\n");
853 		return err;
854 	}
855 
856 	/* Create ATU iommu map.
857 	 * One bit represents one iotte in IOTSB table.
858 	 */
859 	dma_mask = (roundup_pow_of_two(atu->size) - 1UL);
860 	num_iotte = atu->size / IO_PAGE_SIZE;
861 	map_size = num_iotte / 8;
862 	atu->tbl.table_map_base = atu->base;
863 	atu->dma_addr_mask = dma_mask;
864 	atu->tbl.map = kzalloc(map_size, GFP_KERNEL);
865 	if (!atu->tbl.map)
866 		return -ENOMEM;
867 
868 	iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT,
869 			    NULL, false /* no large_pool */,
870 			    0 /* default npools */,
871 			    false /* want span boundary checking */);
872 
873 	return 0;
874 }
875 
876 static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
877 {
878 	static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
879 	struct iommu *iommu = pbm->iommu;
880 	unsigned long num_tsb_entries, sz;
881 	u32 dma_mask, dma_offset;
882 	const u32 *vdma;
883 
884 	vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
885 	if (!vdma)
886 		vdma = vdma_default;
887 
888 	if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
889 		printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
890 		       vdma[0], vdma[1]);
891 		return -EINVAL;
892 	}
893 
894 	dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
895 	num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
896 
897 	dma_offset = vdma[0];
898 
899 	/* Setup initial software IOMMU state. */
900 	spin_lock_init(&iommu->lock);
901 	iommu->ctx_lowest_free = 1;
902 	iommu->tbl.table_map_base = dma_offset;
903 	iommu->dma_addr_mask = dma_mask;
904 
905 	/* Allocate and initialize the free area map.  */
906 	sz = (num_tsb_entries + 7) / 8;
907 	sz = (sz + 7UL) & ~7UL;
908 	iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
909 	if (!iommu->tbl.map) {
910 		printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
911 		return -ENOMEM;
912 	}
913 	iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
914 			    NULL, false /* no large_pool */,
915 			    0 /* default npools */,
916 			    false /* want span boundary checking */);
917 	sz = probe_existing_entries(pbm, &iommu->tbl);
918 	if (sz)
919 		printk("%s: Imported %lu TSB entries from OBP\n",
920 		       pbm->name, sz);
921 
922 	return 0;
923 }
924 
925 #ifdef CONFIG_PCI_MSI
926 struct pci_sun4v_msiq_entry {
927 	u64		version_type;
928 #define MSIQ_VERSION_MASK		0xffffffff00000000UL
929 #define MSIQ_VERSION_SHIFT		32
930 #define MSIQ_TYPE_MASK			0x00000000000000ffUL
931 #define MSIQ_TYPE_SHIFT			0
932 #define MSIQ_TYPE_NONE			0x00
933 #define MSIQ_TYPE_MSG			0x01
934 #define MSIQ_TYPE_MSI32			0x02
935 #define MSIQ_TYPE_MSI64			0x03
936 #define MSIQ_TYPE_INTX			0x08
937 #define MSIQ_TYPE_NONE2			0xff
938 
939 	u64		intx_sysino;
940 	u64		reserved1;
941 	u64		stick;
942 	u64		req_id;  /* bus/device/func */
943 #define MSIQ_REQID_BUS_MASK		0xff00UL
944 #define MSIQ_REQID_BUS_SHIFT		8
945 #define MSIQ_REQID_DEVICE_MASK		0x00f8UL
946 #define MSIQ_REQID_DEVICE_SHIFT		3
947 #define MSIQ_REQID_FUNC_MASK		0x0007UL
948 #define MSIQ_REQID_FUNC_SHIFT		0
949 
950 	u64		msi_address;
951 
952 	/* The format of this value is message type dependent.
953 	 * For MSI bits 15:0 are the data from the MSI packet.
954 	 * For MSI-X bits 31:0 are the data from the MSI packet.
955 	 * For MSG, the message code and message routing code where:
956 	 * 	bits 39:32 is the bus/device/fn of the msg target-id
957 	 *	bits 18:16 is the message routing code
958 	 *	bits 7:0 is the message code
959 	 * For INTx the low order 2-bits are:
960 	 *	00 - INTA
961 	 *	01 - INTB
962 	 *	10 - INTC
963 	 *	11 - INTD
964 	 */
965 	u64		msi_data;
966 
967 	u64		reserved2;
968 };
969 
970 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
971 			      unsigned long *head)
972 {
973 	unsigned long err, limit;
974 
975 	err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
976 	if (unlikely(err))
977 		return -ENXIO;
978 
979 	limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
980 	if (unlikely(*head >= limit))
981 		return -EFBIG;
982 
983 	return 0;
984 }
985 
986 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
987 				 unsigned long msiqid, unsigned long *head,
988 				 unsigned long *msi)
989 {
990 	struct pci_sun4v_msiq_entry *ep;
991 	unsigned long err, type;
992 
993 	/* Note: void pointer arithmetic, 'head' is a byte offset  */
994 	ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
995 				 (pbm->msiq_ent_count *
996 				  sizeof(struct pci_sun4v_msiq_entry))) +
997 	      *head);
998 
999 	if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
1000 		return 0;
1001 
1002 	type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
1003 	if (unlikely(type != MSIQ_TYPE_MSI32 &&
1004 		     type != MSIQ_TYPE_MSI64))
1005 		return -EINVAL;
1006 
1007 	*msi = ep->msi_data;
1008 
1009 	err = pci_sun4v_msi_setstate(pbm->devhandle,
1010 				     ep->msi_data /* msi_num */,
1011 				     HV_MSISTATE_IDLE);
1012 	if (unlikely(err))
1013 		return -ENXIO;
1014 
1015 	/* Clear the entry.  */
1016 	ep->version_type &= ~MSIQ_TYPE_MASK;
1017 
1018 	(*head) += sizeof(struct pci_sun4v_msiq_entry);
1019 	if (*head >=
1020 	    (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
1021 		*head = 0;
1022 
1023 	return 1;
1024 }
1025 
1026 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
1027 			      unsigned long head)
1028 {
1029 	unsigned long err;
1030 
1031 	err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
1032 	if (unlikely(err))
1033 		return -EINVAL;
1034 
1035 	return 0;
1036 }
1037 
1038 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
1039 			       unsigned long msi, int is_msi64)
1040 {
1041 	if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
1042 				  (is_msi64 ?
1043 				   HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1044 		return -ENXIO;
1045 	if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
1046 		return -ENXIO;
1047 	if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
1048 		return -ENXIO;
1049 	return 0;
1050 }
1051 
1052 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
1053 {
1054 	unsigned long err, msiqid;
1055 
1056 	err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
1057 	if (err)
1058 		return -ENXIO;
1059 
1060 	pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
1061 
1062 	return 0;
1063 }
1064 
1065 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
1066 {
1067 	unsigned long q_size, alloc_size, pages, order;
1068 	int i;
1069 
1070 	q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1071 	alloc_size = (pbm->msiq_num * q_size);
1072 	order = get_order(alloc_size);
1073 	pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1074 	if (pages == 0UL) {
1075 		printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1076 		       order);
1077 		return -ENOMEM;
1078 	}
1079 	memset((char *)pages, 0, PAGE_SIZE << order);
1080 	pbm->msi_queues = (void *) pages;
1081 
1082 	for (i = 0; i < pbm->msiq_num; i++) {
1083 		unsigned long err, base = __pa(pages + (i * q_size));
1084 		unsigned long ret1, ret2;
1085 
1086 		err = pci_sun4v_msiq_conf(pbm->devhandle,
1087 					  pbm->msiq_first + i,
1088 					  base, pbm->msiq_ent_count);
1089 		if (err) {
1090 			printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1091 			       err);
1092 			goto h_error;
1093 		}
1094 
1095 		err = pci_sun4v_msiq_info(pbm->devhandle,
1096 					  pbm->msiq_first + i,
1097 					  &ret1, &ret2);
1098 		if (err) {
1099 			printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1100 			       err);
1101 			goto h_error;
1102 		}
1103 		if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1104 			printk(KERN_ERR "MSI: Bogus qconf "
1105 			       "expected[%lx:%x] got[%lx:%lx]\n",
1106 			       base, pbm->msiq_ent_count,
1107 			       ret1, ret2);
1108 			goto h_error;
1109 		}
1110 	}
1111 
1112 	return 0;
1113 
1114 h_error:
1115 	free_pages(pages, order);
1116 	return -EINVAL;
1117 }
1118 
1119 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
1120 {
1121 	unsigned long q_size, alloc_size, pages, order;
1122 	int i;
1123 
1124 	for (i = 0; i < pbm->msiq_num; i++) {
1125 		unsigned long msiqid = pbm->msiq_first + i;
1126 
1127 		(void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
1128 	}
1129 
1130 	q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1131 	alloc_size = (pbm->msiq_num * q_size);
1132 	order = get_order(alloc_size);
1133 
1134 	pages = (unsigned long) pbm->msi_queues;
1135 
1136 	free_pages(pages, order);
1137 
1138 	pbm->msi_queues = NULL;
1139 }
1140 
1141 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
1142 				    unsigned long msiqid,
1143 				    unsigned long devino)
1144 {
1145 	unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
1146 
1147 	if (!irq)
1148 		return -ENOMEM;
1149 
1150 	if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1151 		return -EINVAL;
1152 	if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1153 		return -EINVAL;
1154 
1155 	return irq;
1156 }
1157 
1158 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
1159 	.get_head	=	pci_sun4v_get_head,
1160 	.dequeue_msi	=	pci_sun4v_dequeue_msi,
1161 	.set_head	=	pci_sun4v_set_head,
1162 	.msi_setup	=	pci_sun4v_msi_setup,
1163 	.msi_teardown	=	pci_sun4v_msi_teardown,
1164 	.msiq_alloc	=	pci_sun4v_msiq_alloc,
1165 	.msiq_free	=	pci_sun4v_msiq_free,
1166 	.msiq_build_irq	=	pci_sun4v_msiq_build_irq,
1167 };
1168 
1169 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1170 {
1171 	sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
1172 }
1173 #else /* CONFIG_PCI_MSI */
1174 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1175 {
1176 }
1177 #endif /* !(CONFIG_PCI_MSI) */
1178 
1179 static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
1180 			      struct platform_device *op, u32 devhandle)
1181 {
1182 	struct device_node *dp = op->dev.of_node;
1183 	int err;
1184 
1185 	pbm->numa_node = of_node_to_nid(dp);
1186 
1187 	pbm->pci_ops = &sun4v_pci_ops;
1188 	pbm->config_space_reg_bits = 12;
1189 
1190 	pbm->index = pci_num_pbms++;
1191 
1192 	pbm->op = op;
1193 
1194 	pbm->devhandle = devhandle;
1195 
1196 	pbm->name = dp->full_name;
1197 
1198 	printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1199 	printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
1200 
1201 	pci_determine_mem_io_space(pbm);
1202 
1203 	pci_get_pbm_props(pbm);
1204 
1205 	err = pci_sun4v_iommu_init(pbm);
1206 	if (err)
1207 		return err;
1208 
1209 	pci_sun4v_msi_init(pbm);
1210 
1211 	pci_sun4v_scan_bus(pbm, &op->dev);
1212 
1213 	/* if atu_init fails its not complete failure.
1214 	 * we can still continue using legacy iommu.
1215 	 */
1216 	if (pbm->iommu->atu) {
1217 		err = pci_sun4v_atu_init(pbm);
1218 		if (err) {
1219 			kfree(pbm->iommu->atu);
1220 			pbm->iommu->atu = NULL;
1221 			pr_err(PFX "ATU init failed, err=%d\n", err);
1222 		}
1223 	}
1224 
1225 	pbm->next = pci_pbm_root;
1226 	pci_pbm_root = pbm;
1227 
1228 	return 0;
1229 }
1230 
1231 static int pci_sun4v_probe(struct platform_device *op)
1232 {
1233 	const struct linux_prom64_registers *regs;
1234 	static int hvapi_negotiated = 0;
1235 	struct pci_pbm_info *pbm;
1236 	struct device_node *dp;
1237 	struct iommu *iommu;
1238 	struct atu *atu;
1239 	u32 devhandle;
1240 	int i, err = -ENODEV;
1241 	static bool hv_atu = true;
1242 
1243 	dp = op->dev.of_node;
1244 
1245 	if (!hvapi_negotiated++) {
1246 		for (i = 0; i < ARRAY_SIZE(vpci_versions); i++) {
1247 			vpci_major = vpci_versions[i].major;
1248 			vpci_minor = vpci_versions[i].minor;
1249 
1250 			err = sun4v_hvapi_register(HV_GRP_PCI, vpci_major,
1251 						   &vpci_minor);
1252 			if (!err)
1253 				break;
1254 		}
1255 
1256 		if (err) {
1257 			pr_err(PFX "Could not register hvapi, err=%d\n", err);
1258 			return err;
1259 		}
1260 		pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",
1261 			vpci_major, vpci_minor);
1262 
1263 		err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor);
1264 		if (err) {
1265 			/* don't return an error if we fail to register the
1266 			 * ATU group, but ATU hcalls won't be available.
1267 			 */
1268 			hv_atu = false;
1269 			pr_err(PFX "Could not register hvapi ATU err=%d\n",
1270 			       err);
1271 		} else {
1272 			pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
1273 				vatu_major, vatu_minor);
1274 		}
1275 
1276 		dma_ops = &sun4v_dma_ops;
1277 	}
1278 
1279 	regs = of_get_property(dp, "reg", NULL);
1280 	err = -ENODEV;
1281 	if (!regs) {
1282 		printk(KERN_ERR PFX "Could not find config registers\n");
1283 		goto out_err;
1284 	}
1285 	devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1286 
1287 	err = -ENOMEM;
1288 	if (!iommu_batch_initialized) {
1289 		for_each_possible_cpu(i) {
1290 			unsigned long page = get_zeroed_page(GFP_KERNEL);
1291 
1292 			if (!page)
1293 				goto out_err;
1294 
1295 			per_cpu(iommu_batch, i).pglist = (u64 *) page;
1296 		}
1297 		iommu_batch_initialized = 1;
1298 	}
1299 
1300 	pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1301 	if (!pbm) {
1302 		printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
1303 		goto out_err;
1304 	}
1305 
1306 	iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1307 	if (!iommu) {
1308 		printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
1309 		goto out_free_controller;
1310 	}
1311 
1312 	pbm->iommu = iommu;
1313 	iommu->atu = NULL;
1314 	if (hv_atu) {
1315 		atu = kzalloc(sizeof(*atu), GFP_KERNEL);
1316 		if (!atu)
1317 			pr_err(PFX "Could not allocate atu\n");
1318 		else
1319 			iommu->atu = atu;
1320 	}
1321 
1322 	err = pci_sun4v_pbm_init(pbm, op, devhandle);
1323 	if (err)
1324 		goto out_free_iommu;
1325 
1326 	dev_set_drvdata(&op->dev, pbm);
1327 
1328 	return 0;
1329 
1330 out_free_iommu:
1331 	kfree(iommu->atu);
1332 	kfree(pbm->iommu);
1333 
1334 out_free_controller:
1335 	kfree(pbm);
1336 
1337 out_err:
1338 	return err;
1339 }
1340 
1341 static const struct of_device_id pci_sun4v_match[] = {
1342 	{
1343 		.name = "pci",
1344 		.compatible = "SUNW,sun4v-pci",
1345 	},
1346 	{},
1347 };
1348 
1349 static struct platform_driver pci_sun4v_driver = {
1350 	.driver = {
1351 		.name = DRIVER_NAME,
1352 		.of_match_table = pci_sun4v_match,
1353 	},
1354 	.probe		= pci_sun4v_probe,
1355 };
1356 
1357 static int __init pci_sun4v_init(void)
1358 {
1359 	return platform_driver_register(&pci_sun4v_driver);
1360 }
1361 
1362 subsys_initcall(pci_sun4v_init);
1363