1 // SPDX-License-Identifier: GPL-2.0 2 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. 3 * 4 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net) 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/export.h> 13 #include <linux/interrupt.h> 14 #include <linux/of_device.h> 15 #include <linux/numa.h> 16 17 #include <asm/iommu.h> 18 #include <asm/irq.h> 19 #include <asm/pstate.h> 20 #include <asm/prom.h> 21 #include <asm/upa.h> 22 23 #include "pci_impl.h" 24 #include "iommu_common.h" 25 26 #define DRIVER_NAME "schizo" 27 #define PFX DRIVER_NAME ": " 28 29 /* This is a convention that at least Excalibur and Merlin 30 * follow. I suppose the SCHIZO used in Starcat and friends 31 * will do similar. 32 * 33 * The only way I could see this changing is if the newlink 34 * block requires more space in Schizo's address space than 35 * they predicted, thus requiring an address space reorg when 36 * the newer Schizo is taped out. 37 */ 38 39 /* Streaming buffer control register. */ 40 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ 41 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ 42 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ 43 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 44 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ 45 46 /* IOMMU control register. */ 47 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ 48 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ 49 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ 50 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ 51 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ 52 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 53 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ 54 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ 55 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ 56 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ 57 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ 58 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ 59 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ 60 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ 61 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ 62 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ 63 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ 64 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 65 66 /* Schizo config space address format is nearly identical to 67 * that of PSYCHO: 68 * 69 * 32 24 23 16 15 11 10 8 7 2 1 0 70 * --------------------------------------------------------- 71 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 | 72 * --------------------------------------------------------- 73 */ 74 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space) 75 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ 76 (((unsigned long)(BUS) << 16) | \ 77 ((unsigned long)(DEVFN) << 8) | \ 78 ((unsigned long)(REG))) 79 80 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm, 81 unsigned char bus, 82 unsigned int devfn, 83 int where) 84 { 85 if (!pbm) 86 return NULL; 87 bus -= pbm->pci_first_busno; 88 return (void *) 89 (SCHIZO_CONFIG_BASE(pbm) | 90 SCHIZO_CONFIG_ENCODE(bus, devfn, where)); 91 } 92 93 /* SCHIZO error handling support. */ 94 enum schizo_error_type { 95 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR 96 }; 97 98 static DEFINE_SPINLOCK(stc_buf_lock); 99 static unsigned long stc_error_buf[128]; 100 static unsigned long stc_tag_buf[16]; 101 static unsigned long stc_line_buf[16]; 102 103 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */ 104 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */ 105 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */ 106 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ 107 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */ 108 109 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ 110 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ 111 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ 112 113 #define SCHIZO_STCERR_WRITE 0x2UL 114 #define SCHIZO_STCERR_READ 0x1UL 115 116 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL 117 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL 118 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL 119 #define SCHIZO_STCTAG_READ 0x4000000000000000UL 120 121 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL 122 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL 123 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL 124 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL 125 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL 126 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL 127 128 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm, 129 enum schizo_error_type type) 130 { 131 struct strbuf *strbuf = &pbm->stc; 132 unsigned long regbase = pbm->pbm_regs; 133 unsigned long err_base, tag_base, line_base; 134 u64 control; 135 int i; 136 137 err_base = regbase + SCHIZO_STC_ERR; 138 tag_base = regbase + SCHIZO_STC_TAG; 139 line_base = regbase + SCHIZO_STC_LINE; 140 141 spin_lock(&stc_buf_lock); 142 143 /* This is __REALLY__ dangerous. When we put the 144 * streaming buffer into diagnostic mode to probe 145 * it's tags and error status, we _must_ clear all 146 * of the line tag valid bits before re-enabling 147 * the streaming buffer. If any dirty data lives 148 * in the STC when we do this, we will end up 149 * invalidating it before it has a chance to reach 150 * main memory. 151 */ 152 control = upa_readq(strbuf->strbuf_control); 153 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), 154 strbuf->strbuf_control); 155 for (i = 0; i < 128; i++) { 156 unsigned long val; 157 158 val = upa_readq(err_base + (i * 8UL)); 159 upa_writeq(0UL, err_base + (i * 8UL)); 160 stc_error_buf[i] = val; 161 } 162 for (i = 0; i < 16; i++) { 163 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL)); 164 stc_line_buf[i] = upa_readq(line_base + (i * 8UL)); 165 upa_writeq(0UL, tag_base + (i * 8UL)); 166 upa_writeq(0UL, line_base + (i * 8UL)); 167 } 168 169 /* OK, state is logged, exit diagnostic mode. */ 170 upa_writeq(control, strbuf->strbuf_control); 171 172 for (i = 0; i < 16; i++) { 173 int j, saw_error, first, last; 174 175 saw_error = 0; 176 first = i * 8; 177 last = first + 8; 178 for (j = first; j < last; j++) { 179 unsigned long errval = stc_error_buf[j]; 180 if (errval != 0) { 181 saw_error++; 182 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", 183 pbm->name, 184 j, 185 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, 186 (errval & SCHIZO_STCERR_READ) ? 1 : 0); 187 } 188 } 189 if (saw_error != 0) { 190 unsigned long tagval = stc_tag_buf[i]; 191 unsigned long lineval = stc_line_buf[i]; 192 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n", 193 pbm->name, 194 i, 195 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), 196 (tagval & SCHIZO_STCTAG_VPN), 197 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), 198 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); 199 200 /* XXX Should spit out per-bank error information... -DaveM */ 201 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" 202 "V(%d)FOFN(%d)]\n", 203 pbm->name, 204 i, 205 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), 206 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), 207 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), 208 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), 209 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), 210 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); 211 } 212 } 213 214 spin_unlock(&stc_buf_lock); 215 } 216 217 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous 218 * controller level errors. 219 */ 220 221 #define SCHIZO_IOMMU_TAG 0xa580UL 222 #define SCHIZO_IOMMU_DATA 0xa600UL 223 224 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL 225 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL 226 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL 227 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL 228 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL 229 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL 230 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL 231 232 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL 233 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL 234 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL 235 236 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm, 237 enum schizo_error_type type) 238 { 239 struct iommu *iommu = pbm->iommu; 240 unsigned long iommu_tag[16]; 241 unsigned long iommu_data[16]; 242 unsigned long flags; 243 u64 control; 244 int i; 245 246 spin_lock_irqsave(&iommu->lock, flags); 247 control = upa_readq(iommu->iommu_control); 248 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { 249 unsigned long base; 250 char *type_string; 251 252 /* Clear the error encountered bit. */ 253 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; 254 upa_writeq(control, iommu->iommu_control); 255 256 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { 257 case 0: 258 type_string = "Protection Error"; 259 break; 260 case 1: 261 type_string = "Invalid Error"; 262 break; 263 case 2: 264 type_string = "TimeOut Error"; 265 break; 266 case 3: 267 default: 268 type_string = "ECC Error"; 269 break; 270 } 271 printk("%s: IOMMU Error, type[%s]\n", 272 pbm->name, type_string); 273 274 /* Put the IOMMU into diagnostic mode and probe 275 * it's TLB for entries with error status. 276 * 277 * It is very possible for another DVMA to occur 278 * while we do this probe, and corrupt the system 279 * further. But we are so screwed at this point 280 * that we are likely to crash hard anyways, so 281 * get as much diagnostic information to the 282 * console as we can. 283 */ 284 upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB, 285 iommu->iommu_control); 286 287 base = pbm->pbm_regs; 288 289 for (i = 0; i < 16; i++) { 290 iommu_tag[i] = 291 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL)); 292 iommu_data[i] = 293 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL)); 294 295 /* Now clear out the entry. */ 296 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL)); 297 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL)); 298 } 299 300 /* Leave diagnostic mode. */ 301 upa_writeq(control, iommu->iommu_control); 302 303 for (i = 0; i < 16; i++) { 304 unsigned long tag, data; 305 306 tag = iommu_tag[i]; 307 if (!(tag & SCHIZO_IOMMU_TAG_ERR)) 308 continue; 309 310 data = iommu_data[i]; 311 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { 312 case 0: 313 type_string = "Protection Error"; 314 break; 315 case 1: 316 type_string = "Invalid Error"; 317 break; 318 case 2: 319 type_string = "TimeOut Error"; 320 break; 321 case 3: 322 default: 323 type_string = "ECC Error"; 324 break; 325 } 326 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) " 327 "sz(%dK) vpg(%08lx)]\n", 328 pbm->name, i, type_string, 329 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), 330 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), 331 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), 332 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8), 333 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); 334 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", 335 pbm->name, i, 336 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), 337 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), 338 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); 339 } 340 } 341 if (pbm->stc.strbuf_enabled) 342 __schizo_check_stc_error_pbm(pbm, type); 343 spin_unlock_irqrestore(&iommu->lock, flags); 344 } 345 346 static void schizo_check_iommu_error(struct pci_pbm_info *pbm, 347 enum schizo_error_type type) 348 { 349 schizo_check_iommu_error_pbm(pbm, type); 350 if (pbm->sibling) 351 schizo_check_iommu_error_pbm(pbm->sibling, type); 352 } 353 354 /* Uncorrectable ECC error status gathering. */ 355 #define SCHIZO_UE_AFSR 0x10030UL 356 #define SCHIZO_UE_AFAR 0x10038UL 357 358 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */ 359 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */ 360 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */ 361 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */ 362 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */ 363 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */ 364 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */ 365 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */ 366 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */ 367 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */ 368 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */ 369 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */ 370 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */ 371 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */ 372 373 static irqreturn_t schizo_ue_intr(int irq, void *dev_id) 374 { 375 struct pci_pbm_info *pbm = dev_id; 376 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR; 377 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR; 378 unsigned long afsr, afar, error_bits; 379 int reported, limit; 380 381 /* Latch uncorrectable error status. */ 382 afar = upa_readq(afar_reg); 383 384 /* If either of the error pending bits are set in the 385 * AFSR, the error status is being actively updated by 386 * the hardware and we must re-read to get a clean value. 387 */ 388 limit = 1000; 389 do { 390 afsr = upa_readq(afsr_reg); 391 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 392 393 /* Clear the primary/secondary error status bits. */ 394 error_bits = afsr & 395 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR | 396 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); 397 if (!error_bits) 398 return IRQ_NONE; 399 upa_writeq(error_bits, afsr_reg); 400 401 /* Log the error. */ 402 printk("%s: Uncorrectable Error, primary error type[%s]\n", 403 pbm->name, 404 (((error_bits & SCHIZO_UEAFSR_PPIO) ? 405 "PIO" : 406 ((error_bits & SCHIZO_UEAFSR_PDRD) ? 407 "DMA Read" : 408 ((error_bits & SCHIZO_UEAFSR_PDWR) ? 409 "DMA Write" : "???"))))); 410 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 411 pbm->name, 412 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 413 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 414 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 415 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 416 pbm->name, 417 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 418 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 419 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 420 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 421 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 422 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 423 printk("%s: UE Secondary errors [", pbm->name); 424 reported = 0; 425 if (afsr & SCHIZO_UEAFSR_SPIO) { 426 reported++; 427 printk("(PIO)"); 428 } 429 if (afsr & SCHIZO_UEAFSR_SDMA) { 430 reported++; 431 printk("(DMA)"); 432 } 433 if (!reported) 434 printk("(none)"); 435 printk("]\n"); 436 437 /* Interrogate IOMMU for error status. */ 438 schizo_check_iommu_error(pbm, UE_ERR); 439 440 return IRQ_HANDLED; 441 } 442 443 #define SCHIZO_CE_AFSR 0x10040UL 444 #define SCHIZO_CE_AFAR 0x10048UL 445 446 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL 447 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL 448 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL 449 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL 450 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL 451 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL 452 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL 453 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL 454 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL 455 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL 456 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL 457 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL 458 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL 459 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL 460 461 static irqreturn_t schizo_ce_intr(int irq, void *dev_id) 462 { 463 struct pci_pbm_info *pbm = dev_id; 464 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR; 465 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR; 466 unsigned long afsr, afar, error_bits; 467 int reported, limit; 468 469 /* Latch error status. */ 470 afar = upa_readq(afar_reg); 471 472 /* If either of the error pending bits are set in the 473 * AFSR, the error status is being actively updated by 474 * the hardware and we must re-read to get a clean value. 475 */ 476 limit = 1000; 477 do { 478 afsr = upa_readq(afsr_reg); 479 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); 480 481 /* Clear primary/secondary error status bits. */ 482 error_bits = afsr & 483 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR | 484 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); 485 if (!error_bits) 486 return IRQ_NONE; 487 upa_writeq(error_bits, afsr_reg); 488 489 /* Log the error. */ 490 printk("%s: Correctable Error, primary error type[%s]\n", 491 pbm->name, 492 (((error_bits & SCHIZO_CEAFSR_PPIO) ? 493 "PIO" : 494 ((error_bits & SCHIZO_CEAFSR_PDRD) ? 495 "DMA Read" : 496 ((error_bits & SCHIZO_CEAFSR_PDWR) ? 497 "DMA Write" : "???"))))); 498 499 /* XXX Use syndrome and afar to print out module string just like 500 * XXX UDB CE trap handler does... -DaveM 501 */ 502 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", 503 pbm->name, 504 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, 505 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, 506 (afsr & SCHIZO_UEAFSR_AID) >> 24UL); 507 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", 508 pbm->name, 509 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, 510 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, 511 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, 512 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, 513 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); 514 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 515 printk("%s: CE Secondary errors [", pbm->name); 516 reported = 0; 517 if (afsr & SCHIZO_CEAFSR_SPIO) { 518 reported++; 519 printk("(PIO)"); 520 } 521 if (afsr & SCHIZO_CEAFSR_SDMA) { 522 reported++; 523 printk("(DMA)"); 524 } 525 if (!reported) 526 printk("(none)"); 527 printk("]\n"); 528 529 return IRQ_HANDLED; 530 } 531 532 #define SCHIZO_PCI_AFSR 0x2010UL 533 #define SCHIZO_PCI_AFAR 0x2018UL 534 535 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */ 536 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */ 537 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */ 538 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */ 539 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */ 540 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */ 541 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */ 542 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */ 543 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */ 544 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */ 545 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */ 546 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */ 547 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */ 548 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */ 549 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */ 550 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */ 551 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */ 552 553 #define SCHIZO_PCI_CTRL (0x2000UL) 554 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */ 555 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */ 556 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */ 557 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */ 558 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */ 559 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */ 560 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */ 561 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */ 562 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */ 563 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */ 564 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */ 565 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */ 566 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */ 567 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */ 568 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */ 569 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL 570 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */ 571 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */ 572 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */ 573 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */ 574 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */ 575 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */ 576 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */ 577 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */ 578 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */ 579 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */ 580 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */ 581 582 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm) 583 { 584 unsigned long csr_reg, csr, csr_error_bits; 585 irqreturn_t ret = IRQ_NONE; 586 u32 stat; 587 588 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; 589 csr = upa_readq(csr_reg); 590 csr_error_bits = 591 csr & (SCHIZO_PCICTRL_BUS_UNUS | 592 SCHIZO_PCICTRL_TTO_ERR | 593 SCHIZO_PCICTRL_RTRY_ERR | 594 SCHIZO_PCICTRL_DTO_ERR | 595 SCHIZO_PCICTRL_SBH_ERR | 596 SCHIZO_PCICTRL_SERR); 597 if (csr_error_bits) { 598 /* Clear the errors. */ 599 upa_writeq(csr, csr_reg); 600 601 /* Log 'em. */ 602 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) 603 printk("%s: Bus unusable error asserted.\n", 604 pbm->name); 605 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR) 606 printk("%s: PCI TRDY# timeout error asserted.\n", 607 pbm->name); 608 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR) 609 printk("%s: PCI excessive retry error asserted.\n", 610 pbm->name); 611 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR) 612 printk("%s: PCI discard timeout error asserted.\n", 613 pbm->name); 614 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR) 615 printk("%s: PCI streaming byte hole error asserted.\n", 616 pbm->name); 617 if (csr_error_bits & SCHIZO_PCICTRL_SERR) 618 printk("%s: PCI SERR signal asserted.\n", 619 pbm->name); 620 ret = IRQ_HANDLED; 621 } 622 pbm->pci_ops->read(pbm->pci_bus, 0, PCI_STATUS, 2, &stat); 623 if (stat & (PCI_STATUS_PARITY | 624 PCI_STATUS_SIG_TARGET_ABORT | 625 PCI_STATUS_REC_TARGET_ABORT | 626 PCI_STATUS_REC_MASTER_ABORT | 627 PCI_STATUS_SIG_SYSTEM_ERROR)) { 628 printk("%s: PCI bus error, PCI_STATUS[%04x]\n", 629 pbm->name, stat); 630 pbm->pci_ops->write(pbm->pci_bus, 0, PCI_STATUS, 2, 0xffff); 631 ret = IRQ_HANDLED; 632 } 633 return ret; 634 } 635 636 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id) 637 { 638 struct pci_pbm_info *pbm = dev_id; 639 unsigned long afsr_reg, afar_reg, base; 640 unsigned long afsr, afar, error_bits; 641 int reported; 642 643 base = pbm->pbm_regs; 644 645 afsr_reg = base + SCHIZO_PCI_AFSR; 646 afar_reg = base + SCHIZO_PCI_AFAR; 647 648 /* Latch error status. */ 649 afar = upa_readq(afar_reg); 650 afsr = upa_readq(afsr_reg); 651 652 /* Clear primary/secondary error status bits. */ 653 error_bits = afsr & 654 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 655 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 656 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 657 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 658 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 659 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); 660 if (!error_bits) 661 return schizo_pcierr_intr_other(pbm); 662 upa_writeq(error_bits, afsr_reg); 663 664 /* Log the error. */ 665 printk("%s: PCI Error, primary error type[%s]\n", 666 pbm->name, 667 (((error_bits & SCHIZO_PCIAFSR_PMA) ? 668 "Master Abort" : 669 ((error_bits & SCHIZO_PCIAFSR_PTA) ? 670 "Target Abort" : 671 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ? 672 "Excessive Retries" : 673 ((error_bits & SCHIZO_PCIAFSR_PPERR) ? 674 "Parity Error" : 675 ((error_bits & SCHIZO_PCIAFSR_PTTO) ? 676 "Timeout" : 677 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ? 678 "Bus Unusable" : "???")))))))); 679 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n", 680 pbm->name, 681 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, 682 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, 683 ((afsr & SCHIZO_PCIAFSR_CFG) ? 684 "Config" : 685 ((afsr & SCHIZO_PCIAFSR_MEM) ? 686 "Memory" : 687 ((afsr & SCHIZO_PCIAFSR_IO) ? 688 "I/O" : "???")))); 689 printk("%s: PCI AFAR [%016lx]\n", 690 pbm->name, afar); 691 printk("%s: PCI Secondary errors [", 692 pbm->name); 693 reported = 0; 694 if (afsr & SCHIZO_PCIAFSR_SMA) { 695 reported++; 696 printk("(Master Abort)"); 697 } 698 if (afsr & SCHIZO_PCIAFSR_STA) { 699 reported++; 700 printk("(Target Abort)"); 701 } 702 if (afsr & SCHIZO_PCIAFSR_SRTRY) { 703 reported++; 704 printk("(Excessive Retries)"); 705 } 706 if (afsr & SCHIZO_PCIAFSR_SPERR) { 707 reported++; 708 printk("(Parity Error)"); 709 } 710 if (afsr & SCHIZO_PCIAFSR_STTO) { 711 reported++; 712 printk("(Timeout)"); 713 } 714 if (afsr & SCHIZO_PCIAFSR_SUNUS) { 715 reported++; 716 printk("(Bus Unusable)"); 717 } 718 if (!reported) 719 printk("(none)"); 720 printk("]\n"); 721 722 /* For the error types shown, scan PBM's PCI bus for devices 723 * which have logged that error type. 724 */ 725 726 /* If we see a Target Abort, this could be the result of an 727 * IOMMU translation error of some sort. It is extremely 728 * useful to log this information as usually it indicates 729 * a bug in the IOMMU support code or a PCI device driver. 730 */ 731 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { 732 schizo_check_iommu_error(pbm, PCI_ERR); 733 pci_scan_for_target_abort(pbm, pbm->pci_bus); 734 } 735 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) 736 pci_scan_for_master_abort(pbm, pbm->pci_bus); 737 738 /* For excessive retries, PSYCHO/PBM will abort the device 739 * and there is no way to specifically check for excessive 740 * retries in the config space status registers. So what 741 * we hope is that we'll catch it via the master/target 742 * abort events. 743 */ 744 745 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) 746 pci_scan_for_parity_error(pbm, pbm->pci_bus); 747 748 return IRQ_HANDLED; 749 } 750 751 #define SCHIZO_SAFARI_ERRLOG 0x10018UL 752 753 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL 754 755 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */ 756 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */ 757 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */ 758 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */ 759 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */ 760 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */ 761 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */ 762 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */ 763 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */ 764 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */ 765 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */ 766 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */ 767 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */ 768 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */ 769 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */ 770 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */ 771 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */ 772 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */ 773 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */ 774 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */ 775 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */ 776 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */ 777 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */ 778 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */ 779 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */ 780 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */ 781 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */ 782 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */ 783 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */ 784 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */ 785 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */ 786 787 /* We only expect UNMAP errors here. The rest of the Safari errors 788 * are marked fatal and thus cause a system reset. 789 */ 790 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id) 791 { 792 struct pci_pbm_info *pbm = dev_id; 793 u64 errlog; 794 795 errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 796 upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT), 797 pbm->controller_regs + SCHIZO_SAFARI_ERRLOG); 798 799 if (!(errlog & BUS_ERROR_UNMAP)) { 800 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n", 801 pbm->name, errlog); 802 803 return IRQ_HANDLED; 804 } 805 806 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", 807 pbm->name); 808 schizo_check_iommu_error(pbm, SAFARI_ERR); 809 810 return IRQ_HANDLED; 811 } 812 813 /* Nearly identical to PSYCHO equivalents... */ 814 #define SCHIZO_ECC_CTRL 0x10020UL 815 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 816 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ 817 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 818 819 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL 820 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL 821 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL 822 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL 823 824 static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino) 825 { 826 ino &= IMAP_INO; 827 828 if (pbm->ino_bitmap & (1UL << ino)) 829 return 1; 830 831 return 0; 832 } 833 834 /* How the Tomatillo IRQs are routed around is pure guesswork here. 835 * 836 * All the Tomatillo devices I see in prtconf dumps seem to have only 837 * a single PCI bus unit attached to it. It would seem they are separate 838 * devices because their PortID (ie. JBUS ID) values are all different 839 * and thus the registers are mapped to totally different locations. 840 * 841 * However, two Tomatillo's look "similar" in that the only difference 842 * in their PortID is the lowest bit. 843 * 844 * So if we were to ignore this lower bit, it certainly looks like two 845 * PCI bus units of the same Tomatillo. I still have not really 846 * figured this out... 847 */ 848 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm) 849 { 850 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 851 u64 tmp, err_mask, err_no_mask; 852 int err; 853 854 /* Tomatillo IRQ property layout is: 855 * 0: PCIERR 856 * 1: UE ERR 857 * 2: CE ERR 858 * 3: SERR 859 * 4: POWER FAIL? 860 */ 861 862 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 863 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 864 "TOMATILLO_UE", pbm); 865 if (err) 866 printk(KERN_WARNING "%s: Could not register UE, " 867 "err=%d\n", pbm->name, err); 868 } 869 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 870 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 871 "TOMATILLO_CE", pbm); 872 if (err) 873 printk(KERN_WARNING "%s: Could not register CE, " 874 "err=%d\n", pbm->name, err); 875 } 876 err = 0; 877 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 878 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 879 "TOMATILLO_PCIERR", pbm); 880 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 881 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 882 "TOMATILLO_PCIERR", pbm); 883 } 884 if (err) 885 printk(KERN_WARNING "%s: Could not register PCIERR, " 886 "err=%d\n", pbm->name, err); 887 888 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 889 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 890 "TOMATILLO_SERR", pbm); 891 if (err) 892 printk(KERN_WARNING "%s: Could not register SERR, " 893 "err=%d\n", pbm->name, err); 894 } 895 896 /* Enable UE and CE interrupts for controller. */ 897 upa_writeq((SCHIZO_ECCCTRL_EE | 898 SCHIZO_ECCCTRL_UE | 899 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 900 901 /* Enable PCI Error interrupts and clear error 902 * bits. 903 */ 904 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 905 SCHIZO_PCICTRL_TTO_ERR | 906 SCHIZO_PCICTRL_RTRY_ERR | 907 SCHIZO_PCICTRL_SERR | 908 SCHIZO_PCICTRL_EEN); 909 910 err_no_mask = SCHIZO_PCICTRL_DTO_ERR; 911 912 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 913 tmp |= err_mask; 914 tmp &= ~err_no_mask; 915 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 916 917 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 918 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 919 SCHIZO_PCIAFSR_PTTO | 920 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 921 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 922 SCHIZO_PCIAFSR_STTO); 923 924 upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR); 925 926 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | 927 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | 928 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA | 929 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO | 930 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR | 931 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B | 932 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR | 933 BUS_ERROR_APERR | BUS_ERROR_UNMAP | 934 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); 935 936 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 937 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 938 939 upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)), 940 pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL); 941 } 942 943 static void schizo_register_error_handlers(struct pci_pbm_info *pbm) 944 { 945 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 946 u64 tmp, err_mask, err_no_mask; 947 int err; 948 949 /* Schizo IRQ property layout is: 950 * 0: PCIERR 951 * 1: UE ERR 952 * 2: CE ERR 953 * 3: SERR 954 * 4: POWER FAIL? 955 */ 956 957 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) { 958 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0, 959 "SCHIZO_UE", pbm); 960 if (err) 961 printk(KERN_WARNING "%s: Could not register UE, " 962 "err=%d\n", pbm->name, err); 963 } 964 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) { 965 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0, 966 "SCHIZO_CE", pbm); 967 if (err) 968 printk(KERN_WARNING "%s: Could not register CE, " 969 "err=%d\n", pbm->name, err); 970 } 971 err = 0; 972 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) { 973 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 974 "SCHIZO_PCIERR", pbm); 975 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) { 976 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0, 977 "SCHIZO_PCIERR", pbm); 978 } 979 if (err) 980 printk(KERN_WARNING "%s: Could not register PCIERR, " 981 "err=%d\n", pbm->name, err); 982 983 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) { 984 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0, 985 "SCHIZO_SERR", pbm); 986 if (err) 987 printk(KERN_WARNING "%s: Could not register SERR, " 988 "err=%d\n", pbm->name, err); 989 } 990 991 /* Enable UE and CE interrupts for controller. */ 992 upa_writeq((SCHIZO_ECCCTRL_EE | 993 SCHIZO_ECCCTRL_UE | 994 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL); 995 996 err_mask = (SCHIZO_PCICTRL_BUS_UNUS | 997 SCHIZO_PCICTRL_ESLCK | 998 SCHIZO_PCICTRL_TTO_ERR | 999 SCHIZO_PCICTRL_RTRY_ERR | 1000 SCHIZO_PCICTRL_SBH_ERR | 1001 SCHIZO_PCICTRL_SERR | 1002 SCHIZO_PCICTRL_EEN); 1003 1004 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR | 1005 SCHIZO_PCICTRL_SBH_INT); 1006 1007 /* Enable PCI Error interrupts and clear error 1008 * bits for each PBM. 1009 */ 1010 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1011 tmp |= err_mask; 1012 tmp &= ~err_no_mask; 1013 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1014 1015 upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | 1016 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | 1017 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | 1018 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | 1019 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | 1020 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS), 1021 pbm->pbm_regs + SCHIZO_PCI_AFSR); 1022 1023 /* Make all Safari error conditions fatal except unmapped 1024 * errors which we make generate interrupts. 1025 */ 1026 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS | 1027 BUS_ERROR_BADMA | BUS_ERROR_BADMB | 1028 BUS_ERROR_BADMC | 1029 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1030 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB | 1031 BUS_ERROR_CIQTO | 1032 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO | 1033 BUS_ERROR_UFPQTO | BUS_ERROR_APERR | 1034 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT | 1035 BUS_ERROR_ILL); 1036 #if 1 1037 /* XXX Something wrong with some Excalibur systems 1038 * XXX Sun is shipping. The behavior on a 2-cpu 1039 * XXX machine is that both CPU1 parity error bits 1040 * XXX are set and are immediately set again when 1041 * XXX their error status bits are cleared. Just 1042 * XXX ignore them for now. -DaveM 1043 */ 1044 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | 1045 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); 1046 #endif 1047 1048 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask), 1049 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL); 1050 } 1051 1052 static void pbm_config_busmastering(struct pci_pbm_info *pbm) 1053 { 1054 u8 *addr; 1055 1056 /* Set cache-line size to 64 bytes, this is actually 1057 * a nop but I do it for completeness. 1058 */ 1059 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1060 0, PCI_CACHE_LINE_SIZE); 1061 pci_config_write8(addr, 64 / sizeof(u32)); 1062 1063 /* Set PBM latency timer to 64 PCI clocks. */ 1064 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, 1065 0, PCI_LATENCY_TIMER); 1066 pci_config_write8(addr, 64); 1067 } 1068 1069 static void schizo_scan_bus(struct pci_pbm_info *pbm, struct device *parent) 1070 { 1071 pbm_config_busmastering(pbm); 1072 pbm->is_66mhz_capable = 1073 (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL) 1074 != NULL); 1075 1076 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 1077 1078 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1079 tomatillo_register_error_handlers(pbm); 1080 else 1081 schizo_register_error_handlers(pbm); 1082 } 1083 1084 #define SCHIZO_STRBUF_CONTROL (0x02800UL) 1085 #define SCHIZO_STRBUF_FLUSH (0x02808UL) 1086 #define SCHIZO_STRBUF_FSYNC (0x02810UL) 1087 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL) 1088 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL) 1089 1090 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) 1091 { 1092 unsigned long base = pbm->pbm_regs; 1093 u64 control; 1094 1095 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1096 /* TOMATILLO lacks streaming cache. */ 1097 return; 1098 } 1099 1100 /* SCHIZO has context flushing. */ 1101 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; 1102 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; 1103 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; 1104 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; 1105 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; 1106 1107 pbm->stc.strbuf_flushflag = (volatile unsigned long *) 1108 ((((unsigned long)&pbm->stc.__flushflag_buf[0]) 1109 + 63UL) 1110 & ~63UL); 1111 pbm->stc.strbuf_flushflag_pa = (unsigned long) 1112 __pa(pbm->stc.strbuf_flushflag); 1113 1114 /* Turn off LRU locking and diag mode, enable the 1115 * streaming buffer and leave the rerun-disable 1116 * setting however OBP set it. 1117 */ 1118 control = upa_readq(pbm->stc.strbuf_control); 1119 control &= ~(SCHIZO_STRBUF_CTRL_LPTR | 1120 SCHIZO_STRBUF_CTRL_LENAB | 1121 SCHIZO_STRBUF_CTRL_DENAB); 1122 control |= SCHIZO_STRBUF_CTRL_ENAB; 1123 upa_writeq(control, pbm->stc.strbuf_control); 1124 1125 pbm->stc.strbuf_enabled = 1; 1126 } 1127 1128 #define SCHIZO_IOMMU_CONTROL (0x00200UL) 1129 #define SCHIZO_IOMMU_TSBBASE (0x00208UL) 1130 #define SCHIZO_IOMMU_FLUSH (0x00210UL) 1131 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL) 1132 1133 static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm) 1134 { 1135 static const u32 vdma_default[] = { 0xc0000000, 0x40000000 }; 1136 unsigned long i, tagbase, database; 1137 struct iommu *iommu = pbm->iommu; 1138 int tsbsize, err; 1139 const u32 *vdma; 1140 u32 dma_mask; 1141 u64 control; 1142 1143 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL); 1144 if (!vdma) 1145 vdma = vdma_default; 1146 1147 dma_mask = vdma[0]; 1148 switch (vdma[1]) { 1149 case 0x20000000: 1150 dma_mask |= 0x1fffffff; 1151 tsbsize = 64; 1152 break; 1153 1154 case 0x40000000: 1155 dma_mask |= 0x3fffffff; 1156 tsbsize = 128; 1157 break; 1158 1159 case 0x80000000: 1160 dma_mask |= 0x7fffffff; 1161 tsbsize = 128; 1162 break; 1163 1164 default: 1165 printk(KERN_ERR PFX "Strange virtual-dma size.\n"); 1166 return -EINVAL; 1167 } 1168 1169 /* Register addresses, SCHIZO has iommu ctx flushing. */ 1170 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; 1171 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; 1172 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; 1173 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL); 1174 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; 1175 1176 /* We use the main control/status register of SCHIZO as the write 1177 * completion register. 1178 */ 1179 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; 1180 1181 /* 1182 * Invalidate TLB Entries. 1183 */ 1184 control = upa_readq(iommu->iommu_control); 1185 control |= SCHIZO_IOMMU_CTRL_DENAB; 1186 upa_writeq(control, iommu->iommu_control); 1187 1188 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; 1189 1190 for (i = 0; i < 16; i++) { 1191 upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL)); 1192 upa_writeq(0, pbm->pbm_regs + database + (i * 8UL)); 1193 } 1194 1195 /* Leave diag mode enabled for full-flushing done 1196 * in pci_iommu.c 1197 */ 1198 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, 1199 pbm->numa_node); 1200 if (err) { 1201 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err); 1202 return err; 1203 } 1204 1205 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); 1206 1207 control = upa_readq(iommu->iommu_control); 1208 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); 1209 switch (tsbsize) { 1210 case 64: 1211 control |= SCHIZO_IOMMU_TSBSZ_64K; 1212 break; 1213 case 128: 1214 control |= SCHIZO_IOMMU_TSBSZ_128K; 1215 break; 1216 } 1217 1218 control |= SCHIZO_IOMMU_CTRL_ENAB; 1219 upa_writeq(control, iommu->iommu_control); 1220 1221 return 0; 1222 } 1223 1224 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL) 1225 #define SCHIZO_IRQ_RETRY_INF 0xffUL 1226 1227 #define SCHIZO_PCI_DIAG (0x2020UL) 1228 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */ 1229 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */ 1230 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */ 1231 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */ 1232 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */ 1233 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */ 1234 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */ 1235 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */ 1236 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */ 1237 1238 #define TOMATILLO_PCI_IOC_CSR (0x2248UL) 1239 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL 1240 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL 1241 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL 1242 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL 1243 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL 1244 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL 1245 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL 1246 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL 1247 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL 1248 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL 1249 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL 1250 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL 1251 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL 1252 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL 1253 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL 1254 1255 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL) 1256 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL) 1257 1258 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) 1259 { 1260 u64 tmp; 1261 1262 upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY); 1263 1264 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL); 1265 1266 /* Enable arbiter for all PCI slots. */ 1267 tmp |= 0xff; 1268 1269 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1270 pbm->chip_version >= 0x2) 1271 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; 1272 1273 if (!of_property_read_bool(pbm->op->dev.of_node, "no-bus-parking")) 1274 tmp |= SCHIZO_PCICTRL_PARK; 1275 else 1276 tmp &= ~SCHIZO_PCICTRL_PARK; 1277 1278 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && 1279 pbm->chip_version <= 0x1) 1280 tmp |= SCHIZO_PCICTRL_DTO_INT; 1281 else 1282 tmp &= ~SCHIZO_PCICTRL_DTO_INT; 1283 1284 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) 1285 tmp |= (SCHIZO_PCICTRL_MRM_PREF | 1286 SCHIZO_PCICTRL_RDO_PREF | 1287 SCHIZO_PCICTRL_RDL_PREF); 1288 1289 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL); 1290 1291 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG); 1292 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | 1293 SCHIZO_PCIDIAG_D_RETRY | 1294 SCHIZO_PCIDIAG_D_INTSYNC); 1295 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG); 1296 1297 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1298 /* Clear prefetch lengths to workaround a bug in 1299 * Jalapeno... 1300 */ 1301 tmp = (TOMATILLO_IOC_PART_WPENAB | 1302 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | 1303 TOMATILLO_IOC_RDMULT_CPENAB | 1304 TOMATILLO_IOC_RDONE_CPENAB | 1305 TOMATILLO_IOC_RDLINE_CPENAB); 1306 1307 upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR); 1308 } 1309 } 1310 1311 static int schizo_pbm_init(struct pci_pbm_info *pbm, 1312 struct platform_device *op, u32 portid, 1313 int chip_type) 1314 { 1315 const struct linux_prom64_registers *regs; 1316 struct device_node *dp = op->dev.of_node; 1317 const char *chipset_name; 1318 int err; 1319 1320 switch (chip_type) { 1321 case PBM_CHIP_TYPE_TOMATILLO: 1322 chipset_name = "TOMATILLO"; 1323 break; 1324 1325 case PBM_CHIP_TYPE_SCHIZO_PLUS: 1326 chipset_name = "SCHIZO+"; 1327 break; 1328 1329 case PBM_CHIP_TYPE_SCHIZO: 1330 default: 1331 chipset_name = "SCHIZO"; 1332 break; 1333 } 1334 1335 /* For SCHIZO, three OBP regs: 1336 * 1) PBM controller regs 1337 * 2) Schizo front-end controller regs (same for both PBMs) 1338 * 3) PBM PCI config space 1339 * 1340 * For TOMATILLO, four OBP regs: 1341 * 1) PBM controller regs 1342 * 2) Tomatillo front-end controller regs 1343 * 3) PBM PCI config space 1344 * 4) Ichip regs 1345 */ 1346 regs = of_get_property(dp, "reg", NULL); 1347 1348 pbm->next = pci_pbm_root; 1349 pci_pbm_root = pbm; 1350 1351 pbm->numa_node = NUMA_NO_NODE; 1352 1353 pbm->pci_ops = &sun4u_pci_ops; 1354 pbm->config_space_reg_bits = 8; 1355 1356 pbm->index = pci_num_pbms++; 1357 1358 pbm->portid = portid; 1359 pbm->op = op; 1360 1361 pbm->chip_type = chip_type; 1362 pbm->chip_version = of_getintprop_default(dp, "version#", 0); 1363 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0); 1364 1365 pbm->pbm_regs = regs[0].phys_addr; 1366 pbm->controller_regs = regs[1].phys_addr - 0x10000UL; 1367 1368 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) 1369 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL; 1370 1371 pbm->name = dp->full_name; 1372 1373 printk("%s: %s PCI Bus Module ver[%x:%x]\n", 1374 pbm->name, chipset_name, 1375 pbm->chip_version, pbm->chip_revision); 1376 1377 schizo_pbm_hw_init(pbm); 1378 1379 pci_determine_mem_io_space(pbm); 1380 1381 pci_get_pbm_props(pbm); 1382 1383 err = schizo_pbm_iommu_init(pbm); 1384 if (err) 1385 return err; 1386 1387 schizo_pbm_strbuf_init(pbm); 1388 1389 schizo_scan_bus(pbm, &op->dev); 1390 1391 return 0; 1392 } 1393 1394 static inline int portid_compare(u32 x, u32 y, int chip_type) 1395 { 1396 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) { 1397 if (x == (y ^ 1)) 1398 return 1; 1399 return 0; 1400 } 1401 return (x == y); 1402 } 1403 1404 static struct pci_pbm_info *schizo_find_sibling(u32 portid, int chip_type) 1405 { 1406 struct pci_pbm_info *pbm; 1407 1408 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 1409 if (portid_compare(pbm->portid, portid, chip_type)) 1410 return pbm; 1411 } 1412 return NULL; 1413 } 1414 1415 static int __schizo_init(struct platform_device *op, unsigned long chip_type) 1416 { 1417 struct device_node *dp = op->dev.of_node; 1418 struct pci_pbm_info *pbm; 1419 struct iommu *iommu; 1420 u32 portid; 1421 int err; 1422 1423 portid = of_getintprop_default(dp, "portid", 0xff); 1424 1425 err = -ENOMEM; 1426 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 1427 if (!pbm) { 1428 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); 1429 goto out_err; 1430 } 1431 1432 pbm->sibling = schizo_find_sibling(portid, chip_type); 1433 1434 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); 1435 if (!iommu) { 1436 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n"); 1437 goto out_free_pbm; 1438 } 1439 1440 pbm->iommu = iommu; 1441 1442 if (schizo_pbm_init(pbm, op, portid, chip_type)) 1443 goto out_free_iommu; 1444 1445 if (pbm->sibling) 1446 pbm->sibling->sibling = pbm; 1447 1448 dev_set_drvdata(&op->dev, pbm); 1449 1450 return 0; 1451 1452 out_free_iommu: 1453 kfree(pbm->iommu); 1454 1455 out_free_pbm: 1456 kfree(pbm); 1457 1458 out_err: 1459 return err; 1460 } 1461 1462 static const struct of_device_id schizo_match[]; 1463 static int schizo_probe(struct platform_device *op) 1464 { 1465 const struct of_device_id *match; 1466 1467 match = of_match_device(schizo_match, &op->dev); 1468 if (!match) 1469 return -EINVAL; 1470 return __schizo_init(op, (unsigned long)match->data); 1471 } 1472 1473 /* The ordering of this table is very important. Some Tomatillo 1474 * nodes announce that they are compatible with both pci108e,a801 1475 * and pci108e,8001. So list the chips in reverse chronological 1476 * order. 1477 */ 1478 static const struct of_device_id schizo_match[] = { 1479 { 1480 .name = "pci", 1481 .compatible = "pci108e,a801", 1482 .data = (void *) PBM_CHIP_TYPE_TOMATILLO, 1483 }, 1484 { 1485 .name = "pci", 1486 .compatible = "pci108e,8002", 1487 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS, 1488 }, 1489 { 1490 .name = "pci", 1491 .compatible = "pci108e,8001", 1492 .data = (void *) PBM_CHIP_TYPE_SCHIZO, 1493 }, 1494 {}, 1495 }; 1496 1497 static struct platform_driver schizo_driver = { 1498 .driver = { 1499 .name = DRIVER_NAME, 1500 .of_match_table = schizo_match, 1501 }, 1502 .probe = schizo_probe, 1503 }; 1504 1505 static int __init schizo_init(void) 1506 { 1507 return platform_driver_register(&schizo_driver); 1508 } 1509 1510 subsys_initcall(schizo_init); 1511