1 // SPDX-License-Identifier: GPL-2.0 2 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/types.h> 11 #include <linux/pci.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/slab.h> 15 #include <linux/interrupt.h> 16 #include <linux/of.h> 17 #include <linux/of_platform.h> 18 #include <linux/platform_device.h> 19 20 #include <asm/iommu.h> 21 #include <asm/irq.h> 22 #include <asm/starfire.h> 23 #include <asm/prom.h> 24 #include <asm/upa.h> 25 26 #include "pci_impl.h" 27 #include "iommu_common.h" 28 #include "psycho_common.h" 29 30 #define DRIVER_NAME "psycho" 31 #define PFX DRIVER_NAME ": " 32 33 /* Misc. PSYCHO PCI controller register offsets and definitions. */ 34 #define PSYCHO_CONTROL 0x0010UL 35 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ 36 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */ 37 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */ 38 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */ 39 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */ 40 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */ 41 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */ 42 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */ 43 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */ 44 #define PSYCHO_PCIA_CTRL 0x2000UL 45 #define PSYCHO_PCIB_CTRL 0x4000UL 46 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */ 47 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */ 48 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */ 49 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */ 50 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */ 51 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */ 52 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */ 53 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */ 54 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */ 55 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */ 56 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ 57 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ 58 59 /* PSYCHO error handling support. */ 60 61 /* Helper function of IOMMU error checking, which checks out 62 * the state of the streaming buffers. The IOMMU lock is 63 * held when this is called. 64 * 65 * For the PCI error case we know which PBM (and thus which 66 * streaming buffer) caused the error, but for the uncorrectable 67 * error case we do not. So we always check both streaming caches. 68 */ 69 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL 70 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL 71 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ 72 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ 73 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ 74 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ 75 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ 76 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL 77 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL 78 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL 79 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL 80 #define PSYCHO_STC_DATA_A 0xb000UL 81 #define PSYCHO_STC_DATA_B 0xc000UL 82 #define PSYCHO_STC_ERR_A 0xb400UL 83 #define PSYCHO_STC_ERR_B 0xc400UL 84 #define PSYCHO_STC_TAG_A 0xb800UL 85 #define PSYCHO_STC_TAG_B 0xc800UL 86 #define PSYCHO_STC_LINE_A 0xb900UL 87 #define PSYCHO_STC_LINE_B 0xc900UL 88 89 /* When an Uncorrectable Error or a PCI Error happens, we 90 * interrogate the IOMMU state to see if it is the cause. 91 */ 92 #define PSYCHO_IOMMU_CONTROL 0x0200UL 93 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ 94 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ 95 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ 96 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ 97 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ 98 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ 99 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ 100 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ 101 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ 102 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ 103 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ 104 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ 105 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ 106 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ 107 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ 108 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ 109 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ 110 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ 111 #define PSYCHO_IOMMU_TSBBASE 0x0208UL 112 #define PSYCHO_IOMMU_FLUSH 0x0210UL 113 #define PSYCHO_IOMMU_TAG 0xa580UL 114 #define PSYCHO_IOMMU_DATA 0xa600UL 115 116 /* Uncorrectable Errors. Cause of the error and the address are 117 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors 118 * relating to UPA interface transactions. 119 */ 120 #define PSYCHO_UE_AFSR 0x0030UL 121 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ 122 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ 123 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ 124 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ 125 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ 126 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ 127 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ 128 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ 129 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */ 130 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ 131 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ 132 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ 133 #define PSYCHO_UE_AFAR 0x0038UL 134 135 static irqreturn_t psycho_ue_intr(int irq, void *dev_id) 136 { 137 struct pci_pbm_info *pbm = dev_id; 138 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR; 139 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR; 140 unsigned long afsr, afar, error_bits; 141 int reported; 142 143 /* Latch uncorrectable error status. */ 144 afar = upa_readq(afar_reg); 145 afsr = upa_readq(afsr_reg); 146 147 /* Clear the primary/secondary error status bits. */ 148 error_bits = afsr & 149 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR | 150 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); 151 if (!error_bits) 152 return IRQ_NONE; 153 upa_writeq(error_bits, afsr_reg); 154 155 /* Log the error. */ 156 printk("%s: Uncorrectable Error, primary error type[%s]\n", 157 pbm->name, 158 (((error_bits & PSYCHO_UEAFSR_PPIO) ? 159 "PIO" : 160 ((error_bits & PSYCHO_UEAFSR_PDRD) ? 161 "DMA Read" : 162 ((error_bits & PSYCHO_UEAFSR_PDWR) ? 163 "DMA Write" : "???"))))); 164 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n", 165 pbm->name, 166 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL, 167 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL, 168 (afsr & PSYCHO_UEAFSR_MID) >> 24UL, 169 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0)); 170 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); 171 printk("%s: UE Secondary errors [", pbm->name); 172 reported = 0; 173 if (afsr & PSYCHO_UEAFSR_SPIO) { 174 reported++; 175 printk("(PIO)"); 176 } 177 if (afsr & PSYCHO_UEAFSR_SDRD) { 178 reported++; 179 printk("(DMA Read)"); 180 } 181 if (afsr & PSYCHO_UEAFSR_SDWR) { 182 reported++; 183 printk("(DMA Write)"); 184 } 185 if (!reported) 186 printk("(none)"); 187 printk("]\n"); 188 189 /* Interrogate both IOMMUs for error status. */ 190 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR); 191 if (pbm->sibling) 192 psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR); 193 194 return IRQ_HANDLED; 195 } 196 197 /* Correctable Errors. */ 198 #define PSYCHO_CE_AFSR 0x0040UL 199 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ 200 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ 201 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ 202 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ 203 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ 204 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ 205 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ 206 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ 207 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ 208 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */ 209 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ 210 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ 211 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ 212 #define PSYCHO_CE_AFAR 0x0040UL 213 214 static irqreturn_t psycho_ce_intr(int irq, void *dev_id) 215 { 216 struct pci_pbm_info *pbm = dev_id; 217 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR; 218 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR; 219 unsigned long afsr, afar, error_bits; 220 int reported; 221 222 /* Latch error status. */ 223 afar = upa_readq(afar_reg); 224 afsr = upa_readq(afsr_reg); 225 226 /* Clear primary/secondary error status bits. */ 227 error_bits = afsr & 228 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR | 229 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); 230 if (!error_bits) 231 return IRQ_NONE; 232 upa_writeq(error_bits, afsr_reg); 233 234 /* Log the error. */ 235 printk("%s: Correctable Error, primary error type[%s]\n", 236 pbm->name, 237 (((error_bits & PSYCHO_CEAFSR_PPIO) ? 238 "PIO" : 239 ((error_bits & PSYCHO_CEAFSR_PDRD) ? 240 "DMA Read" : 241 ((error_bits & PSYCHO_CEAFSR_PDWR) ? 242 "DMA Write" : "???"))))); 243 244 /* XXX Use syndrome and afar to print out module string just like 245 * XXX UDB CE trap handler does... -DaveM 246 */ 247 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " 248 "UPA_MID[%02lx] was_block(%d)\n", 249 pbm->name, 250 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL, 251 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL, 252 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL, 253 (afsr & PSYCHO_CEAFSR_MID) >> 24UL, 254 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0)); 255 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); 256 printk("%s: CE Secondary errors [", pbm->name); 257 reported = 0; 258 if (afsr & PSYCHO_CEAFSR_SPIO) { 259 reported++; 260 printk("(PIO)"); 261 } 262 if (afsr & PSYCHO_CEAFSR_SDRD) { 263 reported++; 264 printk("(DMA Read)"); 265 } 266 if (afsr & PSYCHO_CEAFSR_SDWR) { 267 reported++; 268 printk("(DMA Write)"); 269 } 270 if (!reported) 271 printk("(none)"); 272 printk("]\n"); 273 274 return IRQ_HANDLED; 275 } 276 277 /* PCI Errors. They are signalled by the PCI bus module since they 278 * are associated with a specific bus segment. 279 */ 280 #define PSYCHO_PCI_AFSR_A 0x2010UL 281 #define PSYCHO_PCI_AFSR_B 0x4010UL 282 #define PSYCHO_PCI_AFAR_A 0x2018UL 283 #define PSYCHO_PCI_AFAR_B 0x4018UL 284 285 /* XXX What about PowerFail/PowerManagement??? -DaveM */ 286 #define PSYCHO_ECC_CTRL 0x0020 287 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ 288 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ 289 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ 290 static void psycho_register_error_handlers(struct pci_pbm_info *pbm) 291 { 292 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); 293 unsigned long base = pbm->controller_regs; 294 u64 tmp; 295 int err; 296 297 if (!op) 298 return; 299 300 /* Psycho interrupt property order is: 301 * 0: PCIERR INO for this PBM 302 * 1: UE ERR 303 * 2: CE ERR 304 * 3: POWER FAIL 305 * 4: SPARE HARDWARE 306 * 5: POWER MANAGEMENT 307 */ 308 309 if (op->archdata.num_irqs < 6) 310 return; 311 312 /* We really mean to ignore the return result here. Two 313 * PCI controller share the same interrupt numbers and 314 * drive the same front-end hardware. 315 */ 316 err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED, 317 "PSYCHO_UE", pbm); 318 err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED, 319 "PSYCHO_CE", pbm); 320 321 /* This one, however, ought not to fail. We can just warn 322 * about it since the system can still operate properly even 323 * if this fails. 324 */ 325 err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED, 326 "PSYCHO_PCIERR", pbm); 327 if (err) 328 printk(KERN_WARNING "%s: Could not register PCIERR, " 329 "err=%d\n", pbm->name, err); 330 331 /* Enable UE and CE interrupts for controller. */ 332 upa_writeq((PSYCHO_ECCCTRL_EE | 333 PSYCHO_ECCCTRL_UE | 334 PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL); 335 336 /* Enable PCI Error interrupts and clear error 337 * bits for each PBM. 338 */ 339 tmp = upa_readq(base + PSYCHO_PCIA_CTRL); 340 tmp |= (PSYCHO_PCICTRL_SERR | 341 PSYCHO_PCICTRL_SBH_ERR | 342 PSYCHO_PCICTRL_EEN); 343 tmp &= ~(PSYCHO_PCICTRL_SBH_INT); 344 upa_writeq(tmp, base + PSYCHO_PCIA_CTRL); 345 346 tmp = upa_readq(base + PSYCHO_PCIB_CTRL); 347 tmp |= (PSYCHO_PCICTRL_SERR | 348 PSYCHO_PCICTRL_SBH_ERR | 349 PSYCHO_PCICTRL_EEN); 350 tmp &= ~(PSYCHO_PCICTRL_SBH_INT); 351 upa_writeq(tmp, base + PSYCHO_PCIB_CTRL); 352 } 353 354 /* PSYCHO boot time probing and initialization. */ 355 static void pbm_config_busmastering(struct pci_pbm_info *pbm) 356 { 357 u8 *addr; 358 359 /* Set cache-line size to 64 bytes, this is actually 360 * a nop but I do it for completeness. 361 */ 362 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, 363 0, PCI_CACHE_LINE_SIZE); 364 pci_config_write8(addr, 64 / sizeof(u32)); 365 366 /* Set PBM latency timer to 64 PCI clocks. */ 367 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, 368 0, PCI_LATENCY_TIMER); 369 pci_config_write8(addr, 64); 370 } 371 372 static void psycho_scan_bus(struct pci_pbm_info *pbm, 373 struct device *parent) 374 { 375 pbm_config_busmastering(pbm); 376 pbm->is_66mhz_capable = 0; 377 pbm->pci_bus = pci_scan_one_pbm(pbm, parent); 378 379 /* After the PCI bus scan is complete, we can register 380 * the error interrupt handlers. 381 */ 382 psycho_register_error_handlers(pbm); 383 } 384 385 #define PSYCHO_IRQ_RETRY 0x1a00UL 386 #define PSYCHO_PCIA_DIAG 0x2020UL 387 #define PSYCHO_PCIB_DIAG 0x4020UL 388 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */ 389 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */ 390 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */ 391 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */ 392 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */ 393 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */ 394 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ 395 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ 396 397 static void psycho_controller_hwinit(struct pci_pbm_info *pbm) 398 { 399 u64 tmp; 400 401 upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY); 402 403 /* Enable arbiter for all PCI slots. */ 404 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL); 405 tmp |= PSYCHO_PCICTRL_AEN; 406 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL); 407 408 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL); 409 tmp |= PSYCHO_PCICTRL_AEN; 410 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL); 411 412 /* Disable DMA write / PIO read synchronization on 413 * both PCI bus segments. 414 * [ U2P Erratum 1243770, STP2223BGA data sheet ] 415 */ 416 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG); 417 tmp |= PSYCHO_PCIDIAG_DDWSYNC; 418 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG); 419 420 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG); 421 tmp |= PSYCHO_PCIDIAG_DDWSYNC; 422 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG); 423 } 424 425 static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, 426 int is_pbm_a) 427 { 428 unsigned long base = pbm->controller_regs; 429 u64 control; 430 431 if (is_pbm_a) { 432 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; 433 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; 434 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; 435 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A; 436 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A; 437 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A; 438 } else { 439 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; 440 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; 441 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; 442 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B; 443 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B; 444 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B; 445 } 446 /* PSYCHO's streaming buffer lacks ctx flushing. */ 447 pbm->stc.strbuf_ctxflush = 0; 448 pbm->stc.strbuf_ctxmatch_base = 0; 449 450 pbm->stc.strbuf_flushflag = (volatile unsigned long *) 451 ((((unsigned long)&pbm->stc.__flushflag_buf[0]) 452 + 63UL) 453 & ~63UL); 454 pbm->stc.strbuf_flushflag_pa = (unsigned long) 455 __pa(pbm->stc.strbuf_flushflag); 456 457 /* Enable the streaming buffer. We have to be careful 458 * just in case OBP left it with LRU locking enabled. 459 * 460 * It is possible to control if PBM will be rerun on 461 * line misses. Currently I just retain whatever setting 462 * OBP left us with. All checks so far show it having 463 * a value of zero. 464 */ 465 #undef PSYCHO_STRBUF_RERUN_ENABLE 466 #undef PSYCHO_STRBUF_RERUN_DISABLE 467 control = upa_readq(pbm->stc.strbuf_control); 468 control |= PSYCHO_STRBUF_CTRL_ENAB; 469 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); 470 #ifdef PSYCHO_STRBUF_RERUN_ENABLE 471 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); 472 #else 473 #ifdef PSYCHO_STRBUF_RERUN_DISABLE 474 control |= PSYCHO_STRBUF_CTRL_RRDIS; 475 #endif 476 #endif 477 upa_writeq(control, pbm->stc.strbuf_control); 478 479 pbm->stc.strbuf_enabled = 1; 480 } 481 482 #define PSYCHO_IOSPACE_A 0x002000000UL 483 #define PSYCHO_IOSPACE_B 0x002010000UL 484 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL 485 #define PSYCHO_MEMSPACE_A 0x100000000UL 486 #define PSYCHO_MEMSPACE_B 0x180000000UL 487 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL 488 489 static void psycho_pbm_init(struct pci_pbm_info *pbm, 490 struct platform_device *op, int is_pbm_a) 491 { 492 psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO); 493 psycho_pbm_strbuf_init(pbm, is_pbm_a); 494 psycho_scan_bus(pbm, &op->dev); 495 } 496 497 static struct pci_pbm_info *psycho_find_sibling(u32 upa_portid) 498 { 499 struct pci_pbm_info *pbm; 500 501 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 502 if (pbm->portid == upa_portid) 503 return pbm; 504 } 505 return NULL; 506 } 507 508 #define PSYCHO_CONFIGSPACE 0x001000000UL 509 510 static int psycho_probe(struct platform_device *op) 511 { 512 const struct linux_prom64_registers *pr_regs; 513 struct device_node *dp = op->dev.of_node; 514 struct pci_pbm_info *pbm; 515 struct iommu *iommu; 516 int is_pbm_a, err; 517 u32 upa_portid; 518 519 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); 520 521 err = -ENOMEM; 522 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); 523 if (!pbm) { 524 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); 525 goto out_err; 526 } 527 528 pbm->sibling = psycho_find_sibling(upa_portid); 529 if (pbm->sibling) { 530 iommu = pbm->sibling->iommu; 531 } else { 532 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); 533 if (!iommu) { 534 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); 535 goto out_free_controller; 536 } 537 } 538 539 pbm->iommu = iommu; 540 pbm->portid = upa_portid; 541 542 pr_regs = of_get_property(dp, "reg", NULL); 543 err = -ENODEV; 544 if (!pr_regs) { 545 printk(KERN_ERR PFX "No reg property.\n"); 546 goto out_free_iommu; 547 } 548 549 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); 550 551 pbm->controller_regs = pr_regs[2].phys_addr; 552 pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); 553 554 if (is_pbm_a) { 555 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A; 556 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A; 557 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL; 558 } else { 559 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B; 560 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B; 561 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL; 562 } 563 564 psycho_controller_hwinit(pbm); 565 if (!pbm->sibling) { 566 err = psycho_iommu_init(pbm, 128, 0xc0000000, 567 0xffffffff, PSYCHO_CONTROL); 568 if (err) 569 goto out_free_iommu; 570 571 /* If necessary, hook us up for starfire IRQ translations. */ 572 if (this_is_starfire) 573 starfire_hookup(pbm->portid); 574 } 575 576 psycho_pbm_init(pbm, op, is_pbm_a); 577 578 pbm->next = pci_pbm_root; 579 pci_pbm_root = pbm; 580 581 if (pbm->sibling) 582 pbm->sibling->sibling = pbm; 583 584 dev_set_drvdata(&op->dev, pbm); 585 586 return 0; 587 588 out_free_iommu: 589 if (!pbm->sibling) 590 kfree(pbm->iommu); 591 592 out_free_controller: 593 kfree(pbm); 594 595 out_err: 596 return err; 597 } 598 599 static const struct of_device_id psycho_match[] = { 600 { 601 .name = "pci", 602 .compatible = "pci108e,8000", 603 }, 604 {}, 605 }; 606 607 static struct platform_driver psycho_driver = { 608 .driver = { 609 .name = DRIVER_NAME, 610 .of_match_table = psycho_match, 611 }, 612 .probe = psycho_probe, 613 }; 614 615 static int __init psycho_init(void) 616 { 617 return platform_driver_register(&psycho_driver); 618 } 619 620 subsys_initcall(psycho_init); 621