xref: /openbmc/linux/arch/sparc/kernel/pci_impl.h (revision 7effbd18)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* pci_impl.h: Helper definitions for PCI controller support.
3  *
4  * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
5  */
6 
7 #ifndef PCI_IMPL_H
8 #define PCI_IMPL_H
9 
10 #include <linux/types.h>
11 #include <linux/spinlock.h>
12 #include <linux/pci.h>
13 #include <linux/msi.h>
14 #include <linux/of_device.h>
15 #include <asm/io.h>
16 #include <asm/prom.h>
17 #include <asm/iommu.h>
18 
19 /* The abstraction used here is that there are PCI controllers,
20  * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
21  * underneath.  Each PCI bus module uses an IOMMU (shared by both
22  * PBMs of a controller, or per-PBM), and if a streaming buffer
23  * is present, each PCI bus module has it's own. (ie. the IOMMU
24  * might be shared between PBMs, the STC is never shared)
25  * Furthermore, each PCI bus module controls it's own autonomous
26  * PCI bus.
27  */
28 
29 #define PCI_STC_FLUSHFLAG_INIT(STC) \
30 	(*((STC)->strbuf_flushflag) = 0UL)
31 #define PCI_STC_FLUSHFLAG_SET(STC) \
32 	(*((STC)->strbuf_flushflag) != 0UL)
33 
34 #ifdef CONFIG_PCI_MSI
35 struct pci_pbm_info;
36 struct sparc64_msiq_ops {
37 	int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
38 			unsigned long *head);
39 	int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid,
40 			   unsigned long *head, unsigned long *msi);
41 	int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
42 			unsigned long head);
43 	int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid,
44 			 unsigned long msi, int is_msi64);
45 	int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi);
46 	int (*msiq_alloc)(struct pci_pbm_info *pbm);
47 	void (*msiq_free)(struct pci_pbm_info *pbm);
48 	int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid,
49 			      unsigned long devino);
50 };
51 
52 void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
53 			  const struct sparc64_msiq_ops *ops);
54 
55 struct sparc64_msiq_cookie {
56 	struct pci_pbm_info *pbm;
57 	unsigned long msiqid;
58 };
59 #endif
60 
61 struct pci_pbm_info {
62 	struct pci_pbm_info		*next;
63 	struct pci_pbm_info		*sibling;
64 	int				index;
65 
66 	/* Physical address base of controller registers. */
67 	unsigned long			controller_regs;
68 
69 	/* Physical address base of PBM registers. */
70 	unsigned long			pbm_regs;
71 
72 	/* Physical address of DMA sync register, if any.  */
73 	unsigned long			sync_reg;
74 
75 	/* Opaque 32-bit system bus Port ID. */
76 	u32				portid;
77 
78 	/* Opaque 32-bit handle used for hypervisor calls.  */
79 	u32				devhandle;
80 
81 	/* Chipset version information. */
82 	int				chip_type;
83 #define PBM_CHIP_TYPE_SABRE		1
84 #define PBM_CHIP_TYPE_PSYCHO		2
85 #define PBM_CHIP_TYPE_SCHIZO		3
86 #define PBM_CHIP_TYPE_SCHIZO_PLUS	4
87 #define PBM_CHIP_TYPE_TOMATILLO		5
88 	int				chip_version;
89 	int				chip_revision;
90 
91 	/* Name used for top-level resources. */
92 	const char			*name;
93 
94 	/* OBP specific information. */
95 	struct platform_device		*op;
96 	u64				ino_bitmap;
97 
98 	/* PBM I/O and Memory space resources. */
99 	struct resource			io_space;
100 	struct resource			mem_space;
101 	struct resource			mem64_space;
102 	struct resource			busn;
103 	/* offset */
104 	resource_size_t			io_offset;
105 	resource_size_t			mem_offset;
106 	resource_size_t			mem64_offset;
107 
108 	/* Base of PCI Config space, can be per-PBM or shared. */
109 	unsigned long			config_space;
110 
111 	/* This will be 12 on PCI-E controllers, 8 elsewhere.  */
112 	unsigned long			config_space_reg_bits;
113 
114 	unsigned long			pci_afsr;
115 	unsigned long			pci_afar;
116 	unsigned long			pci_csr;
117 
118 	/* State of 66MHz capabilities on this PBM. */
119 	int				is_66mhz_capable;
120 	int				all_devs_66mhz;
121 
122 #ifdef CONFIG_PCI_MSI
123 	/* MSI info.  */
124 	u32				msiq_num;
125 	u32				msiq_ent_count;
126 	u32				msiq_first;
127 	u32				msiq_first_devino;
128 	u32				msiq_rotor;
129 	struct sparc64_msiq_cookie	*msiq_irq_cookies;
130 	u32				msi_num;
131 	u32				msi_first;
132 	u32				msi_data_mask;
133 	u32				msix_data_width;
134 	u64				msi32_start;
135 	u64				msi64_start;
136 	u32				msi32_len;
137 	u32				msi64_len;
138 	void				*msi_queues;
139 	unsigned long			*msi_bitmap;
140 	unsigned int			*msi_irq_table;
141 	int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev,
142 			     struct msi_desc *entry);
143 	void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev);
144 	const struct sparc64_msiq_ops	*msi_ops;
145 #endif /* !(CONFIG_PCI_MSI) */
146 
147 	/* This PBM's streaming buffer. */
148 	struct strbuf			stc;
149 
150 	/* IOMMU state, potentially shared by both PBM segments. */
151 	struct iommu			*iommu;
152 
153 	/* Now things for the actual PCI bus probes. */
154 	unsigned int			pci_first_busno;
155 	unsigned int			pci_last_busno;
156 	struct pci_bus			*pci_bus;
157 	struct pci_ops			*pci_ops;
158 
159 	int				numa_node;
160 };
161 
162 extern struct pci_pbm_info *pci_pbm_root;
163 
164 extern int pci_num_pbms;
165 
166 /* PCI bus scanning and fixup support. */
167 void pci_get_pbm_props(struct pci_pbm_info *pbm);
168 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
169 				 struct device *parent);
170 void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
171 
172 /* Error reporting support. */
173 void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
174 void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
175 void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
176 
177 /* Configuration space access. */
178 void pci_config_read8(u8 *addr, u8 *ret);
179 void pci_config_read16(u16 *addr, u16 *ret);
180 void pci_config_read32(u32 *addr, u32 *ret);
181 void pci_config_write8(u8 *addr, u8 val);
182 void pci_config_write16(u16 *addr, u16 val);
183 void pci_config_write32(u32 *addr, u32 val);
184 
185 extern struct pci_ops sun4u_pci_ops;
186 extern struct pci_ops sun4v_pci_ops;
187 
188 extern volatile int pci_poke_in_progress;
189 extern volatile int pci_poke_cpu;
190 extern volatile int pci_poke_faulted;
191 
192 #endif /* !(PCI_IMPL_H) */
193