1 /* pci.c: UltraSparc PCI controller support. 2 * 3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) 6 * 7 * OF tree based PCI bus probing taken from the PowerPC port 8 * with minor modifications, see there for credits. 9 */ 10 11 #include <linux/export.h> 12 #include <linux/kernel.h> 13 #include <linux/string.h> 14 #include <linux/sched.h> 15 #include <linux/capability.h> 16 #include <linux/errno.h> 17 #include <linux/pci.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 24 #include <asm/uaccess.h> 25 #include <asm/pgtable.h> 26 #include <asm/irq.h> 27 #include <asm/prom.h> 28 #include <asm/apb.h> 29 30 #include "pci_impl.h" 31 #include "kernel.h" 32 33 /* List of all PCI controllers found in the system. */ 34 struct pci_pbm_info *pci_pbm_root = NULL; 35 36 /* Each PBM found gets a unique index. */ 37 int pci_num_pbms = 0; 38 39 volatile int pci_poke_in_progress; 40 volatile int pci_poke_cpu = -1; 41 volatile int pci_poke_faulted; 42 43 static DEFINE_SPINLOCK(pci_poke_lock); 44 45 void pci_config_read8(u8 *addr, u8 *ret) 46 { 47 unsigned long flags; 48 u8 byte; 49 50 spin_lock_irqsave(&pci_poke_lock, flags); 51 pci_poke_cpu = smp_processor_id(); 52 pci_poke_in_progress = 1; 53 pci_poke_faulted = 0; 54 __asm__ __volatile__("membar #Sync\n\t" 55 "lduba [%1] %2, %0\n\t" 56 "membar #Sync" 57 : "=r" (byte) 58 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 59 : "memory"); 60 pci_poke_in_progress = 0; 61 pci_poke_cpu = -1; 62 if (!pci_poke_faulted) 63 *ret = byte; 64 spin_unlock_irqrestore(&pci_poke_lock, flags); 65 } 66 67 void pci_config_read16(u16 *addr, u16 *ret) 68 { 69 unsigned long flags; 70 u16 word; 71 72 spin_lock_irqsave(&pci_poke_lock, flags); 73 pci_poke_cpu = smp_processor_id(); 74 pci_poke_in_progress = 1; 75 pci_poke_faulted = 0; 76 __asm__ __volatile__("membar #Sync\n\t" 77 "lduha [%1] %2, %0\n\t" 78 "membar #Sync" 79 : "=r" (word) 80 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 81 : "memory"); 82 pci_poke_in_progress = 0; 83 pci_poke_cpu = -1; 84 if (!pci_poke_faulted) 85 *ret = word; 86 spin_unlock_irqrestore(&pci_poke_lock, flags); 87 } 88 89 void pci_config_read32(u32 *addr, u32 *ret) 90 { 91 unsigned long flags; 92 u32 dword; 93 94 spin_lock_irqsave(&pci_poke_lock, flags); 95 pci_poke_cpu = smp_processor_id(); 96 pci_poke_in_progress = 1; 97 pci_poke_faulted = 0; 98 __asm__ __volatile__("membar #Sync\n\t" 99 "lduwa [%1] %2, %0\n\t" 100 "membar #Sync" 101 : "=r" (dword) 102 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 103 : "memory"); 104 pci_poke_in_progress = 0; 105 pci_poke_cpu = -1; 106 if (!pci_poke_faulted) 107 *ret = dword; 108 spin_unlock_irqrestore(&pci_poke_lock, flags); 109 } 110 111 void pci_config_write8(u8 *addr, u8 val) 112 { 113 unsigned long flags; 114 115 spin_lock_irqsave(&pci_poke_lock, flags); 116 pci_poke_cpu = smp_processor_id(); 117 pci_poke_in_progress = 1; 118 pci_poke_faulted = 0; 119 __asm__ __volatile__("membar #Sync\n\t" 120 "stba %0, [%1] %2\n\t" 121 "membar #Sync" 122 : /* no outputs */ 123 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 124 : "memory"); 125 pci_poke_in_progress = 0; 126 pci_poke_cpu = -1; 127 spin_unlock_irqrestore(&pci_poke_lock, flags); 128 } 129 130 void pci_config_write16(u16 *addr, u16 val) 131 { 132 unsigned long flags; 133 134 spin_lock_irqsave(&pci_poke_lock, flags); 135 pci_poke_cpu = smp_processor_id(); 136 pci_poke_in_progress = 1; 137 pci_poke_faulted = 0; 138 __asm__ __volatile__("membar #Sync\n\t" 139 "stha %0, [%1] %2\n\t" 140 "membar #Sync" 141 : /* no outputs */ 142 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 143 : "memory"); 144 pci_poke_in_progress = 0; 145 pci_poke_cpu = -1; 146 spin_unlock_irqrestore(&pci_poke_lock, flags); 147 } 148 149 void pci_config_write32(u32 *addr, u32 val) 150 { 151 unsigned long flags; 152 153 spin_lock_irqsave(&pci_poke_lock, flags); 154 pci_poke_cpu = smp_processor_id(); 155 pci_poke_in_progress = 1; 156 pci_poke_faulted = 0; 157 __asm__ __volatile__("membar #Sync\n\t" 158 "stwa %0, [%1] %2\n\t" 159 "membar #Sync" 160 : /* no outputs */ 161 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 162 : "memory"); 163 pci_poke_in_progress = 0; 164 pci_poke_cpu = -1; 165 spin_unlock_irqrestore(&pci_poke_lock, flags); 166 } 167 168 static int ofpci_verbose; 169 170 static int __init ofpci_debug(char *str) 171 { 172 int val = 0; 173 174 get_option(&str, &val); 175 if (val) 176 ofpci_verbose = 1; 177 return 1; 178 } 179 180 __setup("ofpci_debug=", ofpci_debug); 181 182 static unsigned long pci_parse_of_flags(u32 addr0) 183 { 184 unsigned long flags = 0; 185 186 if (addr0 & 0x02000000) { 187 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; 188 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; 189 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; 190 if (addr0 & 0x40000000) 191 flags |= IORESOURCE_PREFETCH 192 | PCI_BASE_ADDRESS_MEM_PREFETCH; 193 } else if (addr0 & 0x01000000) 194 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 195 return flags; 196 } 197 198 /* The of_device layer has translated all of the assigned-address properties 199 * into physical address resources, we only have to figure out the register 200 * mapping. 201 */ 202 static void pci_parse_of_addrs(struct platform_device *op, 203 struct device_node *node, 204 struct pci_dev *dev) 205 { 206 struct resource *op_res; 207 const u32 *addrs; 208 int proplen; 209 210 addrs = of_get_property(node, "assigned-addresses", &proplen); 211 if (!addrs) 212 return; 213 if (ofpci_verbose) 214 printk(" parse addresses (%d bytes) @ %p\n", 215 proplen, addrs); 216 op_res = &op->resource[0]; 217 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { 218 struct resource *res; 219 unsigned long flags; 220 int i; 221 222 flags = pci_parse_of_flags(addrs[0]); 223 if (!flags) 224 continue; 225 i = addrs[0] & 0xff; 226 if (ofpci_verbose) 227 printk(" start: %llx, end: %llx, i: %x\n", 228 op_res->start, op_res->end, i); 229 230 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { 231 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; 232 } else if (i == dev->rom_base_reg) { 233 res = &dev->resource[PCI_ROM_RESOURCE]; 234 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE 235 | IORESOURCE_SIZEALIGN; 236 } else { 237 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); 238 continue; 239 } 240 res->start = op_res->start; 241 res->end = op_res->end; 242 res->flags = flags; 243 res->name = pci_name(dev); 244 } 245 } 246 247 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, 248 struct device_node *node, 249 struct pci_bus *bus, int devfn) 250 { 251 struct dev_archdata *sd; 252 struct pci_slot *slot; 253 struct platform_device *op; 254 struct pci_dev *dev; 255 const char *type; 256 u32 class; 257 258 dev = pci_alloc_dev(bus); 259 if (!dev) 260 return NULL; 261 262 sd = &dev->dev.archdata; 263 sd->iommu = pbm->iommu; 264 sd->stc = &pbm->stc; 265 sd->host_controller = pbm; 266 sd->op = op = of_find_device_by_node(node); 267 sd->numa_node = pbm->numa_node; 268 269 sd = &op->dev.archdata; 270 sd->iommu = pbm->iommu; 271 sd->stc = &pbm->stc; 272 sd->numa_node = pbm->numa_node; 273 274 if (!strcmp(node->name, "ebus")) 275 of_propagate_archdata(op); 276 277 type = of_get_property(node, "device_type", NULL); 278 if (type == NULL) 279 type = ""; 280 281 if (ofpci_verbose) 282 printk(" create device, devfn: %x, type: %s\n", 283 devfn, type); 284 285 dev->sysdata = node; 286 dev->dev.parent = bus->bridge; 287 dev->dev.bus = &pci_bus_type; 288 dev->dev.of_node = of_node_get(node); 289 dev->devfn = devfn; 290 dev->multifunction = 0; /* maybe a lie? */ 291 set_pcie_port_type(dev); 292 293 list_for_each_entry(slot, &dev->bus->slots, list) 294 if (PCI_SLOT(dev->devfn) == slot->number) 295 dev->slot = slot; 296 297 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); 298 dev->device = of_getintprop_default(node, "device-id", 0xffff); 299 dev->subsystem_vendor = 300 of_getintprop_default(node, "subsystem-vendor-id", 0); 301 dev->subsystem_device = 302 of_getintprop_default(node, "subsystem-id", 0); 303 304 dev->cfg_size = pci_cfg_space_size(dev); 305 306 /* We can't actually use the firmware value, we have 307 * to read what is in the register right now. One 308 * reason is that in the case of IDE interfaces the 309 * firmware can sample the value before the the IDE 310 * interface is programmed into native mode. 311 */ 312 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 313 dev->class = class >> 8; 314 dev->revision = class & 0xff; 315 316 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), 317 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 318 319 if (ofpci_verbose) 320 printk(" class: 0x%x device name: %s\n", 321 dev->class, pci_name(dev)); 322 323 /* I have seen IDE devices which will not respond to 324 * the bmdma simplex check reads if bus mastering is 325 * disabled. 326 */ 327 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) 328 pci_set_master(dev); 329 330 dev->current_state = PCI_UNKNOWN; /* unknown power state */ 331 dev->error_state = pci_channel_io_normal; 332 dev->dma_mask = 0xffffffff; 333 334 if (!strcmp(node->name, "pci")) { 335 /* a PCI-PCI bridge */ 336 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 337 dev->rom_base_reg = PCI_ROM_ADDRESS1; 338 } else if (!strcmp(type, "cardbus")) { 339 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; 340 } else { 341 dev->hdr_type = PCI_HEADER_TYPE_NORMAL; 342 dev->rom_base_reg = PCI_ROM_ADDRESS; 343 344 dev->irq = sd->op->archdata.irqs[0]; 345 if (dev->irq == 0xffffffff) 346 dev->irq = PCI_IRQ_NONE; 347 } 348 349 pci_parse_of_addrs(sd->op, node, dev); 350 351 if (ofpci_verbose) 352 printk(" adding to system ...\n"); 353 354 pci_device_add(dev, bus); 355 356 return dev; 357 } 358 359 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) 360 { 361 u32 idx, first, last; 362 363 first = 8; 364 last = 0; 365 for (idx = 0; idx < 8; idx++) { 366 if ((map & (1 << idx)) != 0) { 367 if (first > idx) 368 first = idx; 369 if (last < idx) 370 last = idx; 371 } 372 } 373 374 *first_p = first; 375 *last_p = last; 376 } 377 378 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack 379 * a proper 'ranges' property. 380 */ 381 static void apb_fake_ranges(struct pci_dev *dev, 382 struct pci_bus *bus, 383 struct pci_pbm_info *pbm) 384 { 385 struct pci_bus_region region; 386 struct resource *res; 387 u32 first, last; 388 u8 map; 389 390 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); 391 apb_calc_first_last(map, &first, &last); 392 res = bus->resource[0]; 393 res->flags = IORESOURCE_IO; 394 region.start = (first << 21); 395 region.end = (last << 21) + ((1 << 21) - 1); 396 pcibios_bus_to_resource(dev->bus, res, ®ion); 397 398 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); 399 apb_calc_first_last(map, &first, &last); 400 res = bus->resource[1]; 401 res->flags = IORESOURCE_MEM; 402 region.start = (first << 29); 403 region.end = (last << 29) + ((1 << 29) - 1); 404 pcibios_bus_to_resource(dev->bus, res, ®ion); 405 } 406 407 static void pci_of_scan_bus(struct pci_pbm_info *pbm, 408 struct device_node *node, 409 struct pci_bus *bus); 410 411 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) 412 413 static void of_scan_pci_bridge(struct pci_pbm_info *pbm, 414 struct device_node *node, 415 struct pci_dev *dev) 416 { 417 struct pci_bus *bus; 418 const u32 *busrange, *ranges; 419 int len, i, simba; 420 struct pci_bus_region region; 421 struct resource *res; 422 unsigned int flags; 423 u64 size; 424 425 if (ofpci_verbose) 426 printk("of_scan_pci_bridge(%s)\n", node->full_name); 427 428 /* parse bus-range property */ 429 busrange = of_get_property(node, "bus-range", &len); 430 if (busrange == NULL || len != 8) { 431 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", 432 node->full_name); 433 return; 434 } 435 ranges = of_get_property(node, "ranges", &len); 436 simba = 0; 437 if (ranges == NULL) { 438 const char *model = of_get_property(node, "model", NULL); 439 if (model && !strcmp(model, "SUNW,simba")) 440 simba = 1; 441 } 442 443 bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 444 if (!bus) { 445 printk(KERN_ERR "Failed to create pci bus for %s\n", 446 node->full_name); 447 return; 448 } 449 450 bus->primary = dev->bus->number; 451 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]); 452 bus->bridge_ctl = 0; 453 454 /* parse ranges property, or cook one up by hand for Simba */ 455 /* PCI #address-cells == 3 and #size-cells == 2 always */ 456 res = &dev->resource[PCI_BRIDGE_RESOURCES]; 457 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { 458 res->flags = 0; 459 bus->resource[i] = res; 460 ++res; 461 } 462 if (simba) { 463 apb_fake_ranges(dev, bus, pbm); 464 goto after_ranges; 465 } else if (ranges == NULL) { 466 pci_read_bridge_bases(bus); 467 goto after_ranges; 468 } 469 i = 1; 470 for (; len >= 32; len -= 32, ranges += 8) { 471 flags = pci_parse_of_flags(ranges[0]); 472 size = GET_64BIT(ranges, 6); 473 if (flags == 0 || size == 0) 474 continue; 475 if (flags & IORESOURCE_IO) { 476 res = bus->resource[0]; 477 if (res->flags) { 478 printk(KERN_ERR "PCI: ignoring extra I/O range" 479 " for bridge %s\n", node->full_name); 480 continue; 481 } 482 } else { 483 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { 484 printk(KERN_ERR "PCI: too many memory ranges" 485 " for bridge %s\n", node->full_name); 486 continue; 487 } 488 res = bus->resource[i]; 489 ++i; 490 } 491 492 res->flags = flags; 493 region.start = GET_64BIT(ranges, 1); 494 region.end = region.start + size - 1; 495 pcibios_bus_to_resource(dev->bus, res, ®ion); 496 } 497 after_ranges: 498 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 499 bus->number); 500 if (ofpci_verbose) 501 printk(" bus name: %s\n", bus->name); 502 503 pci_of_scan_bus(pbm, node, bus); 504 } 505 506 static void pci_of_scan_bus(struct pci_pbm_info *pbm, 507 struct device_node *node, 508 struct pci_bus *bus) 509 { 510 struct device_node *child; 511 const u32 *reg; 512 int reglen, devfn, prev_devfn; 513 struct pci_dev *dev; 514 515 if (ofpci_verbose) 516 printk("PCI: scan_bus[%s] bus no %d\n", 517 node->full_name, bus->number); 518 519 child = NULL; 520 prev_devfn = -1; 521 while ((child = of_get_next_child(node, child)) != NULL) { 522 if (ofpci_verbose) 523 printk(" * %s\n", child->full_name); 524 reg = of_get_property(child, "reg", ®len); 525 if (reg == NULL || reglen < 20) 526 continue; 527 528 devfn = (reg[0] >> 8) & 0xff; 529 530 /* This is a workaround for some device trees 531 * which list PCI devices twice. On the V100 532 * for example, device number 3 is listed twice. 533 * Once as "pm" and once again as "lomp". 534 */ 535 if (devfn == prev_devfn) 536 continue; 537 prev_devfn = devfn; 538 539 /* create a new pci_dev for this device */ 540 dev = of_create_pci_dev(pbm, child, bus, devfn); 541 if (!dev) 542 continue; 543 if (ofpci_verbose) 544 printk("PCI: dev header type: %x\n", 545 dev->hdr_type); 546 547 if (pci_is_bridge(dev)) 548 of_scan_pci_bridge(pbm, child, dev); 549 } 550 } 551 552 static ssize_t 553 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) 554 { 555 struct pci_dev *pdev; 556 struct device_node *dp; 557 558 pdev = to_pci_dev(dev); 559 dp = pdev->dev.of_node; 560 561 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); 562 } 563 564 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); 565 566 static void pci_bus_register_of_sysfs(struct pci_bus *bus) 567 { 568 struct pci_dev *dev; 569 struct pci_bus *child_bus; 570 int err; 571 572 list_for_each_entry(dev, &bus->devices, bus_list) { 573 /* we don't really care if we can create this file or 574 * not, but we need to assign the result of the call 575 * or the world will fall under alien invasion and 576 * everybody will be frozen on a spaceship ready to be 577 * eaten on alpha centauri by some green and jelly 578 * humanoid. 579 */ 580 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); 581 (void) err; 582 } 583 list_for_each_entry(child_bus, &bus->children, node) 584 pci_bus_register_of_sysfs(child_bus); 585 } 586 587 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm, 588 struct device *parent) 589 { 590 LIST_HEAD(resources); 591 struct device_node *node = pbm->op->dev.of_node; 592 struct pci_bus *bus; 593 594 printk("PCI: Scanning PBM %s\n", node->full_name); 595 596 pci_add_resource_offset(&resources, &pbm->io_space, 597 pbm->io_space.start); 598 pci_add_resource_offset(&resources, &pbm->mem_space, 599 pbm->mem_space.start); 600 pbm->busn.start = pbm->pci_first_busno; 601 pbm->busn.end = pbm->pci_last_busno; 602 pbm->busn.flags = IORESOURCE_BUS; 603 pci_add_resource(&resources, &pbm->busn); 604 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops, 605 pbm, &resources); 606 if (!bus) { 607 printk(KERN_ERR "Failed to create bus for %s\n", 608 node->full_name); 609 pci_free_resource_list(&resources); 610 return NULL; 611 } 612 613 pci_of_scan_bus(pbm, node, bus); 614 pci_bus_add_devices(bus); 615 pci_bus_register_of_sysfs(bus); 616 617 return bus; 618 } 619 620 void pcibios_fixup_bus(struct pci_bus *pbus) 621 { 622 } 623 624 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 625 resource_size_t size, resource_size_t align) 626 { 627 return res->start; 628 } 629 630 int pcibios_enable_device(struct pci_dev *dev, int mask) 631 { 632 u16 cmd, oldcmd; 633 int i; 634 635 pci_read_config_word(dev, PCI_COMMAND, &cmd); 636 oldcmd = cmd; 637 638 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 639 struct resource *res = &dev->resource[i]; 640 641 /* Only set up the requested stuff */ 642 if (!(mask & (1<<i))) 643 continue; 644 645 if (res->flags & IORESOURCE_IO) 646 cmd |= PCI_COMMAND_IO; 647 if (res->flags & IORESOURCE_MEM) 648 cmd |= PCI_COMMAND_MEMORY; 649 } 650 651 if (cmd != oldcmd) { 652 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", 653 pci_name(dev), cmd); 654 /* Enable the appropriate bits in the PCI command register. */ 655 pci_write_config_word(dev, PCI_COMMAND, cmd); 656 } 657 return 0; 658 } 659 660 /* Platform support for /proc/bus/pci/X/Y mmap()s. */ 661 662 /* If the user uses a host-bridge as the PCI device, he may use 663 * this to perform a raw mmap() of the I/O or MEM space behind 664 * that controller. 665 * 666 * This can be useful for execution of x86 PCI bios initialization code 667 * on a PCI card, like the xfree86 int10 stuff does. 668 */ 669 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, 670 enum pci_mmap_state mmap_state) 671 { 672 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 673 unsigned long space_size, user_offset, user_size; 674 675 if (mmap_state == pci_mmap_io) { 676 space_size = resource_size(&pbm->io_space); 677 } else { 678 space_size = resource_size(&pbm->mem_space); 679 } 680 681 /* Make sure the request is in range. */ 682 user_offset = vma->vm_pgoff << PAGE_SHIFT; 683 user_size = vma->vm_end - vma->vm_start; 684 685 if (user_offset >= space_size || 686 (user_offset + user_size) > space_size) 687 return -EINVAL; 688 689 if (mmap_state == pci_mmap_io) { 690 vma->vm_pgoff = (pbm->io_space.start + 691 user_offset) >> PAGE_SHIFT; 692 } else { 693 vma->vm_pgoff = (pbm->mem_space.start + 694 user_offset) >> PAGE_SHIFT; 695 } 696 697 return 0; 698 } 699 700 /* Adjust vm_pgoff of VMA such that it is the physical page offset 701 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 702 * 703 * Basically, the user finds the base address for his device which he wishes 704 * to mmap. They read the 32-bit value from the config space base register, 705 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 706 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 707 * 708 * Returns negative error code on failure, zero on success. 709 */ 710 static int __pci_mmap_make_offset(struct pci_dev *pdev, 711 struct vm_area_struct *vma, 712 enum pci_mmap_state mmap_state) 713 { 714 unsigned long user_paddr, user_size; 715 int i, err; 716 717 /* First compute the physical address in vma->vm_pgoff, 718 * making sure the user offset is within range in the 719 * appropriate PCI space. 720 */ 721 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state); 722 if (err) 723 return err; 724 725 /* If this is a mapping on a host bridge, any address 726 * is OK. 727 */ 728 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST) 729 return err; 730 731 /* Otherwise make sure it's in the range for one of the 732 * device's resources. 733 */ 734 user_paddr = vma->vm_pgoff << PAGE_SHIFT; 735 user_size = vma->vm_end - vma->vm_start; 736 737 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 738 struct resource *rp = &pdev->resource[i]; 739 resource_size_t aligned_end; 740 741 /* Active? */ 742 if (!rp->flags) 743 continue; 744 745 /* Same type? */ 746 if (i == PCI_ROM_RESOURCE) { 747 if (mmap_state != pci_mmap_mem) 748 continue; 749 } else { 750 if ((mmap_state == pci_mmap_io && 751 (rp->flags & IORESOURCE_IO) == 0) || 752 (mmap_state == pci_mmap_mem && 753 (rp->flags & IORESOURCE_MEM) == 0)) 754 continue; 755 } 756 757 /* Align the resource end to the next page address. 758 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1), 759 * because actually we need the address of the next byte 760 * after rp->end. 761 */ 762 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK; 763 764 if ((rp->start <= user_paddr) && 765 (user_paddr + user_size) <= aligned_end) 766 break; 767 } 768 769 if (i > PCI_ROM_RESOURCE) 770 return -EINVAL; 771 772 return 0; 773 } 774 775 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 776 * device mapping. 777 */ 778 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, 779 enum pci_mmap_state mmap_state) 780 { 781 /* Our io_remap_pfn_range takes care of this, do nothing. */ 782 } 783 784 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate 785 * for this architecture. The region in the process to map is described by vm_start 786 * and vm_end members of VMA, the base physical address is found in vm_pgoff. 787 * The pci device structure is provided so that architectures may make mapping 788 * decisions on a per-device or per-bus basis. 789 * 790 * Returns a negative error code on failure, zero on success. 791 */ 792 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 793 enum pci_mmap_state mmap_state, 794 int write_combine) 795 { 796 int ret; 797 798 ret = __pci_mmap_make_offset(dev, vma, mmap_state); 799 if (ret < 0) 800 return ret; 801 802 __pci_mmap_set_pgprot(dev, vma, mmap_state); 803 804 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 805 ret = io_remap_pfn_range(vma, vma->vm_start, 806 vma->vm_pgoff, 807 vma->vm_end - vma->vm_start, 808 vma->vm_page_prot); 809 if (ret) 810 return ret; 811 812 return 0; 813 } 814 815 #ifdef CONFIG_NUMA 816 int pcibus_to_node(struct pci_bus *pbus) 817 { 818 struct pci_pbm_info *pbm = pbus->sysdata; 819 820 return pbm->numa_node; 821 } 822 EXPORT_SYMBOL(pcibus_to_node); 823 #endif 824 825 /* Return the domain number for this pci bus */ 826 827 int pci_domain_nr(struct pci_bus *pbus) 828 { 829 struct pci_pbm_info *pbm = pbus->sysdata; 830 int ret; 831 832 if (!pbm) { 833 ret = -ENXIO; 834 } else { 835 ret = pbm->index; 836 } 837 838 return ret; 839 } 840 EXPORT_SYMBOL(pci_domain_nr); 841 842 #ifdef CONFIG_PCI_MSI 843 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 844 { 845 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 846 unsigned int irq; 847 848 if (!pbm->setup_msi_irq) 849 return -EINVAL; 850 851 return pbm->setup_msi_irq(&irq, pdev, desc); 852 } 853 854 void arch_teardown_msi_irq(unsigned int irq) 855 { 856 struct msi_desc *entry = irq_get_msi_desc(irq); 857 struct pci_dev *pdev = entry->dev; 858 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 859 860 if (pbm->teardown_msi_irq) 861 pbm->teardown_msi_irq(irq, pdev); 862 } 863 #endif /* !(CONFIG_PCI_MSI) */ 864 865 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) 866 { 867 struct pci_dev *ali_isa_bridge; 868 u8 val; 869 870 /* ALI sound chips generate 31-bits of DMA, a special register 871 * determines what bit 31 is emitted as. 872 */ 873 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, 874 PCI_DEVICE_ID_AL_M1533, 875 NULL); 876 877 pci_read_config_byte(ali_isa_bridge, 0x7e, &val); 878 if (set_bit) 879 val |= 0x01; 880 else 881 val &= ~0x01; 882 pci_write_config_byte(ali_isa_bridge, 0x7e, val); 883 pci_dev_put(ali_isa_bridge); 884 } 885 886 int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask) 887 { 888 u64 dma_addr_mask; 889 890 if (pdev == NULL) { 891 dma_addr_mask = 0xffffffff; 892 } else { 893 struct iommu *iommu = pdev->dev.archdata.iommu; 894 895 dma_addr_mask = iommu->dma_addr_mask; 896 897 if (pdev->vendor == PCI_VENDOR_ID_AL && 898 pdev->device == PCI_DEVICE_ID_AL_M5451 && 899 device_mask == 0x7fffffff) { 900 ali_sound_dma_hack(pdev, 901 (dma_addr_mask & 0x80000000) != 0); 902 return 1; 903 } 904 } 905 906 if (device_mask >= (1UL << 32UL)) 907 return 0; 908 909 return (device_mask & dma_addr_mask) == dma_addr_mask; 910 } 911 912 void pci_resource_to_user(const struct pci_dev *pdev, int bar, 913 const struct resource *rp, resource_size_t *start, 914 resource_size_t *end) 915 { 916 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 917 unsigned long offset; 918 919 if (rp->flags & IORESOURCE_IO) 920 offset = pbm->io_space.start; 921 else 922 offset = pbm->mem_space.start; 923 924 *start = rp->start - offset; 925 *end = rp->end - offset; 926 } 927 928 void pcibios_set_master(struct pci_dev *dev) 929 { 930 /* No special bus mastering setup handling */ 931 } 932 933 static int __init pcibios_init(void) 934 { 935 pci_dfl_cache_line_size = 64 >> 2; 936 return 0; 937 } 938 subsys_initcall(pcibios_init); 939 940 #ifdef CONFIG_SYSFS 941 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus) 942 { 943 const struct pci_slot_names { 944 u32 slot_mask; 945 char names[0]; 946 } *prop; 947 const char *sp; 948 int len, i; 949 u32 mask; 950 951 prop = of_get_property(node, "slot-names", &len); 952 if (!prop) 953 return; 954 955 mask = prop->slot_mask; 956 sp = prop->names; 957 958 if (ofpci_verbose) 959 printk("PCI: Making slots for [%s] mask[0x%02x]\n", 960 node->full_name, mask); 961 962 i = 0; 963 while (mask) { 964 struct pci_slot *pci_slot; 965 u32 this_bit = 1 << i; 966 967 if (!(mask & this_bit)) { 968 i++; 969 continue; 970 } 971 972 if (ofpci_verbose) 973 printk("PCI: Making slot [%s]\n", sp); 974 975 pci_slot = pci_create_slot(bus, i, sp, NULL); 976 if (IS_ERR(pci_slot)) 977 printk(KERN_ERR "PCI: pci_create_slot returned %ld\n", 978 PTR_ERR(pci_slot)); 979 980 sp += strlen(sp) + 1; 981 mask &= ~this_bit; 982 i++; 983 } 984 } 985 986 static int __init of_pci_slot_init(void) 987 { 988 struct pci_bus *pbus = NULL; 989 990 while ((pbus = pci_find_next_bus(pbus)) != NULL) { 991 struct device_node *node; 992 993 if (pbus->self) { 994 /* PCI->PCI bridge */ 995 node = pbus->self->dev.of_node; 996 } else { 997 struct pci_pbm_info *pbm = pbus->sysdata; 998 999 /* Host PCI controller */ 1000 node = pbm->op->dev.of_node; 1001 } 1002 1003 pci_bus_slot_names(node, pbus); 1004 } 1005 1006 return 0; 1007 } 1008 device_initcall(of_pci_slot_init); 1009 #endif 1010