1 /* pci.c: UltraSparc PCI controller support. 2 * 3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) 6 * 7 * OF tree based PCI bus probing taken from the PowerPC port 8 * with minor modifications, see there for credits. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/string.h> 14 #include <linux/sched.h> 15 #include <linux/capability.h> 16 #include <linux/errno.h> 17 #include <linux/pci.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 24 #include <asm/uaccess.h> 25 #include <asm/pgtable.h> 26 #include <asm/irq.h> 27 #include <asm/prom.h> 28 #include <asm/apb.h> 29 30 #include "pci_impl.h" 31 32 /* List of all PCI controllers found in the system. */ 33 struct pci_pbm_info *pci_pbm_root = NULL; 34 35 /* Each PBM found gets a unique index. */ 36 int pci_num_pbms = 0; 37 38 volatile int pci_poke_in_progress; 39 volatile int pci_poke_cpu = -1; 40 volatile int pci_poke_faulted; 41 42 static DEFINE_SPINLOCK(pci_poke_lock); 43 44 void pci_config_read8(u8 *addr, u8 *ret) 45 { 46 unsigned long flags; 47 u8 byte; 48 49 spin_lock_irqsave(&pci_poke_lock, flags); 50 pci_poke_cpu = smp_processor_id(); 51 pci_poke_in_progress = 1; 52 pci_poke_faulted = 0; 53 __asm__ __volatile__("membar #Sync\n\t" 54 "lduba [%1] %2, %0\n\t" 55 "membar #Sync" 56 : "=r" (byte) 57 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 58 : "memory"); 59 pci_poke_in_progress = 0; 60 pci_poke_cpu = -1; 61 if (!pci_poke_faulted) 62 *ret = byte; 63 spin_unlock_irqrestore(&pci_poke_lock, flags); 64 } 65 66 void pci_config_read16(u16 *addr, u16 *ret) 67 { 68 unsigned long flags; 69 u16 word; 70 71 spin_lock_irqsave(&pci_poke_lock, flags); 72 pci_poke_cpu = smp_processor_id(); 73 pci_poke_in_progress = 1; 74 pci_poke_faulted = 0; 75 __asm__ __volatile__("membar #Sync\n\t" 76 "lduha [%1] %2, %0\n\t" 77 "membar #Sync" 78 : "=r" (word) 79 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 80 : "memory"); 81 pci_poke_in_progress = 0; 82 pci_poke_cpu = -1; 83 if (!pci_poke_faulted) 84 *ret = word; 85 spin_unlock_irqrestore(&pci_poke_lock, flags); 86 } 87 88 void pci_config_read32(u32 *addr, u32 *ret) 89 { 90 unsigned long flags; 91 u32 dword; 92 93 spin_lock_irqsave(&pci_poke_lock, flags); 94 pci_poke_cpu = smp_processor_id(); 95 pci_poke_in_progress = 1; 96 pci_poke_faulted = 0; 97 __asm__ __volatile__("membar #Sync\n\t" 98 "lduwa [%1] %2, %0\n\t" 99 "membar #Sync" 100 : "=r" (dword) 101 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 102 : "memory"); 103 pci_poke_in_progress = 0; 104 pci_poke_cpu = -1; 105 if (!pci_poke_faulted) 106 *ret = dword; 107 spin_unlock_irqrestore(&pci_poke_lock, flags); 108 } 109 110 void pci_config_write8(u8 *addr, u8 val) 111 { 112 unsigned long flags; 113 114 spin_lock_irqsave(&pci_poke_lock, flags); 115 pci_poke_cpu = smp_processor_id(); 116 pci_poke_in_progress = 1; 117 pci_poke_faulted = 0; 118 __asm__ __volatile__("membar #Sync\n\t" 119 "stba %0, [%1] %2\n\t" 120 "membar #Sync" 121 : /* no outputs */ 122 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 123 : "memory"); 124 pci_poke_in_progress = 0; 125 pci_poke_cpu = -1; 126 spin_unlock_irqrestore(&pci_poke_lock, flags); 127 } 128 129 void pci_config_write16(u16 *addr, u16 val) 130 { 131 unsigned long flags; 132 133 spin_lock_irqsave(&pci_poke_lock, flags); 134 pci_poke_cpu = smp_processor_id(); 135 pci_poke_in_progress = 1; 136 pci_poke_faulted = 0; 137 __asm__ __volatile__("membar #Sync\n\t" 138 "stha %0, [%1] %2\n\t" 139 "membar #Sync" 140 : /* no outputs */ 141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 142 : "memory"); 143 pci_poke_in_progress = 0; 144 pci_poke_cpu = -1; 145 spin_unlock_irqrestore(&pci_poke_lock, flags); 146 } 147 148 void pci_config_write32(u32 *addr, u32 val) 149 { 150 unsigned long flags; 151 152 spin_lock_irqsave(&pci_poke_lock, flags); 153 pci_poke_cpu = smp_processor_id(); 154 pci_poke_in_progress = 1; 155 pci_poke_faulted = 0; 156 __asm__ __volatile__("membar #Sync\n\t" 157 "stwa %0, [%1] %2\n\t" 158 "membar #Sync" 159 : /* no outputs */ 160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 161 : "memory"); 162 pci_poke_in_progress = 0; 163 pci_poke_cpu = -1; 164 spin_unlock_irqrestore(&pci_poke_lock, flags); 165 } 166 167 static int ofpci_verbose; 168 169 static int __init ofpci_debug(char *str) 170 { 171 int val = 0; 172 173 get_option(&str, &val); 174 if (val) 175 ofpci_verbose = 1; 176 return 1; 177 } 178 179 __setup("ofpci_debug=", ofpci_debug); 180 181 static unsigned long pci_parse_of_flags(u32 addr0) 182 { 183 unsigned long flags = 0; 184 185 if (addr0 & 0x02000000) { 186 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; 187 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; 188 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; 189 if (addr0 & 0x40000000) 190 flags |= IORESOURCE_PREFETCH 191 | PCI_BASE_ADDRESS_MEM_PREFETCH; 192 } else if (addr0 & 0x01000000) 193 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 194 return flags; 195 } 196 197 /* The of_device layer has translated all of the assigned-address properties 198 * into physical address resources, we only have to figure out the register 199 * mapping. 200 */ 201 static void pci_parse_of_addrs(struct of_device *op, 202 struct device_node *node, 203 struct pci_dev *dev) 204 { 205 struct resource *op_res; 206 const u32 *addrs; 207 int proplen; 208 209 addrs = of_get_property(node, "assigned-addresses", &proplen); 210 if (!addrs) 211 return; 212 if (ofpci_verbose) 213 printk(" parse addresses (%d bytes) @ %p\n", 214 proplen, addrs); 215 op_res = &op->resource[0]; 216 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { 217 struct resource *res; 218 unsigned long flags; 219 int i; 220 221 flags = pci_parse_of_flags(addrs[0]); 222 if (!flags) 223 continue; 224 i = addrs[0] & 0xff; 225 if (ofpci_verbose) 226 printk(" start: %llx, end: %llx, i: %x\n", 227 op_res->start, op_res->end, i); 228 229 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { 230 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; 231 } else if (i == dev->rom_base_reg) { 232 res = &dev->resource[PCI_ROM_RESOURCE]; 233 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; 234 } else { 235 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); 236 continue; 237 } 238 res->start = op_res->start; 239 res->end = op_res->end; 240 res->flags = flags; 241 res->name = pci_name(dev); 242 } 243 } 244 245 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, 246 struct device_node *node, 247 struct pci_bus *bus, int devfn) 248 { 249 struct dev_archdata *sd; 250 struct of_device *op; 251 struct pci_dev *dev; 252 const char *type; 253 u32 class; 254 255 dev = alloc_pci_dev(); 256 if (!dev) 257 return NULL; 258 259 sd = &dev->dev.archdata; 260 sd->iommu = pbm->iommu; 261 sd->stc = &pbm->stc; 262 sd->host_controller = pbm; 263 sd->prom_node = node; 264 sd->op = op = of_find_device_by_node(node); 265 sd->numa_node = pbm->numa_node; 266 267 sd = &op->dev.archdata; 268 sd->iommu = pbm->iommu; 269 sd->stc = &pbm->stc; 270 sd->numa_node = pbm->numa_node; 271 272 if (!strcmp(node->name, "ebus")) 273 of_propagate_archdata(op); 274 275 type = of_get_property(node, "device_type", NULL); 276 if (type == NULL) 277 type = ""; 278 279 if (ofpci_verbose) 280 printk(" create device, devfn: %x, type: %s\n", 281 devfn, type); 282 283 dev->bus = bus; 284 dev->sysdata = node; 285 dev->dev.parent = bus->bridge; 286 dev->dev.bus = &pci_bus_type; 287 dev->devfn = devfn; 288 dev->multifunction = 0; /* maybe a lie? */ 289 290 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); 291 dev->device = of_getintprop_default(node, "device-id", 0xffff); 292 dev->subsystem_vendor = 293 of_getintprop_default(node, "subsystem-vendor-id", 0); 294 dev->subsystem_device = 295 of_getintprop_default(node, "subsystem-id", 0); 296 297 dev->cfg_size = pci_cfg_space_size(dev); 298 299 /* We can't actually use the firmware value, we have 300 * to read what is in the register right now. One 301 * reason is that in the case of IDE interfaces the 302 * firmware can sample the value before the the IDE 303 * interface is programmed into native mode. 304 */ 305 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 306 dev->class = class >> 8; 307 dev->revision = class & 0xff; 308 309 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), 310 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 311 312 if (ofpci_verbose) 313 printk(" class: 0x%x device name: %s\n", 314 dev->class, pci_name(dev)); 315 316 /* I have seen IDE devices which will not respond to 317 * the bmdma simplex check reads if bus mastering is 318 * disabled. 319 */ 320 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) 321 pci_set_master(dev); 322 323 dev->current_state = 4; /* unknown power state */ 324 dev->error_state = pci_channel_io_normal; 325 326 if (!strcmp(node->name, "pci")) { 327 /* a PCI-PCI bridge */ 328 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 329 dev->rom_base_reg = PCI_ROM_ADDRESS1; 330 } else if (!strcmp(type, "cardbus")) { 331 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; 332 } else { 333 dev->hdr_type = PCI_HEADER_TYPE_NORMAL; 334 dev->rom_base_reg = PCI_ROM_ADDRESS; 335 336 dev->irq = sd->op->irqs[0]; 337 if (dev->irq == 0xffffffff) 338 dev->irq = PCI_IRQ_NONE; 339 } 340 341 pci_parse_of_addrs(sd->op, node, dev); 342 343 if (ofpci_verbose) 344 printk(" adding to system ...\n"); 345 346 pci_device_add(dev, bus); 347 348 return dev; 349 } 350 351 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) 352 { 353 u32 idx, first, last; 354 355 first = 8; 356 last = 0; 357 for (idx = 0; idx < 8; idx++) { 358 if ((map & (1 << idx)) != 0) { 359 if (first > idx) 360 first = idx; 361 if (last < idx) 362 last = idx; 363 } 364 } 365 366 *first_p = first; 367 *last_p = last; 368 } 369 370 static void pci_resource_adjust(struct resource *res, 371 struct resource *root) 372 { 373 res->start += root->start; 374 res->end += root->start; 375 } 376 377 /* For PCI bus devices which lack a 'ranges' property we interrogate 378 * the config space values to set the resources, just like the generic 379 * Linux PCI probing code does. 380 */ 381 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev, 382 struct pci_bus *bus, 383 struct pci_pbm_info *pbm) 384 { 385 struct resource *res; 386 u8 io_base_lo, io_limit_lo; 387 u16 mem_base_lo, mem_limit_lo; 388 unsigned long base, limit; 389 390 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 391 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 392 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; 393 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; 394 395 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 396 u16 io_base_hi, io_limit_hi; 397 398 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 399 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 400 base |= (io_base_hi << 16); 401 limit |= (io_limit_hi << 16); 402 } 403 404 res = bus->resource[0]; 405 if (base <= limit) { 406 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 407 if (!res->start) 408 res->start = base; 409 if (!res->end) 410 res->end = limit + 0xfff; 411 pci_resource_adjust(res, &pbm->io_space); 412 } 413 414 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 415 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 416 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 417 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 418 419 res = bus->resource[1]; 420 if (base <= limit) { 421 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | 422 IORESOURCE_MEM); 423 res->start = base; 424 res->end = limit + 0xfffff; 425 pci_resource_adjust(res, &pbm->mem_space); 426 } 427 428 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 429 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 430 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 431 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 432 433 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 434 u32 mem_base_hi, mem_limit_hi; 435 436 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 437 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 438 439 /* 440 * Some bridges set the base > limit by default, and some 441 * (broken) BIOSes do not initialize them. If we find 442 * this, just assume they are not being used. 443 */ 444 if (mem_base_hi <= mem_limit_hi) { 445 base |= ((long) mem_base_hi) << 32; 446 limit |= ((long) mem_limit_hi) << 32; 447 } 448 } 449 450 res = bus->resource[2]; 451 if (base <= limit) { 452 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | 453 IORESOURCE_MEM | IORESOURCE_PREFETCH); 454 res->start = base; 455 res->end = limit + 0xfffff; 456 pci_resource_adjust(res, &pbm->mem_space); 457 } 458 } 459 460 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack 461 * a proper 'ranges' property. 462 */ 463 static void __devinit apb_fake_ranges(struct pci_dev *dev, 464 struct pci_bus *bus, 465 struct pci_pbm_info *pbm) 466 { 467 struct resource *res; 468 u32 first, last; 469 u8 map; 470 471 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); 472 apb_calc_first_last(map, &first, &last); 473 res = bus->resource[0]; 474 res->start = (first << 21); 475 res->end = (last << 21) + ((1 << 21) - 1); 476 res->flags = IORESOURCE_IO; 477 pci_resource_adjust(res, &pbm->io_space); 478 479 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); 480 apb_calc_first_last(map, &first, &last); 481 res = bus->resource[1]; 482 res->start = (first << 21); 483 res->end = (last << 21) + ((1 << 21) - 1); 484 res->flags = IORESOURCE_MEM; 485 pci_resource_adjust(res, &pbm->mem_space); 486 } 487 488 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, 489 struct device_node *node, 490 struct pci_bus *bus); 491 492 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) 493 494 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, 495 struct device_node *node, 496 struct pci_dev *dev) 497 { 498 struct pci_bus *bus; 499 const u32 *busrange, *ranges; 500 int len, i, simba; 501 struct resource *res; 502 unsigned int flags; 503 u64 size; 504 505 if (ofpci_verbose) 506 printk("of_scan_pci_bridge(%s)\n", node->full_name); 507 508 /* parse bus-range property */ 509 busrange = of_get_property(node, "bus-range", &len); 510 if (busrange == NULL || len != 8) { 511 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", 512 node->full_name); 513 return; 514 } 515 ranges = of_get_property(node, "ranges", &len); 516 simba = 0; 517 if (ranges == NULL) { 518 const char *model = of_get_property(node, "model", NULL); 519 if (model && !strcmp(model, "SUNW,simba")) 520 simba = 1; 521 } 522 523 bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 524 if (!bus) { 525 printk(KERN_ERR "Failed to create pci bus for %s\n", 526 node->full_name); 527 return; 528 } 529 530 bus->primary = dev->bus->number; 531 bus->subordinate = busrange[1]; 532 bus->bridge_ctl = 0; 533 534 /* parse ranges property, or cook one up by hand for Simba */ 535 /* PCI #address-cells == 3 and #size-cells == 2 always */ 536 res = &dev->resource[PCI_BRIDGE_RESOURCES]; 537 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { 538 res->flags = 0; 539 bus->resource[i] = res; 540 ++res; 541 } 542 if (simba) { 543 apb_fake_ranges(dev, bus, pbm); 544 goto after_ranges; 545 } else if (ranges == NULL) { 546 pci_cfg_fake_ranges(dev, bus, pbm); 547 goto after_ranges; 548 } 549 i = 1; 550 for (; len >= 32; len -= 32, ranges += 8) { 551 struct resource *root; 552 553 flags = pci_parse_of_flags(ranges[0]); 554 size = GET_64BIT(ranges, 6); 555 if (flags == 0 || size == 0) 556 continue; 557 if (flags & IORESOURCE_IO) { 558 res = bus->resource[0]; 559 if (res->flags) { 560 printk(KERN_ERR "PCI: ignoring extra I/O range" 561 " for bridge %s\n", node->full_name); 562 continue; 563 } 564 root = &pbm->io_space; 565 } else { 566 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { 567 printk(KERN_ERR "PCI: too many memory ranges" 568 " for bridge %s\n", node->full_name); 569 continue; 570 } 571 res = bus->resource[i]; 572 ++i; 573 root = &pbm->mem_space; 574 } 575 576 res->start = GET_64BIT(ranges, 1); 577 res->end = res->start + size - 1; 578 res->flags = flags; 579 580 /* Another way to implement this would be to add an of_device 581 * layer routine that can calculate a resource for a given 582 * range property value in a PCI device. 583 */ 584 pci_resource_adjust(res, root); 585 } 586 after_ranges: 587 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 588 bus->number); 589 if (ofpci_verbose) 590 printk(" bus name: %s\n", bus->name); 591 592 pci_of_scan_bus(pbm, node, bus); 593 } 594 595 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, 596 struct device_node *node, 597 struct pci_bus *bus) 598 { 599 struct device_node *child; 600 const u32 *reg; 601 int reglen, devfn, prev_devfn; 602 struct pci_dev *dev; 603 604 if (ofpci_verbose) 605 printk("PCI: scan_bus[%s] bus no %d\n", 606 node->full_name, bus->number); 607 608 child = NULL; 609 prev_devfn = -1; 610 while ((child = of_get_next_child(node, child)) != NULL) { 611 if (ofpci_verbose) 612 printk(" * %s\n", child->full_name); 613 reg = of_get_property(child, "reg", ®len); 614 if (reg == NULL || reglen < 20) 615 continue; 616 617 devfn = (reg[0] >> 8) & 0xff; 618 619 /* This is a workaround for some device trees 620 * which list PCI devices twice. On the V100 621 * for example, device number 3 is listed twice. 622 * Once as "pm" and once again as "lomp". 623 */ 624 if (devfn == prev_devfn) 625 continue; 626 prev_devfn = devfn; 627 628 /* create a new pci_dev for this device */ 629 dev = of_create_pci_dev(pbm, child, bus, devfn); 630 if (!dev) 631 continue; 632 if (ofpci_verbose) 633 printk("PCI: dev header type: %x\n", 634 dev->hdr_type); 635 636 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 637 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 638 of_scan_pci_bridge(pbm, child, dev); 639 } 640 } 641 642 static ssize_t 643 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) 644 { 645 struct pci_dev *pdev; 646 struct device_node *dp; 647 648 pdev = to_pci_dev(dev); 649 dp = pdev->dev.archdata.prom_node; 650 651 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); 652 } 653 654 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); 655 656 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) 657 { 658 struct pci_dev *dev; 659 struct pci_bus *child_bus; 660 int err; 661 662 list_for_each_entry(dev, &bus->devices, bus_list) { 663 /* we don't really care if we can create this file or 664 * not, but we need to assign the result of the call 665 * or the world will fall under alien invasion and 666 * everybody will be frozen on a spaceship ready to be 667 * eaten on alpha centauri by some green and jelly 668 * humanoid. 669 */ 670 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); 671 } 672 list_for_each_entry(child_bus, &bus->children, node) 673 pci_bus_register_of_sysfs(child_bus); 674 } 675 676 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, 677 struct device *parent) 678 { 679 struct device_node *node = pbm->op->node; 680 struct pci_bus *bus; 681 682 printk("PCI: Scanning PBM %s\n", node->full_name); 683 684 bus = pci_create_bus(parent, pbm->pci_first_busno, pbm->pci_ops, pbm); 685 if (!bus) { 686 printk(KERN_ERR "Failed to create bus for %s\n", 687 node->full_name); 688 return NULL; 689 } 690 bus->secondary = pbm->pci_first_busno; 691 bus->subordinate = pbm->pci_last_busno; 692 693 bus->resource[0] = &pbm->io_space; 694 bus->resource[1] = &pbm->mem_space; 695 696 pci_of_scan_bus(pbm, node, bus); 697 pci_bus_add_devices(bus); 698 pci_bus_register_of_sysfs(bus); 699 700 return bus; 701 } 702 703 void __devinit pcibios_fixup_bus(struct pci_bus *pbus) 704 { 705 struct pci_pbm_info *pbm = pbus->sysdata; 706 707 /* Generic PCI bus probing sets these to point at 708 * &io{port,mem}_resouce which is wrong for us. 709 */ 710 pbus->resource[0] = &pbm->io_space; 711 pbus->resource[1] = &pbm->mem_space; 712 } 713 714 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) 715 { 716 struct pci_pbm_info *pbm = pdev->bus->sysdata; 717 struct resource *root = NULL; 718 719 if (r->flags & IORESOURCE_IO) 720 root = &pbm->io_space; 721 if (r->flags & IORESOURCE_MEM) 722 root = &pbm->mem_space; 723 724 return root; 725 } 726 727 void pcibios_update_irq(struct pci_dev *pdev, int irq) 728 { 729 } 730 731 void pcibios_align_resource(void *data, struct resource *res, 732 resource_size_t size, resource_size_t align) 733 { 734 } 735 736 int pcibios_enable_device(struct pci_dev *dev, int mask) 737 { 738 u16 cmd, oldcmd; 739 int i; 740 741 pci_read_config_word(dev, PCI_COMMAND, &cmd); 742 oldcmd = cmd; 743 744 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 745 struct resource *res = &dev->resource[i]; 746 747 /* Only set up the requested stuff */ 748 if (!(mask & (1<<i))) 749 continue; 750 751 if (res->flags & IORESOURCE_IO) 752 cmd |= PCI_COMMAND_IO; 753 if (res->flags & IORESOURCE_MEM) 754 cmd |= PCI_COMMAND_MEMORY; 755 } 756 757 if (cmd != oldcmd) { 758 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", 759 pci_name(dev), cmd); 760 /* Enable the appropriate bits in the PCI command register. */ 761 pci_write_config_word(dev, PCI_COMMAND, cmd); 762 } 763 return 0; 764 } 765 766 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, 767 struct resource *res) 768 { 769 struct pci_pbm_info *pbm = pdev->bus->sysdata; 770 struct resource zero_res, *root; 771 772 zero_res.start = 0; 773 zero_res.end = 0; 774 zero_res.flags = res->flags; 775 776 if (res->flags & IORESOURCE_IO) 777 root = &pbm->io_space; 778 else 779 root = &pbm->mem_space; 780 781 pci_resource_adjust(&zero_res, root); 782 783 region->start = res->start - zero_res.start; 784 region->end = res->end - zero_res.start; 785 } 786 EXPORT_SYMBOL(pcibios_resource_to_bus); 787 788 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, 789 struct pci_bus_region *region) 790 { 791 struct pci_pbm_info *pbm = pdev->bus->sysdata; 792 struct resource *root; 793 794 res->start = region->start; 795 res->end = region->end; 796 797 if (res->flags & IORESOURCE_IO) 798 root = &pbm->io_space; 799 else 800 root = &pbm->mem_space; 801 802 pci_resource_adjust(res, root); 803 } 804 EXPORT_SYMBOL(pcibios_bus_to_resource); 805 806 char * __devinit pcibios_setup(char *str) 807 { 808 return str; 809 } 810 811 /* Platform support for /proc/bus/pci/X/Y mmap()s. */ 812 813 /* If the user uses a host-bridge as the PCI device, he may use 814 * this to perform a raw mmap() of the I/O or MEM space behind 815 * that controller. 816 * 817 * This can be useful for execution of x86 PCI bios initialization code 818 * on a PCI card, like the xfree86 int10 stuff does. 819 */ 820 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, 821 enum pci_mmap_state mmap_state) 822 { 823 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 824 unsigned long space_size, user_offset, user_size; 825 826 if (mmap_state == pci_mmap_io) { 827 space_size = (pbm->io_space.end - 828 pbm->io_space.start) + 1; 829 } else { 830 space_size = (pbm->mem_space.end - 831 pbm->mem_space.start) + 1; 832 } 833 834 /* Make sure the request is in range. */ 835 user_offset = vma->vm_pgoff << PAGE_SHIFT; 836 user_size = vma->vm_end - vma->vm_start; 837 838 if (user_offset >= space_size || 839 (user_offset + user_size) > space_size) 840 return -EINVAL; 841 842 if (mmap_state == pci_mmap_io) { 843 vma->vm_pgoff = (pbm->io_space.start + 844 user_offset) >> PAGE_SHIFT; 845 } else { 846 vma->vm_pgoff = (pbm->mem_space.start + 847 user_offset) >> PAGE_SHIFT; 848 } 849 850 return 0; 851 } 852 853 /* Adjust vm_pgoff of VMA such that it is the physical page offset 854 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 855 * 856 * Basically, the user finds the base address for his device which he wishes 857 * to mmap. They read the 32-bit value from the config space base register, 858 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 859 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 860 * 861 * Returns negative error code on failure, zero on success. 862 */ 863 static int __pci_mmap_make_offset(struct pci_dev *pdev, 864 struct vm_area_struct *vma, 865 enum pci_mmap_state mmap_state) 866 { 867 unsigned long user_paddr, user_size; 868 int i, err; 869 870 /* First compute the physical address in vma->vm_pgoff, 871 * making sure the user offset is within range in the 872 * appropriate PCI space. 873 */ 874 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state); 875 if (err) 876 return err; 877 878 /* If this is a mapping on a host bridge, any address 879 * is OK. 880 */ 881 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST) 882 return err; 883 884 /* Otherwise make sure it's in the range for one of the 885 * device's resources. 886 */ 887 user_paddr = vma->vm_pgoff << PAGE_SHIFT; 888 user_size = vma->vm_end - vma->vm_start; 889 890 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 891 struct resource *rp = &pdev->resource[i]; 892 resource_size_t aligned_end; 893 894 /* Active? */ 895 if (!rp->flags) 896 continue; 897 898 /* Same type? */ 899 if (i == PCI_ROM_RESOURCE) { 900 if (mmap_state != pci_mmap_mem) 901 continue; 902 } else { 903 if ((mmap_state == pci_mmap_io && 904 (rp->flags & IORESOURCE_IO) == 0) || 905 (mmap_state == pci_mmap_mem && 906 (rp->flags & IORESOURCE_MEM) == 0)) 907 continue; 908 } 909 910 /* Align the resource end to the next page address. 911 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1), 912 * because actually we need the address of the next byte 913 * after rp->end. 914 */ 915 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK; 916 917 if ((rp->start <= user_paddr) && 918 (user_paddr + user_size) <= aligned_end) 919 break; 920 } 921 922 if (i > PCI_ROM_RESOURCE) 923 return -EINVAL; 924 925 return 0; 926 } 927 928 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device 929 * mapping. 930 */ 931 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, 932 enum pci_mmap_state mmap_state) 933 { 934 vma->vm_flags |= (VM_IO | VM_RESERVED); 935 } 936 937 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 938 * device mapping. 939 */ 940 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, 941 enum pci_mmap_state mmap_state) 942 { 943 /* Our io_remap_pfn_range takes care of this, do nothing. */ 944 } 945 946 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate 947 * for this architecture. The region in the process to map is described by vm_start 948 * and vm_end members of VMA, the base physical address is found in vm_pgoff. 949 * The pci device structure is provided so that architectures may make mapping 950 * decisions on a per-device or per-bus basis. 951 * 952 * Returns a negative error code on failure, zero on success. 953 */ 954 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 955 enum pci_mmap_state mmap_state, 956 int write_combine) 957 { 958 int ret; 959 960 ret = __pci_mmap_make_offset(dev, vma, mmap_state); 961 if (ret < 0) 962 return ret; 963 964 __pci_mmap_set_flags(dev, vma, mmap_state); 965 __pci_mmap_set_pgprot(dev, vma, mmap_state); 966 967 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 968 ret = io_remap_pfn_range(vma, vma->vm_start, 969 vma->vm_pgoff, 970 vma->vm_end - vma->vm_start, 971 vma->vm_page_prot); 972 if (ret) 973 return ret; 974 975 return 0; 976 } 977 978 #ifdef CONFIG_NUMA 979 int pcibus_to_node(struct pci_bus *pbus) 980 { 981 struct pci_pbm_info *pbm = pbus->sysdata; 982 983 return pbm->numa_node; 984 } 985 EXPORT_SYMBOL(pcibus_to_node); 986 #endif 987 988 /* Return the domain number for this pci bus */ 989 990 int pci_domain_nr(struct pci_bus *pbus) 991 { 992 struct pci_pbm_info *pbm = pbus->sysdata; 993 int ret; 994 995 if (!pbm) { 996 ret = -ENXIO; 997 } else { 998 ret = pbm->index; 999 } 1000 1001 return ret; 1002 } 1003 EXPORT_SYMBOL(pci_domain_nr); 1004 1005 #ifdef CONFIG_PCI_MSI 1006 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 1007 { 1008 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 1009 unsigned int virt_irq; 1010 1011 if (!pbm->setup_msi_irq) 1012 return -EINVAL; 1013 1014 return pbm->setup_msi_irq(&virt_irq, pdev, desc); 1015 } 1016 1017 void arch_teardown_msi_irq(unsigned int virt_irq) 1018 { 1019 struct msi_desc *entry = get_irq_msi(virt_irq); 1020 struct pci_dev *pdev = entry->dev; 1021 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 1022 1023 if (pbm->teardown_msi_irq) 1024 pbm->teardown_msi_irq(virt_irq, pdev); 1025 } 1026 #endif /* !(CONFIG_PCI_MSI) */ 1027 1028 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) 1029 { 1030 return pdev->dev.archdata.prom_node; 1031 } 1032 EXPORT_SYMBOL(pci_device_to_OF_node); 1033 1034 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) 1035 { 1036 struct pci_dev *ali_isa_bridge; 1037 u8 val; 1038 1039 /* ALI sound chips generate 31-bits of DMA, a special register 1040 * determines what bit 31 is emitted as. 1041 */ 1042 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, 1043 PCI_DEVICE_ID_AL_M1533, 1044 NULL); 1045 1046 pci_read_config_byte(ali_isa_bridge, 0x7e, &val); 1047 if (set_bit) 1048 val |= 0x01; 1049 else 1050 val &= ~0x01; 1051 pci_write_config_byte(ali_isa_bridge, 0x7e, val); 1052 pci_dev_put(ali_isa_bridge); 1053 } 1054 1055 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask) 1056 { 1057 u64 dma_addr_mask; 1058 1059 if (pdev == NULL) { 1060 dma_addr_mask = 0xffffffff; 1061 } else { 1062 struct iommu *iommu = pdev->dev.archdata.iommu; 1063 1064 dma_addr_mask = iommu->dma_addr_mask; 1065 1066 if (pdev->vendor == PCI_VENDOR_ID_AL && 1067 pdev->device == PCI_DEVICE_ID_AL_M5451 && 1068 device_mask == 0x7fffffff) { 1069 ali_sound_dma_hack(pdev, 1070 (dma_addr_mask & 0x80000000) != 0); 1071 return 1; 1072 } 1073 } 1074 1075 if (device_mask >= (1UL << 32UL)) 1076 return 0; 1077 1078 return (device_mask & dma_addr_mask) == dma_addr_mask; 1079 } 1080 EXPORT_SYMBOL(pci_dma_supported); 1081 1082 void pci_resource_to_user(const struct pci_dev *pdev, int bar, 1083 const struct resource *rp, resource_size_t *start, 1084 resource_size_t *end) 1085 { 1086 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 1087 unsigned long offset; 1088 1089 if (rp->flags & IORESOURCE_IO) 1090 offset = pbm->io_space.start; 1091 else 1092 offset = pbm->mem_space.start; 1093 1094 *start = rp->start - offset; 1095 *end = rp->end - offset; 1096 } 1097