1 /* 2 * leon_pci_grpci2.c: GRPCI2 Host PCI driver 3 * 4 * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom 5 * 6 */ 7 8 #include <linux/of_device.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/delay.h> 12 #include <linux/export.h> 13 #include <asm/io.h> 14 #include <asm/leon.h> 15 #include <asm/vaddrs.h> 16 #include <asm/sections.h> 17 #include <asm/leon_pci.h> 18 19 #include "irq.h" 20 21 struct grpci2_barcfg { 22 unsigned long pciadr; /* PCI Space Address */ 23 unsigned long ahbadr; /* PCI Base address mapped to this AHB addr */ 24 }; 25 26 /* Device Node Configuration options: 27 * - barcfgs : Custom Configuration of Host's 6 target BARs 28 * - irq_mask : Limit which PCI interrupts are enabled 29 * - do_reset : Force PCI Reset on startup 30 * 31 * barcfgs 32 * ======= 33 * 34 * Optional custom Target BAR configuration (see struct grpci2_barcfg). All 35 * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes) 36 * 37 * -1 means not configured (let host driver do default setup). 38 * 39 * [i*2+0] = PCI Address of BAR[i] on target interface 40 * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address 41 * 42 * 43 * irq_mask 44 * ======== 45 * 46 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default 47 * all are enabled. Use this when PCI interrupt pins are floating on PCB. 48 * int, len=4. 49 * bit0 = PCI INTA# 50 * bit1 = PCI INTB# 51 * bit2 = PCI INTC# 52 * bit3 = PCI INTD# 53 * 54 * 55 * reset 56 * ===== 57 * 58 * Force PCI reset on startup. int, len=4 59 */ 60 61 /* Enable Debugging Configuration Space Access */ 62 #undef GRPCI2_DEBUG_CFGACCESS 63 64 /* 65 * GRPCI2 APB Register MAP 66 */ 67 struct grpci2_regs { 68 unsigned int ctrl; /* 0x00 Control */ 69 unsigned int sts_cap; /* 0x04 Status / Capabilities */ 70 int res1; /* 0x08 */ 71 unsigned int io_map; /* 0x0C I/O Map address */ 72 unsigned int dma_ctrl; /* 0x10 DMA */ 73 unsigned int dma_bdbase; /* 0x14 DMA */ 74 int res2[2]; /* 0x18 */ 75 unsigned int bars[6]; /* 0x20 read-only PCI BARs */ 76 int res3[2]; /* 0x38 */ 77 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */ 78 79 /* PCI Trace Buffer Registers (OPTIONAL) */ 80 unsigned int t_ctrl; /* 0x80 */ 81 unsigned int t_cnt; /* 0x84 */ 82 unsigned int t_adpat; /* 0x88 */ 83 unsigned int t_admask; /* 0x8C */ 84 unsigned int t_sigpat; /* 0x90 */ 85 unsigned int t_sigmask; /* 0x94 */ 86 unsigned int t_adstate; /* 0x98 */ 87 unsigned int t_sigstate; /* 0x9C */ 88 }; 89 90 #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a)))) 91 #define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a))) 92 93 #define CTRL_BUS_BIT 16 94 95 #define CTRL_RESET (1<<31) 96 #define CTRL_SI (1<<27) 97 #define CTRL_PE (1<<26) 98 #define CTRL_EI (1<<25) 99 #define CTRL_ER (1<<24) 100 #define CTRL_BUS (0xff<<CTRL_BUS_BIT) 101 #define CTRL_HOSTINT 0xf 102 103 #define STS_HOST_BIT 31 104 #define STS_MST_BIT 30 105 #define STS_TAR_BIT 29 106 #define STS_DMA_BIT 28 107 #define STS_DI_BIT 27 108 #define STS_HI_BIT 26 109 #define STS_IRQMODE_BIT 24 110 #define STS_TRACE_BIT 23 111 #define STS_CFGERRVALID_BIT 20 112 #define STS_CFGERR_BIT 19 113 #define STS_INTTYPE_BIT 12 114 #define STS_INTSTS_BIT 8 115 #define STS_FDEPTH_BIT 2 116 #define STS_FNUM_BIT 0 117 118 #define STS_HOST (1<<STS_HOST_BIT) 119 #define STS_MST (1<<STS_MST_BIT) 120 #define STS_TAR (1<<STS_TAR_BIT) 121 #define STS_DMA (1<<STS_DMA_BIT) 122 #define STS_DI (1<<STS_DI_BIT) 123 #define STS_HI (1<<STS_HI_BIT) 124 #define STS_IRQMODE (0x3<<STS_IRQMODE_BIT) 125 #define STS_TRACE (1<<STS_TRACE_BIT) 126 #define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT) 127 #define STS_CFGERR (1<<STS_CFGERR_BIT) 128 #define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT) 129 #define STS_INTSTS (0xf<<STS_INTSTS_BIT) 130 #define STS_FDEPTH (0x7<<STS_FDEPTH_BIT) 131 #define STS_FNUM (0x3<<STS_FNUM_BIT) 132 133 #define STS_ISYSERR (1<<17) 134 #define STS_IDMA (1<<16) 135 #define STS_IDMAERR (1<<15) 136 #define STS_IMSTABRT (1<<14) 137 #define STS_ITGTABRT (1<<13) 138 #define STS_IPARERR (1<<12) 139 140 #define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR) 141 142 struct grpci2_bd_chan { 143 unsigned int ctrl; /* 0x00 DMA Control */ 144 unsigned int nchan; /* 0x04 Next DMA Channel Address */ 145 unsigned int nbd; /* 0x08 Next Data Descriptor in chan */ 146 unsigned int res; /* 0x0C Reserved */ 147 }; 148 149 #define BD_CHAN_EN 0x80000000 150 #define BD_CHAN_TYPE 0x00300000 151 #define BD_CHAN_BDCNT 0x0000ffff 152 #define BD_CHAN_EN_BIT 31 153 #define BD_CHAN_TYPE_BIT 20 154 #define BD_CHAN_BDCNT_BIT 0 155 156 struct grpci2_bd_data { 157 unsigned int ctrl; /* 0x00 DMA Data Control */ 158 unsigned int pci_adr; /* 0x04 PCI Start Address */ 159 unsigned int ahb_adr; /* 0x08 AHB Start address */ 160 unsigned int next; /* 0x0C Next Data Descriptor in chan */ 161 }; 162 163 #define BD_DATA_EN 0x80000000 164 #define BD_DATA_IE 0x40000000 165 #define BD_DATA_DR 0x20000000 166 #define BD_DATA_TYPE 0x00300000 167 #define BD_DATA_ER 0x00080000 168 #define BD_DATA_LEN 0x0000ffff 169 #define BD_DATA_EN_BIT 31 170 #define BD_DATA_IE_BIT 30 171 #define BD_DATA_DR_BIT 29 172 #define BD_DATA_TYPE_BIT 20 173 #define BD_DATA_ER_BIT 19 174 #define BD_DATA_LEN_BIT 0 175 176 /* GRPCI2 Capability */ 177 struct grpci2_cap_first { 178 unsigned int ctrl; 179 unsigned int pci2ahb_map[6]; 180 unsigned int ext2ahb_map; 181 unsigned int io_map; 182 unsigned int pcibar_size[6]; 183 }; 184 #define CAP9_CTRL_OFS 0 185 #define CAP9_BAR_OFS 0x4 186 #define CAP9_IOMAP_OFS 0x20 187 #define CAP9_BARSIZE_OFS 0x24 188 189 struct grpci2_priv { 190 struct leon_pci_info info; /* must be on top of this structure */ 191 struct grpci2_regs *regs; 192 char irq; 193 char irq_mode; /* IRQ Mode from CAPSTS REG */ 194 char bt_enabled; 195 char do_reset; 196 char irq_mask; 197 u32 pciid; /* PCI ID of Host */ 198 unsigned char irq_map[4]; 199 200 /* Virtual IRQ numbers */ 201 unsigned int virq_err; 202 unsigned int virq_dma; 203 204 /* AHB PCI Windows */ 205 unsigned long pci_area; /* MEMORY */ 206 unsigned long pci_area_end; 207 unsigned long pci_io; /* I/O */ 208 unsigned long pci_conf; /* CONFIGURATION */ 209 unsigned long pci_conf_end; 210 unsigned long pci_io_va; 211 212 struct grpci2_barcfg tgtbars[6]; 213 }; 214 215 DEFINE_SPINLOCK(grpci2_dev_lock); 216 struct grpci2_priv *grpci2priv; 217 218 int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 219 { 220 struct grpci2_priv *priv = dev->bus->sysdata; 221 int irq_group; 222 223 /* Use default IRQ decoding on PCI BUS0 according slot numbering */ 224 irq_group = slot & 0x3; 225 pin = ((pin - 1) + irq_group) & 0x3; 226 227 return priv->irq_map[pin]; 228 } 229 230 static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus, 231 unsigned int devfn, int where, u32 *val) 232 { 233 unsigned int *pci_conf; 234 unsigned long flags; 235 u32 tmp; 236 237 if (where & 0x3) 238 return -EINVAL; 239 240 if (bus == 0 && PCI_SLOT(devfn) != 0) 241 devfn += (0x8 * 6); 242 243 /* Select bus */ 244 spin_lock_irqsave(&grpci2_dev_lock, flags); 245 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) | 246 (bus << 16)); 247 spin_unlock_irqrestore(&grpci2_dev_lock, flags); 248 249 /* clear old status */ 250 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID)); 251 252 pci_conf = (unsigned int *) (priv->pci_conf | 253 (devfn << 8) | (where & 0xfc)); 254 tmp = LEON3_BYPASS_LOAD_PA(pci_conf); 255 256 /* Wait until GRPCI2 signals that CFG access is done, it should be 257 * done instantaneously unless a DMA operation is ongoing... 258 */ 259 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0) 260 ; 261 262 if (REGLOAD(priv->regs->sts_cap) & STS_CFGERR) { 263 *val = 0xffffffff; 264 } else { 265 /* Bus always little endian (unaffected by byte-swapping) */ 266 *val = flip_dword(tmp); 267 } 268 269 return 0; 270 } 271 272 static int grpci2_cfg_r16(struct grpci2_priv *priv, unsigned int bus, 273 unsigned int devfn, int where, u32 *val) 274 { 275 u32 v; 276 int ret; 277 278 if (where & 0x1) 279 return -EINVAL; 280 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v); 281 *val = 0xffff & (v >> (8 * (where & 0x3))); 282 return ret; 283 } 284 285 static int grpci2_cfg_r8(struct grpci2_priv *priv, unsigned int bus, 286 unsigned int devfn, int where, u32 *val) 287 { 288 u32 v; 289 int ret; 290 291 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v); 292 *val = 0xff & (v >> (8 * (where & 3))); 293 294 return ret; 295 } 296 297 static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus, 298 unsigned int devfn, int where, u32 val) 299 { 300 unsigned int *pci_conf; 301 unsigned long flags; 302 303 if (where & 0x3) 304 return -EINVAL; 305 306 if (bus == 0 && PCI_SLOT(devfn) != 0) 307 devfn += (0x8 * 6); 308 309 /* Select bus */ 310 spin_lock_irqsave(&grpci2_dev_lock, flags); 311 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) | 312 (bus << 16)); 313 spin_unlock_irqrestore(&grpci2_dev_lock, flags); 314 315 /* clear old status */ 316 REGSTORE(priv->regs->sts_cap, (STS_CFGERR | STS_CFGERRVALID)); 317 318 pci_conf = (unsigned int *) (priv->pci_conf | 319 (devfn << 8) | (where & 0xfc)); 320 LEON3_BYPASS_STORE_PA(pci_conf, flip_dword(val)); 321 322 /* Wait until GRPCI2 signals that CFG access is done, it should be 323 * done instantaneously unless a DMA operation is ongoing... 324 */ 325 while ((REGLOAD(priv->regs->sts_cap) & STS_CFGERRVALID) == 0) 326 ; 327 328 return 0; 329 } 330 331 static int grpci2_cfg_w16(struct grpci2_priv *priv, unsigned int bus, 332 unsigned int devfn, int where, u32 val) 333 { 334 int ret; 335 u32 v; 336 337 if (where & 0x1) 338 return -EINVAL; 339 ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v); 340 if (ret) 341 return ret; 342 v = (v & ~(0xffff << (8 * (where & 0x3)))) | 343 ((0xffff & val) << (8 * (where & 0x3))); 344 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v); 345 } 346 347 static int grpci2_cfg_w8(struct grpci2_priv *priv, unsigned int bus, 348 unsigned int devfn, int where, u32 val) 349 { 350 int ret; 351 u32 v; 352 353 ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v); 354 if (ret != 0) 355 return ret; 356 v = (v & ~(0xff << (8 * (where & 0x3)))) | 357 ((0xff & val) << (8 * (where & 0x3))); 358 return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v); 359 } 360 361 /* Read from Configuration Space. When entering here the PCI layer has taken 362 * the pci_lock spinlock and IRQ is off. 363 */ 364 static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn, 365 int where, int size, u32 *val) 366 { 367 struct grpci2_priv *priv = grpci2priv; 368 unsigned int busno = bus->number; 369 int ret; 370 371 if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0)) { 372 *val = ~0; 373 return 0; 374 } 375 376 switch (size) { 377 case 1: 378 ret = grpci2_cfg_r8(priv, busno, devfn, where, val); 379 break; 380 case 2: 381 ret = grpci2_cfg_r16(priv, busno, devfn, where, val); 382 break; 383 case 4: 384 ret = grpci2_cfg_r32(priv, busno, devfn, where, val); 385 break; 386 default: 387 ret = -EINVAL; 388 break; 389 } 390 391 #ifdef GRPCI2_DEBUG_CFGACCESS 392 printk(KERN_INFO "grpci2_read_config: [%02x:%02x:%x] ofs=%d val=%x " 393 "size=%d\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, 394 *val, size); 395 #endif 396 397 return ret; 398 } 399 400 /* Write to Configuration Space. When entering here the PCI layer has taken 401 * the pci_lock spinlock and IRQ is off. 402 */ 403 static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn, 404 int where, int size, u32 val) 405 { 406 struct grpci2_priv *priv = grpci2priv; 407 unsigned int busno = bus->number; 408 409 if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0)) 410 return 0; 411 412 #ifdef GRPCI2_DEBUG_CFGACCESS 413 printk(KERN_INFO "grpci2_write_config: [%02x:%02x:%x] ofs=%d size=%d " 414 "val=%x\n", busno, PCI_SLOT(devfn), PCI_FUNC(devfn), 415 where, size, val); 416 #endif 417 418 switch (size) { 419 default: 420 return -EINVAL; 421 case 1: 422 return grpci2_cfg_w8(priv, busno, devfn, where, val); 423 case 2: 424 return grpci2_cfg_w16(priv, busno, devfn, where, val); 425 case 4: 426 return grpci2_cfg_w32(priv, busno, devfn, where, val); 427 } 428 } 429 430 static struct pci_ops grpci2_ops = { 431 .read = grpci2_read_config, 432 .write = grpci2_write_config, 433 }; 434 435 /* GENIRQ IRQ chip implementation for GRPCI2 irqmode=0..2. In configuration 436 * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller 437 * this is not needed and the standard IRQ controller can be used. 438 */ 439 440 static void grpci2_mask_irq(struct irq_data *data) 441 { 442 unsigned long flags; 443 unsigned int irqidx; 444 struct grpci2_priv *priv = grpci2priv; 445 446 irqidx = (unsigned int)data->chip_data - 1; 447 if (irqidx > 3) /* only mask PCI interrupts here */ 448 return; 449 450 spin_lock_irqsave(&grpci2_dev_lock, flags); 451 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx)); 452 spin_unlock_irqrestore(&grpci2_dev_lock, flags); 453 } 454 455 static void grpci2_unmask_irq(struct irq_data *data) 456 { 457 unsigned long flags; 458 unsigned int irqidx; 459 struct grpci2_priv *priv = grpci2priv; 460 461 irqidx = (unsigned int)data->chip_data - 1; 462 if (irqidx > 3) /* only unmask PCI interrupts here */ 463 return; 464 465 spin_lock_irqsave(&grpci2_dev_lock, flags); 466 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx)); 467 spin_unlock_irqrestore(&grpci2_dev_lock, flags); 468 } 469 470 static unsigned int grpci2_startup_irq(struct irq_data *data) 471 { 472 grpci2_unmask_irq(data); 473 return 0; 474 } 475 476 static void grpci2_shutdown_irq(struct irq_data *data) 477 { 478 grpci2_mask_irq(data); 479 } 480 481 static struct irq_chip grpci2_irq = { 482 .name = "grpci2", 483 .irq_startup = grpci2_startup_irq, 484 .irq_shutdown = grpci2_shutdown_irq, 485 .irq_mask = grpci2_mask_irq, 486 .irq_unmask = grpci2_unmask_irq, 487 }; 488 489 /* Handle one or multiple IRQs from the PCI core */ 490 static void grpci2_pci_flow_irq(unsigned int irq, struct irq_desc *desc) 491 { 492 struct grpci2_priv *priv = grpci2priv; 493 int i, ack = 0; 494 unsigned int ctrl, sts_cap, pci_ints; 495 496 ctrl = REGLOAD(priv->regs->ctrl); 497 sts_cap = REGLOAD(priv->regs->sts_cap); 498 499 /* Error Interrupt? */ 500 if (sts_cap & STS_ERR_IRQ) { 501 generic_handle_irq(priv->virq_err); 502 ack = 1; 503 } 504 505 /* PCI Interrupt? */ 506 pci_ints = ((~sts_cap) >> STS_INTSTS_BIT) & ctrl & CTRL_HOSTINT; 507 if (pci_ints) { 508 /* Call respective PCI Interrupt handler */ 509 for (i = 0; i < 4; i++) { 510 if (pci_ints & (1 << i)) 511 generic_handle_irq(priv->irq_map[i]); 512 } 513 ack = 1; 514 } 515 516 /* 517 * Decode DMA Interrupt only when shared with Err and PCI INTX#, when 518 * the DMA is a unique IRQ the DMA interrupts doesn't end up here, they 519 * goes directly to DMA ISR. 520 */ 521 if ((priv->irq_mode == 0) && (sts_cap & (STS_IDMA | STS_IDMAERR))) { 522 generic_handle_irq(priv->virq_dma); 523 ack = 1; 524 } 525 526 /* 527 * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ 528 * Controller, this must be done after IRQ sources have been handled to 529 * avoid double IRQ generation 530 */ 531 if (ack) 532 desc->irq_data.chip->irq_eoi(&desc->irq_data); 533 } 534 535 /* Create a virtual IRQ */ 536 static unsigned int grpci2_build_device_irq(unsigned int irq) 537 { 538 unsigned int virq = 0, pil; 539 540 pil = 1 << 8; 541 virq = irq_alloc(irq, pil); 542 if (virq == 0) 543 goto out; 544 545 irq_set_chip_and_handler_name(virq, &grpci2_irq, handle_simple_irq, 546 "pcilvl"); 547 irq_set_chip_data(virq, (void *)irq); 548 549 out: 550 return virq; 551 } 552 553 void grpci2_hw_init(struct grpci2_priv *priv) 554 { 555 u32 ahbadr, pciadr, bar_sz, capptr, io_map, data; 556 struct grpci2_regs *regs = priv->regs; 557 int i; 558 struct grpci2_barcfg *barcfg = priv->tgtbars; 559 560 /* Reset any earlier setup */ 561 if (priv->do_reset) { 562 printk(KERN_INFO "GRPCI2: Resetting PCI bus\n"); 563 REGSTORE(regs->ctrl, CTRL_RESET); 564 ssleep(1); /* Wait for boards to settle */ 565 } 566 REGSTORE(regs->ctrl, 0); 567 REGSTORE(regs->sts_cap, ~0); /* Clear Status */ 568 REGSTORE(regs->dma_ctrl, 0); 569 REGSTORE(regs->dma_bdbase, 0); 570 571 /* Translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */ 572 REGSTORE(regs->io_map, REGLOAD(regs->io_map) & 0x0000ffff); 573 574 /* set 1:1 mapping between AHB -> PCI memory space, for all Masters 575 * Each AHB master has it's own mapping registers. Max 16 AHB masters. 576 */ 577 for (i = 0; i < 16; i++) 578 REGSTORE(regs->ahbmst_map[i], priv->pci_area); 579 580 /* Get the GRPCI2 Host PCI ID */ 581 grpci2_cfg_r32(priv, 0, 0, PCI_VENDOR_ID, &priv->pciid); 582 583 /* Get address to first (always defined) capability structure */ 584 grpci2_cfg_r8(priv, 0, 0, PCI_CAPABILITY_LIST, &capptr); 585 586 /* Enable/Disable Byte twisting */ 587 grpci2_cfg_r32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, &io_map); 588 io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0); 589 grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, io_map); 590 591 /* Setup the Host's PCI Target BARs for other peripherals to access, 592 * and do DMA to the host's memory. The target BARs can be sized and 593 * enabled individually. 594 * 595 * User may set custom target BARs, but default is: 596 * The first BARs is used to map kernel low (DMA is part of normal 597 * region on sparc which is SRMMU_MAXMEM big) main memory 1:1 to the 598 * PCI bus, the other BARs are disabled. We assume that the first BAR 599 * is always available. 600 */ 601 for (i = 0; i < 6; i++) { 602 if (barcfg[i].pciadr != ~0 && barcfg[i].ahbadr != ~0) { 603 /* Target BARs must have the proper alignment */ 604 ahbadr = barcfg[i].ahbadr; 605 pciadr = barcfg[i].pciadr; 606 bar_sz = ((pciadr - 1) & ~pciadr) + 1; 607 } else { 608 if (i == 0) { 609 /* Map main memory */ 610 bar_sz = 0xf0000008; /* 256MB prefetchable */ 611 ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN( 612 (unsigned long) &_end)); 613 pciadr = ahbadr; 614 } else { 615 bar_sz = 0; 616 ahbadr = 0; 617 pciadr = 0; 618 } 619 } 620 grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BARSIZE_OFS+i*4, bar_sz); 621 grpci2_cfg_w32(priv, 0, 0, PCI_BASE_ADDRESS_0+i*4, pciadr); 622 grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr); 623 printk(KERN_INFO " TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n", 624 i, pciadr, ahbadr); 625 } 626 627 /* set as bus master and enable pci memory responses */ 628 grpci2_cfg_r32(priv, 0, 0, PCI_COMMAND, &data); 629 data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 630 grpci2_cfg_w32(priv, 0, 0, PCI_COMMAND, data); 631 632 /* Enable Error respone (CPU-TRAP) on illegal memory access. */ 633 REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE); 634 } 635 636 static irqreturn_t grpci2_jump_interrupt(int irq, void *arg) 637 { 638 printk(KERN_ERR "GRPCI2: Jump IRQ happened\n"); 639 return IRQ_NONE; 640 } 641 642 /* Handle GRPCI2 Error Interrupt */ 643 static irqreturn_t grpci2_err_interrupt(int irq, void *arg) 644 { 645 struct grpci2_priv *priv = arg; 646 struct grpci2_regs *regs = priv->regs; 647 unsigned int status; 648 649 status = REGLOAD(regs->sts_cap); 650 if ((status & STS_ERR_IRQ) == 0) 651 return IRQ_NONE; 652 653 if (status & STS_IPARERR) 654 printk(KERN_ERR "GRPCI2: Parity Error\n"); 655 656 if (status & STS_ITGTABRT) 657 printk(KERN_ERR "GRPCI2: Target Abort\n"); 658 659 if (status & STS_IMSTABRT) 660 printk(KERN_ERR "GRPCI2: Master Abort\n"); 661 662 if (status & STS_ISYSERR) 663 printk(KERN_ERR "GRPCI2: System Error\n"); 664 665 /* Clear handled INT TYPE IRQs */ 666 REGSTORE(regs->sts_cap, status & STS_ERR_IRQ); 667 668 return IRQ_HANDLED; 669 } 670 671 static int __devinit grpci2_of_probe(struct platform_device *ofdev) 672 { 673 struct grpci2_regs *regs; 674 struct grpci2_priv *priv; 675 int err, i, len; 676 const int *tmp; 677 unsigned int capability; 678 679 if (grpci2priv) { 680 printk(KERN_ERR "GRPCI2: only one GRPCI2 core supported\n"); 681 return -ENODEV; 682 } 683 684 if (ofdev->num_resources < 3) { 685 printk(KERN_ERR "GRPCI2: not enough APB/AHB resources\n"); 686 return -EIO; 687 } 688 689 /* Find Device Address */ 690 regs = of_ioremap(&ofdev->resource[0], 0, 691 resource_size(&ofdev->resource[0]), 692 "grlib-grpci2 regs"); 693 if (regs == NULL) { 694 printk(KERN_ERR "GRPCI2: ioremap failed\n"); 695 return -EIO; 696 } 697 698 /* 699 * Check that we're in Host Slot and that we can act as a Host Bridge 700 * and not only as target. 701 */ 702 capability = REGLOAD(regs->sts_cap); 703 if ((capability & STS_HOST) || !(capability & STS_MST)) { 704 printk(KERN_INFO "GRPCI2: not in host system slot\n"); 705 err = -EIO; 706 goto err1; 707 } 708 709 priv = grpci2priv = kzalloc(sizeof(struct grpci2_priv), GFP_KERNEL); 710 if (grpci2priv == NULL) { 711 err = -ENOMEM; 712 goto err1; 713 } 714 memset(grpci2priv, 0, sizeof(*grpci2priv)); 715 priv->regs = regs; 716 priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */ 717 priv->irq_mode = (capability & STS_IRQMODE) >> STS_IRQMODE_BIT; 718 719 printk(KERN_INFO "GRPCI2: host found at %p, irq%d\n", regs, priv->irq); 720 721 /* Byte twisting should be made configurable from kernel command line */ 722 priv->bt_enabled = 1; 723 724 /* Let user do custom Target BAR assignment */ 725 tmp = of_get_property(ofdev->dev.of_node, "barcfg", &len); 726 if (tmp && (len == 2*4*6)) 727 memcpy(priv->tgtbars, tmp, 2*4*6); 728 else 729 memset(priv->tgtbars, -1, 2*4*6); 730 731 /* Limit IRQ unmasking in irq_mode 2 and 3 */ 732 tmp = of_get_property(ofdev->dev.of_node, "irq_mask", &len); 733 if (tmp && (len == 4)) 734 priv->do_reset = *tmp; 735 else 736 priv->irq_mask = 0xf; 737 738 /* Optional PCI reset. Force PCI reset on startup */ 739 tmp = of_get_property(ofdev->dev.of_node, "reset", &len); 740 if (tmp && (len == 4)) 741 priv->do_reset = *tmp; 742 else 743 priv->do_reset = 0; 744 745 /* Find PCI Memory, I/O and Configuration Space Windows */ 746 priv->pci_area = ofdev->resource[1].start; 747 priv->pci_area_end = ofdev->resource[1].end+1; 748 priv->pci_io = ofdev->resource[2].start; 749 priv->pci_conf = ofdev->resource[2].start + 0x10000; 750 priv->pci_conf_end = priv->pci_conf + 0x10000; 751 priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000); 752 if (!priv->pci_io_va) { 753 err = -EIO; 754 goto err2; 755 } 756 757 printk(KERN_INFO 758 "GRPCI2: MEMORY SPACE [0x%08lx - 0x%08lx]\n" 759 " I/O SPACE [0x%08lx - 0x%08lx]\n" 760 " CONFIG SPACE [0x%08lx - 0x%08lx]\n", 761 priv->pci_area, priv->pci_area_end-1, 762 priv->pci_io, priv->pci_conf-1, 763 priv->pci_conf, priv->pci_conf_end-1); 764 765 /* 766 * I/O Space resources in I/O Window mapped into Virtual Adr Space 767 * We never use low 4KB because some devices seem have problems using 768 * address 0. 769 */ 770 memset(&priv->info.io_space, 0, sizeof(struct resource)); 771 priv->info.io_space.name = "GRPCI2 PCI I/O Space"; 772 priv->info.io_space.start = priv->pci_io_va + 0x1000; 773 priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1; 774 priv->info.io_space.flags = IORESOURCE_IO; 775 776 /* 777 * GRPCI2 has no prefetchable memory, map everything as 778 * non-prefetchable memory 779 */ 780 memset(&priv->info.mem_space, 0, sizeof(struct resource)); 781 priv->info.mem_space.name = "GRPCI2 PCI MEM Space"; 782 priv->info.mem_space.start = priv->pci_area; 783 priv->info.mem_space.end = priv->pci_area_end - 1; 784 priv->info.mem_space.flags = IORESOURCE_MEM; 785 786 if (request_resource(&iomem_resource, &priv->info.mem_space) < 0) 787 goto err3; 788 if (request_resource(&ioport_resource, &priv->info.io_space) < 0) 789 goto err4; 790 791 grpci2_hw_init(priv); 792 793 /* 794 * Get PCI Interrupt to System IRQ mapping and setup IRQ handling 795 * Error IRQ always on PCI INTA. 796 */ 797 if (priv->irq_mode < 2) { 798 /* All PCI interrupts are shared using the same system IRQ */ 799 leon_update_virq_handling(priv->irq, grpci2_pci_flow_irq, 800 "pcilvl", 0); 801 802 priv->irq_map[0] = grpci2_build_device_irq(1); 803 priv->irq_map[1] = grpci2_build_device_irq(2); 804 priv->irq_map[2] = grpci2_build_device_irq(3); 805 priv->irq_map[3] = grpci2_build_device_irq(4); 806 807 priv->virq_err = grpci2_build_device_irq(5); 808 if (priv->irq_mode & 1) 809 priv->virq_dma = ofdev->archdata.irqs[1]; 810 else 811 priv->virq_dma = grpci2_build_device_irq(6); 812 813 /* Enable IRQs on LEON IRQ controller */ 814 err = request_irq(priv->irq, grpci2_jump_interrupt, 0, 815 "GRPCI2_JUMP", priv); 816 if (err) 817 printk(KERN_ERR "GRPCI2: ERR IRQ request failed\n"); 818 } else { 819 /* All PCI interrupts have an unique IRQ interrupt */ 820 for (i = 0; i < 4; i++) { 821 /* Make LEON IRQ layer handle level IRQ by acking */ 822 leon_update_virq_handling(ofdev->archdata.irqs[i], 823 handle_fasteoi_irq, "pcilvl", 824 1); 825 priv->irq_map[i] = ofdev->archdata.irqs[i]; 826 } 827 priv->virq_err = priv->irq_map[0]; 828 if (priv->irq_mode & 1) 829 priv->virq_dma = ofdev->archdata.irqs[4]; 830 else 831 priv->virq_dma = priv->irq_map[0]; 832 833 /* Unmask all PCI interrupts, request_irq will not do that */ 834 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf)); 835 } 836 837 /* Setup IRQ handler for non-configuration space access errors */ 838 err = request_irq(priv->virq_err, grpci2_err_interrupt, IRQF_SHARED, 839 "GRPCI2_ERR", priv); 840 if (err) { 841 printk(KERN_DEBUG "GRPCI2: ERR VIRQ request failed: %d\n", err); 842 goto err5; 843 } 844 845 /* 846 * Enable Error Interrupts. PCI interrupts are unmasked once request_irq 847 * is called by the PCI Device drivers 848 */ 849 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl) | CTRL_EI | CTRL_SI); 850 851 /* Init common layer and scan buses */ 852 priv->info.ops = &grpci2_ops; 853 priv->info.map_irq = grpci2_map_irq; 854 leon_pci_init(ofdev, &priv->info); 855 856 return 0; 857 858 err5: 859 release_resource(&priv->info.io_space); 860 err4: 861 release_resource(&priv->info.mem_space); 862 err3: 863 err = -ENOMEM; 864 iounmap((void *)priv->pci_io_va); 865 err2: 866 kfree(priv); 867 err1: 868 of_iounmap(&ofdev->resource[0], regs, 869 resource_size(&ofdev->resource[0])); 870 return err; 871 } 872 873 static struct of_device_id grpci2_of_match[] = { 874 { 875 .name = "GAISLER_GRPCI2", 876 }, 877 { 878 .name = "01_07c", 879 }, 880 {}, 881 }; 882 883 static struct platform_driver grpci2_of_driver = { 884 .driver = { 885 .name = "grpci2", 886 .owner = THIS_MODULE, 887 .of_match_table = grpci2_of_match, 888 }, 889 .probe = grpci2_of_probe, 890 }; 891 892 static int __init grpci2_init(void) 893 { 894 return platform_driver_register(&grpci2_of_driver); 895 } 896 897 subsys_initcall(grpci2_init); 898