1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * leon_pci.c: LEON Host PCI support 4 * 5 * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom 6 * 7 * Code is partially derived from pcic.c 8 */ 9 10 #include <linux/of_device.h> 11 #include <linux/kernel.h> 12 #include <linux/pci.h> 13 #include <linux/export.h> 14 #include <asm/leon.h> 15 #include <asm/leon_pci.h> 16 17 /* The LEON architecture does not rely on a BIOS or bootloader to setup 18 * PCI for us. The Linux generic routines are used to setup resources, 19 * reset values of configuration-space register settings are preserved. 20 * 21 * PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is 22 * accessed through a Window which is translated to low 64KB in PCI space, the 23 * first 4KB is not used so 60KB is available. 24 */ 25 void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info) 26 { 27 LIST_HEAD(resources); 28 struct pci_bus *root_bus; 29 struct pci_host_bridge *bridge; 30 int ret; 31 32 bridge = pci_alloc_host_bridge(0); 33 if (!bridge) 34 return; 35 36 pci_add_resource_offset(&resources, &info->io_space, 37 info->io_space.start - 0x1000); 38 pci_add_resource(&resources, &info->mem_space); 39 info->busn.flags = IORESOURCE_BUS; 40 pci_add_resource(&resources, &info->busn); 41 42 list_splice_init(&resources, &bridge->windows); 43 bridge->dev.parent = &ofdev->dev; 44 bridge->sysdata = info; 45 bridge->busnr = 0; 46 bridge->ops = info->ops; 47 bridge->swizzle_irq = pci_common_swizzle; 48 bridge->map_irq = info->map_irq; 49 50 ret = pci_scan_root_bus_bridge(bridge); 51 if (ret) { 52 pci_free_host_bridge(bridge); 53 return; 54 } 55 56 root_bus = bridge->bus; 57 58 /* Assign devices with resources */ 59 pci_assign_unassigned_resources(); 60 pci_bus_add_devices(root_bus); 61 } 62 63 void pcibios_fixup_bus(struct pci_bus *pbus) 64 { 65 struct pci_dev *dev; 66 int i, has_io, has_mem; 67 u16 cmd; 68 69 list_for_each_entry(dev, &pbus->devices, bus_list) { 70 /* 71 * We can not rely on that the bootloader has enabled I/O 72 * or memory access to PCI devices. Instead we enable it here 73 * if the device has BARs of respective type. 74 */ 75 has_io = has_mem = 0; 76 for (i = 0; i < PCI_ROM_RESOURCE; i++) { 77 unsigned long f = dev->resource[i].flags; 78 if (f & IORESOURCE_IO) 79 has_io = 1; 80 else if (f & IORESOURCE_MEM) 81 has_mem = 1; 82 } 83 /* ROM BARs are mapped into 32-bit memory space */ 84 if (dev->resource[PCI_ROM_RESOURCE].end != 0) { 85 dev->resource[PCI_ROM_RESOURCE].flags |= 86 IORESOURCE_ROM_ENABLE; 87 has_mem = 1; 88 } 89 pci_bus_read_config_word(pbus, dev->devfn, PCI_COMMAND, &cmd); 90 if (has_io && !(cmd & PCI_COMMAND_IO)) { 91 #ifdef CONFIG_PCI_DEBUG 92 printk(KERN_INFO "LEONPCI: Enabling I/O for dev %s\n", 93 pci_name(dev)); 94 #endif 95 cmd |= PCI_COMMAND_IO; 96 pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND, 97 cmd); 98 } 99 if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) { 100 #ifdef CONFIG_PCI_DEBUG 101 printk(KERN_INFO "LEONPCI: Enabling MEMORY for dev" 102 "%s\n", pci_name(dev)); 103 #endif 104 cmd |= PCI_COMMAND_MEMORY; 105 pci_bus_write_config_word(pbus, dev->devfn, PCI_COMMAND, 106 cmd); 107 } 108 } 109 } 110