1 /* irq.c: UltraSparc IRQ handling/init/registry. 2 * 3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) 4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) 6 */ 7 8 #include <linux/module.h> 9 #include <linux/sched.h> 10 #include <linux/linkage.h> 11 #include <linux/ptrace.h> 12 #include <linux/errno.h> 13 #include <linux/kernel_stat.h> 14 #include <linux/signal.h> 15 #include <linux/mm.h> 16 #include <linux/interrupt.h> 17 #include <linux/slab.h> 18 #include <linux/random.h> 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/proc_fs.h> 22 #include <linux/seq_file.h> 23 #include <linux/bootmem.h> 24 #include <linux/irq.h> 25 26 #include <asm/ptrace.h> 27 #include <asm/processor.h> 28 #include <asm/atomic.h> 29 #include <asm/system.h> 30 #include <asm/irq.h> 31 #include <asm/io.h> 32 #include <asm/iommu.h> 33 #include <asm/upa.h> 34 #include <asm/oplib.h> 35 #include <asm/prom.h> 36 #include <asm/timer.h> 37 #include <asm/smp.h> 38 #include <asm/starfire.h> 39 #include <asm/uaccess.h> 40 #include <asm/cache.h> 41 #include <asm/cpudata.h> 42 #include <asm/auxio.h> 43 #include <asm/head.h> 44 #include <asm/hypervisor.h> 45 #include <asm/cacheflush.h> 46 47 #include "entry.h" 48 49 #define NUM_IVECS (IMAP_INR + 1) 50 51 struct ino_bucket *ivector_table; 52 unsigned long ivector_table_pa; 53 54 /* On several sun4u processors, it is illegal to mix bypass and 55 * non-bypass accesses. Therefore we access all INO buckets 56 * using bypass accesses only. 57 */ 58 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa) 59 { 60 unsigned long ret; 61 62 __asm__ __volatile__("ldxa [%1] %2, %0" 63 : "=&r" (ret) 64 : "r" (bucket_pa + 65 offsetof(struct ino_bucket, 66 __irq_chain_pa)), 67 "i" (ASI_PHYS_USE_EC)); 68 69 return ret; 70 } 71 72 static void bucket_clear_chain_pa(unsigned long bucket_pa) 73 { 74 __asm__ __volatile__("stxa %%g0, [%0] %1" 75 : /* no outputs */ 76 : "r" (bucket_pa + 77 offsetof(struct ino_bucket, 78 __irq_chain_pa)), 79 "i" (ASI_PHYS_USE_EC)); 80 } 81 82 static unsigned int bucket_get_virt_irq(unsigned long bucket_pa) 83 { 84 unsigned int ret; 85 86 __asm__ __volatile__("lduwa [%1] %2, %0" 87 : "=&r" (ret) 88 : "r" (bucket_pa + 89 offsetof(struct ino_bucket, 90 __virt_irq)), 91 "i" (ASI_PHYS_USE_EC)); 92 93 return ret; 94 } 95 96 static void bucket_set_virt_irq(unsigned long bucket_pa, 97 unsigned int virt_irq) 98 { 99 __asm__ __volatile__("stwa %0, [%1] %2" 100 : /* no outputs */ 101 : "r" (virt_irq), 102 "r" (bucket_pa + 103 offsetof(struct ino_bucket, 104 __virt_irq)), 105 "i" (ASI_PHYS_USE_EC)); 106 } 107 108 #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) 109 110 static struct { 111 unsigned int dev_handle; 112 unsigned int dev_ino; 113 unsigned int in_use; 114 } virt_irq_table[NR_IRQS]; 115 static DEFINE_SPINLOCK(virt_irq_alloc_lock); 116 117 unsigned char virt_irq_alloc(unsigned int dev_handle, 118 unsigned int dev_ino) 119 { 120 unsigned long flags; 121 unsigned char ent; 122 123 BUILD_BUG_ON(NR_IRQS >= 256); 124 125 spin_lock_irqsave(&virt_irq_alloc_lock, flags); 126 127 for (ent = 1; ent < NR_IRQS; ent++) { 128 if (!virt_irq_table[ent].in_use) 129 break; 130 } 131 if (ent >= NR_IRQS) { 132 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); 133 ent = 0; 134 } else { 135 virt_irq_table[ent].dev_handle = dev_handle; 136 virt_irq_table[ent].dev_ino = dev_ino; 137 virt_irq_table[ent].in_use = 1; 138 } 139 140 spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); 141 142 return ent; 143 } 144 145 #ifdef CONFIG_PCI_MSI 146 void virt_irq_free(unsigned int virt_irq) 147 { 148 unsigned long flags; 149 150 if (virt_irq >= NR_IRQS) 151 return; 152 153 spin_lock_irqsave(&virt_irq_alloc_lock, flags); 154 155 virt_irq_table[virt_irq].in_use = 0; 156 157 spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); 158 } 159 #endif 160 161 /* 162 * /proc/interrupts printing: 163 */ 164 165 int show_interrupts(struct seq_file *p, void *v) 166 { 167 int i = *(loff_t *) v, j; 168 struct irqaction * action; 169 unsigned long flags; 170 171 if (i == 0) { 172 seq_printf(p, " "); 173 for_each_online_cpu(j) 174 seq_printf(p, "CPU%d ",j); 175 seq_putc(p, '\n'); 176 } 177 178 if (i < NR_IRQS) { 179 spin_lock_irqsave(&irq_desc[i].lock, flags); 180 action = irq_desc[i].action; 181 if (!action) 182 goto skip; 183 seq_printf(p, "%3d: ",i); 184 #ifndef CONFIG_SMP 185 seq_printf(p, "%10u ", kstat_irqs(i)); 186 #else 187 for_each_online_cpu(j) 188 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 189 #endif 190 seq_printf(p, " %9s", irq_desc[i].chip->typename); 191 seq_printf(p, " %s", action->name); 192 193 for (action=action->next; action; action = action->next) 194 seq_printf(p, ", %s", action->name); 195 196 seq_putc(p, '\n'); 197 skip: 198 spin_unlock_irqrestore(&irq_desc[i].lock, flags); 199 } else if (i == NR_IRQS) { 200 seq_printf(p, "NMI: "); 201 for_each_online_cpu(j) 202 seq_printf(p, "%10u ", cpu_data(j).__nmi_count); 203 seq_printf(p, " Non-maskable interrupts\n"); 204 } 205 return 0; 206 } 207 208 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) 209 { 210 unsigned int tid; 211 212 if (this_is_starfire) { 213 tid = starfire_translate(imap, cpuid); 214 tid <<= IMAP_TID_SHIFT; 215 tid &= IMAP_TID_UPA; 216 } else { 217 if (tlb_type == cheetah || tlb_type == cheetah_plus) { 218 unsigned long ver; 219 220 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); 221 if ((ver >> 32UL) == __JALAPENO_ID || 222 (ver >> 32UL) == __SERRANO_ID) { 223 tid = cpuid << IMAP_TID_SHIFT; 224 tid &= IMAP_TID_JBUS; 225 } else { 226 unsigned int a = cpuid & 0x1f; 227 unsigned int n = (cpuid >> 5) & 0x1f; 228 229 tid = ((a << IMAP_AID_SHIFT) | 230 (n << IMAP_NID_SHIFT)); 231 tid &= (IMAP_AID_SAFARI | 232 IMAP_NID_SAFARI);; 233 } 234 } else { 235 tid = cpuid << IMAP_TID_SHIFT; 236 tid &= IMAP_TID_UPA; 237 } 238 } 239 240 return tid; 241 } 242 243 struct irq_handler_data { 244 unsigned long iclr; 245 unsigned long imap; 246 247 void (*pre_handler)(unsigned int, void *, void *); 248 void *arg1; 249 void *arg2; 250 }; 251 252 #ifdef CONFIG_SMP 253 static int irq_choose_cpu(unsigned int virt_irq) 254 { 255 cpumask_t mask; 256 int cpuid; 257 258 cpumask_copy(&mask, irq_desc[virt_irq].affinity); 259 if (cpus_equal(mask, CPU_MASK_ALL)) { 260 static int irq_rover; 261 static DEFINE_SPINLOCK(irq_rover_lock); 262 unsigned long flags; 263 264 /* Round-robin distribution... */ 265 do_round_robin: 266 spin_lock_irqsave(&irq_rover_lock, flags); 267 268 while (!cpu_online(irq_rover)) { 269 if (++irq_rover >= nr_cpu_ids) 270 irq_rover = 0; 271 } 272 cpuid = irq_rover; 273 do { 274 if (++irq_rover >= nr_cpu_ids) 275 irq_rover = 0; 276 } while (!cpu_online(irq_rover)); 277 278 spin_unlock_irqrestore(&irq_rover_lock, flags); 279 } else { 280 cpumask_t tmp; 281 282 cpus_and(tmp, cpu_online_map, mask); 283 284 if (cpus_empty(tmp)) 285 goto do_round_robin; 286 287 cpuid = first_cpu(tmp); 288 } 289 290 return cpuid; 291 } 292 #else 293 static int irq_choose_cpu(unsigned int virt_irq) 294 { 295 return real_hard_smp_processor_id(); 296 } 297 #endif 298 299 static void sun4u_irq_enable(unsigned int virt_irq) 300 { 301 struct irq_handler_data *data = get_irq_chip_data(virt_irq); 302 303 if (likely(data)) { 304 unsigned long cpuid, imap, val; 305 unsigned int tid; 306 307 cpuid = irq_choose_cpu(virt_irq); 308 imap = data->imap; 309 310 tid = sun4u_compute_tid(imap, cpuid); 311 312 val = upa_readq(imap); 313 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | 314 IMAP_AID_SAFARI | IMAP_NID_SAFARI); 315 val |= tid | IMAP_VALID; 316 upa_writeq(val, imap); 317 upa_writeq(ICLR_IDLE, data->iclr); 318 } 319 } 320 321 static void sun4u_set_affinity(unsigned int virt_irq, 322 const struct cpumask *mask) 323 { 324 sun4u_irq_enable(virt_irq); 325 } 326 327 /* Don't do anything. The desc->status check for IRQ_DISABLED in 328 * handler_irq() will skip the handler call and that will leave the 329 * interrupt in the sent state. The next ->enable() call will hit the 330 * ICLR register to reset the state machine. 331 * 332 * This scheme is necessary, instead of clearing the Valid bit in the 333 * IMAP register, to handle the case of IMAP registers being shared by 334 * multiple INOs (and thus ICLR registers). Since we use a different 335 * virtual IRQ for each shared IMAP instance, the generic code thinks 336 * there is only one user so it prematurely calls ->disable() on 337 * free_irq(). 338 * 339 * We have to provide an explicit ->disable() method instead of using 340 * NULL to get the default. The reason is that if the generic code 341 * sees that, it also hooks up a default ->shutdown method which 342 * invokes ->mask() which we do not want. See irq_chip_set_defaults(). 343 */ 344 static void sun4u_irq_disable(unsigned int virt_irq) 345 { 346 } 347 348 static void sun4u_irq_eoi(unsigned int virt_irq) 349 { 350 struct irq_handler_data *data = get_irq_chip_data(virt_irq); 351 struct irq_desc *desc = irq_desc + virt_irq; 352 353 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) 354 return; 355 356 if (likely(data)) 357 upa_writeq(ICLR_IDLE, data->iclr); 358 } 359 360 static void sun4v_irq_enable(unsigned int virt_irq) 361 { 362 unsigned int ino = virt_irq_table[virt_irq].dev_ino; 363 unsigned long cpuid = irq_choose_cpu(virt_irq); 364 int err; 365 366 err = sun4v_intr_settarget(ino, cpuid); 367 if (err != HV_EOK) 368 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " 369 "err(%d)\n", ino, cpuid, err); 370 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); 371 if (err != HV_EOK) 372 printk(KERN_ERR "sun4v_intr_setstate(%x): " 373 "err(%d)\n", ino, err); 374 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); 375 if (err != HV_EOK) 376 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", 377 ino, err); 378 } 379 380 static void sun4v_set_affinity(unsigned int virt_irq, 381 const struct cpumask *mask) 382 { 383 unsigned int ino = virt_irq_table[virt_irq].dev_ino; 384 unsigned long cpuid = irq_choose_cpu(virt_irq); 385 int err; 386 387 err = sun4v_intr_settarget(ino, cpuid); 388 if (err != HV_EOK) 389 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " 390 "err(%d)\n", ino, cpuid, err); 391 } 392 393 static void sun4v_irq_disable(unsigned int virt_irq) 394 { 395 unsigned int ino = virt_irq_table[virt_irq].dev_ino; 396 int err; 397 398 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); 399 if (err != HV_EOK) 400 printk(KERN_ERR "sun4v_intr_setenabled(%x): " 401 "err(%d)\n", ino, err); 402 } 403 404 static void sun4v_irq_eoi(unsigned int virt_irq) 405 { 406 unsigned int ino = virt_irq_table[virt_irq].dev_ino; 407 struct irq_desc *desc = irq_desc + virt_irq; 408 int err; 409 410 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) 411 return; 412 413 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); 414 if (err != HV_EOK) 415 printk(KERN_ERR "sun4v_intr_setstate(%x): " 416 "err(%d)\n", ino, err); 417 } 418 419 static void sun4v_virq_enable(unsigned int virt_irq) 420 { 421 unsigned long cpuid, dev_handle, dev_ino; 422 int err; 423 424 cpuid = irq_choose_cpu(virt_irq); 425 426 dev_handle = virt_irq_table[virt_irq].dev_handle; 427 dev_ino = virt_irq_table[virt_irq].dev_ino; 428 429 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); 430 if (err != HV_EOK) 431 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " 432 "err(%d)\n", 433 dev_handle, dev_ino, cpuid, err); 434 err = sun4v_vintr_set_state(dev_handle, dev_ino, 435 HV_INTR_STATE_IDLE); 436 if (err != HV_EOK) 437 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," 438 "HV_INTR_STATE_IDLE): err(%d)\n", 439 dev_handle, dev_ino, err); 440 err = sun4v_vintr_set_valid(dev_handle, dev_ino, 441 HV_INTR_ENABLED); 442 if (err != HV_EOK) 443 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," 444 "HV_INTR_ENABLED): err(%d)\n", 445 dev_handle, dev_ino, err); 446 } 447 448 static void sun4v_virt_set_affinity(unsigned int virt_irq, 449 const struct cpumask *mask) 450 { 451 unsigned long cpuid, dev_handle, dev_ino; 452 int err; 453 454 cpuid = irq_choose_cpu(virt_irq); 455 456 dev_handle = virt_irq_table[virt_irq].dev_handle; 457 dev_ino = virt_irq_table[virt_irq].dev_ino; 458 459 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); 460 if (err != HV_EOK) 461 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " 462 "err(%d)\n", 463 dev_handle, dev_ino, cpuid, err); 464 } 465 466 static void sun4v_virq_disable(unsigned int virt_irq) 467 { 468 unsigned long dev_handle, dev_ino; 469 int err; 470 471 dev_handle = virt_irq_table[virt_irq].dev_handle; 472 dev_ino = virt_irq_table[virt_irq].dev_ino; 473 474 err = sun4v_vintr_set_valid(dev_handle, dev_ino, 475 HV_INTR_DISABLED); 476 if (err != HV_EOK) 477 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," 478 "HV_INTR_DISABLED): err(%d)\n", 479 dev_handle, dev_ino, err); 480 } 481 482 static void sun4v_virq_eoi(unsigned int virt_irq) 483 { 484 struct irq_desc *desc = irq_desc + virt_irq; 485 unsigned long dev_handle, dev_ino; 486 int err; 487 488 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) 489 return; 490 491 dev_handle = virt_irq_table[virt_irq].dev_handle; 492 dev_ino = virt_irq_table[virt_irq].dev_ino; 493 494 err = sun4v_vintr_set_state(dev_handle, dev_ino, 495 HV_INTR_STATE_IDLE); 496 if (err != HV_EOK) 497 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," 498 "HV_INTR_STATE_IDLE): err(%d)\n", 499 dev_handle, dev_ino, err); 500 } 501 502 static struct irq_chip sun4u_irq = { 503 .typename = "sun4u", 504 .enable = sun4u_irq_enable, 505 .disable = sun4u_irq_disable, 506 .eoi = sun4u_irq_eoi, 507 .set_affinity = sun4u_set_affinity, 508 }; 509 510 static struct irq_chip sun4v_irq = { 511 .typename = "sun4v", 512 .enable = sun4v_irq_enable, 513 .disable = sun4v_irq_disable, 514 .eoi = sun4v_irq_eoi, 515 .set_affinity = sun4v_set_affinity, 516 }; 517 518 static struct irq_chip sun4v_virq = { 519 .typename = "vsun4v", 520 .enable = sun4v_virq_enable, 521 .disable = sun4v_virq_disable, 522 .eoi = sun4v_virq_eoi, 523 .set_affinity = sun4v_virt_set_affinity, 524 }; 525 526 static void pre_flow_handler(unsigned int virt_irq, 527 struct irq_desc *desc) 528 { 529 struct irq_handler_data *data = get_irq_chip_data(virt_irq); 530 unsigned int ino = virt_irq_table[virt_irq].dev_ino; 531 532 data->pre_handler(ino, data->arg1, data->arg2); 533 534 handle_fasteoi_irq(virt_irq, desc); 535 } 536 537 void irq_install_pre_handler(int virt_irq, 538 void (*func)(unsigned int, void *, void *), 539 void *arg1, void *arg2) 540 { 541 struct irq_handler_data *data = get_irq_chip_data(virt_irq); 542 struct irq_desc *desc = irq_desc + virt_irq; 543 544 data->pre_handler = func; 545 data->arg1 = arg1; 546 data->arg2 = arg2; 547 548 desc->handle_irq = pre_flow_handler; 549 } 550 551 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) 552 { 553 struct ino_bucket *bucket; 554 struct irq_handler_data *data; 555 unsigned int virt_irq; 556 int ino; 557 558 BUG_ON(tlb_type == hypervisor); 559 560 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; 561 bucket = &ivector_table[ino]; 562 virt_irq = bucket_get_virt_irq(__pa(bucket)); 563 if (!virt_irq) { 564 virt_irq = virt_irq_alloc(0, ino); 565 bucket_set_virt_irq(__pa(bucket), virt_irq); 566 set_irq_chip_and_handler_name(virt_irq, 567 &sun4u_irq, 568 handle_fasteoi_irq, 569 "IVEC"); 570 } 571 572 data = get_irq_chip_data(virt_irq); 573 if (unlikely(data)) 574 goto out; 575 576 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); 577 if (unlikely(!data)) { 578 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); 579 prom_halt(); 580 } 581 set_irq_chip_data(virt_irq, data); 582 583 data->imap = imap; 584 data->iclr = iclr; 585 586 out: 587 return virt_irq; 588 } 589 590 static unsigned int sun4v_build_common(unsigned long sysino, 591 struct irq_chip *chip) 592 { 593 struct ino_bucket *bucket; 594 struct irq_handler_data *data; 595 unsigned int virt_irq; 596 597 BUG_ON(tlb_type != hypervisor); 598 599 bucket = &ivector_table[sysino]; 600 virt_irq = bucket_get_virt_irq(__pa(bucket)); 601 if (!virt_irq) { 602 virt_irq = virt_irq_alloc(0, sysino); 603 bucket_set_virt_irq(__pa(bucket), virt_irq); 604 set_irq_chip_and_handler_name(virt_irq, chip, 605 handle_fasteoi_irq, 606 "IVEC"); 607 } 608 609 data = get_irq_chip_data(virt_irq); 610 if (unlikely(data)) 611 goto out; 612 613 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); 614 if (unlikely(!data)) { 615 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); 616 prom_halt(); 617 } 618 set_irq_chip_data(virt_irq, data); 619 620 /* Catch accidental accesses to these things. IMAP/ICLR handling 621 * is done by hypervisor calls on sun4v platforms, not by direct 622 * register accesses. 623 */ 624 data->imap = ~0UL; 625 data->iclr = ~0UL; 626 627 out: 628 return virt_irq; 629 } 630 631 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) 632 { 633 unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); 634 635 return sun4v_build_common(sysino, &sun4v_irq); 636 } 637 638 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) 639 { 640 struct irq_handler_data *data; 641 unsigned long hv_err, cookie; 642 struct ino_bucket *bucket; 643 struct irq_desc *desc; 644 unsigned int virt_irq; 645 646 bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); 647 if (unlikely(!bucket)) 648 return 0; 649 __flush_dcache_range((unsigned long) bucket, 650 ((unsigned long) bucket + 651 sizeof(struct ino_bucket))); 652 653 virt_irq = virt_irq_alloc(devhandle, devino); 654 bucket_set_virt_irq(__pa(bucket), virt_irq); 655 656 set_irq_chip_and_handler_name(virt_irq, &sun4v_virq, 657 handle_fasteoi_irq, 658 "IVEC"); 659 660 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); 661 if (unlikely(!data)) 662 return 0; 663 664 /* In order to make the LDC channel startup sequence easier, 665 * especially wrt. locking, we do not let request_irq() enable 666 * the interrupt. 667 */ 668 desc = irq_desc + virt_irq; 669 desc->status |= IRQ_NOAUTOEN; 670 671 set_irq_chip_data(virt_irq, data); 672 673 /* Catch accidental accesses to these things. IMAP/ICLR handling 674 * is done by hypervisor calls on sun4v platforms, not by direct 675 * register accesses. 676 */ 677 data->imap = ~0UL; 678 data->iclr = ~0UL; 679 680 cookie = ~__pa(bucket); 681 hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie); 682 if (hv_err) { 683 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " 684 "err=%lu\n", devhandle, devino, hv_err); 685 prom_halt(); 686 } 687 688 return virt_irq; 689 } 690 691 void ack_bad_irq(unsigned int virt_irq) 692 { 693 unsigned int ino = virt_irq_table[virt_irq].dev_ino; 694 695 if (!ino) 696 ino = 0xdeadbeef; 697 698 printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", 699 ino, virt_irq); 700 } 701 702 void *hardirq_stack[NR_CPUS]; 703 void *softirq_stack[NR_CPUS]; 704 705 static __attribute__((always_inline)) void *set_hardirq_stack(void) 706 { 707 void *orig_sp, *sp = hardirq_stack[smp_processor_id()]; 708 709 __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp)); 710 if (orig_sp < sp || 711 orig_sp > (sp + THREAD_SIZE)) { 712 sp += THREAD_SIZE - 192 - STACK_BIAS; 713 __asm__ __volatile__("mov %0, %%sp" : : "r" (sp)); 714 } 715 716 return orig_sp; 717 } 718 static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp) 719 { 720 __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp)); 721 } 722 723 void handler_irq(int irq, struct pt_regs *regs) 724 { 725 unsigned long pstate, bucket_pa; 726 struct pt_regs *old_regs; 727 void *orig_sp; 728 729 clear_softint(1 << irq); 730 731 old_regs = set_irq_regs(regs); 732 irq_enter(); 733 734 /* Grab an atomic snapshot of the pending IVECs. */ 735 __asm__ __volatile__("rdpr %%pstate, %0\n\t" 736 "wrpr %0, %3, %%pstate\n\t" 737 "ldx [%2], %1\n\t" 738 "stx %%g0, [%2]\n\t" 739 "wrpr %0, 0x0, %%pstate\n\t" 740 : "=&r" (pstate), "=&r" (bucket_pa) 741 : "r" (irq_work_pa(smp_processor_id())), 742 "i" (PSTATE_IE) 743 : "memory"); 744 745 orig_sp = set_hardirq_stack(); 746 747 while (bucket_pa) { 748 struct irq_desc *desc; 749 unsigned long next_pa; 750 unsigned int virt_irq; 751 752 next_pa = bucket_get_chain_pa(bucket_pa); 753 virt_irq = bucket_get_virt_irq(bucket_pa); 754 bucket_clear_chain_pa(bucket_pa); 755 756 desc = irq_desc + virt_irq; 757 758 if (!(desc->status & IRQ_DISABLED)) 759 desc->handle_irq(virt_irq, desc); 760 761 bucket_pa = next_pa; 762 } 763 764 restore_hardirq_stack(orig_sp); 765 766 irq_exit(); 767 set_irq_regs(old_regs); 768 } 769 770 void do_softirq(void) 771 { 772 unsigned long flags; 773 774 if (in_interrupt()) 775 return; 776 777 local_irq_save(flags); 778 779 if (local_softirq_pending()) { 780 void *orig_sp, *sp = softirq_stack[smp_processor_id()]; 781 782 sp += THREAD_SIZE - 192 - STACK_BIAS; 783 784 __asm__ __volatile__("mov %%sp, %0\n\t" 785 "mov %1, %%sp" 786 : "=&r" (orig_sp) 787 : "r" (sp)); 788 __do_softirq(); 789 __asm__ __volatile__("mov %0, %%sp" 790 : : "r" (orig_sp)); 791 } 792 793 local_irq_restore(flags); 794 } 795 796 #ifdef CONFIG_HOTPLUG_CPU 797 void fixup_irqs(void) 798 { 799 unsigned int irq; 800 801 for (irq = 0; irq < NR_IRQS; irq++) { 802 unsigned long flags; 803 804 spin_lock_irqsave(&irq_desc[irq].lock, flags); 805 if (irq_desc[irq].action && 806 !(irq_desc[irq].status & IRQ_PER_CPU)) { 807 if (irq_desc[irq].chip->set_affinity) 808 irq_desc[irq].chip->set_affinity(irq, 809 irq_desc[irq].affinity); 810 } 811 spin_unlock_irqrestore(&irq_desc[irq].lock, flags); 812 } 813 814 tick_ops->disable_irq(); 815 } 816 #endif 817 818 struct sun5_timer { 819 u64 count0; 820 u64 limit0; 821 u64 count1; 822 u64 limit1; 823 }; 824 825 static struct sun5_timer *prom_timers; 826 static u64 prom_limit0, prom_limit1; 827 828 static void map_prom_timers(void) 829 { 830 struct device_node *dp; 831 const unsigned int *addr; 832 833 /* PROM timer node hangs out in the top level of device siblings... */ 834 dp = of_find_node_by_path("/"); 835 dp = dp->child; 836 while (dp) { 837 if (!strcmp(dp->name, "counter-timer")) 838 break; 839 dp = dp->sibling; 840 } 841 842 /* Assume if node is not present, PROM uses different tick mechanism 843 * which we should not care about. 844 */ 845 if (!dp) { 846 prom_timers = (struct sun5_timer *) 0; 847 return; 848 } 849 850 /* If PROM is really using this, it must be mapped by him. */ 851 addr = of_get_property(dp, "address", NULL); 852 if (!addr) { 853 prom_printf("PROM does not have timer mapped, trying to continue.\n"); 854 prom_timers = (struct sun5_timer *) 0; 855 return; 856 } 857 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); 858 } 859 860 static void kill_prom_timer(void) 861 { 862 if (!prom_timers) 863 return; 864 865 /* Save them away for later. */ 866 prom_limit0 = prom_timers->limit0; 867 prom_limit1 = prom_timers->limit1; 868 869 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. 870 * We turn both off here just to be paranoid. 871 */ 872 prom_timers->limit0 = 0; 873 prom_timers->limit1 = 0; 874 875 /* Wheee, eat the interrupt packet too... */ 876 __asm__ __volatile__( 877 " mov 0x40, %%g2\n" 878 " ldxa [%%g0] %0, %%g1\n" 879 " ldxa [%%g2] %1, %%g1\n" 880 " stxa %%g0, [%%g0] %0\n" 881 " membar #Sync\n" 882 : /* no outputs */ 883 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) 884 : "g1", "g2"); 885 } 886 887 void notrace init_irqwork_curcpu(void) 888 { 889 int cpu = hard_smp_processor_id(); 890 891 trap_block[cpu].irq_worklist_pa = 0UL; 892 } 893 894 /* Please be very careful with register_one_mondo() and 895 * sun4v_register_mondo_queues(). 896 * 897 * On SMP this gets invoked from the CPU trampoline before 898 * the cpu has fully taken over the trap table from OBP, 899 * and it's kernel stack + %g6 thread register state is 900 * not fully cooked yet. 901 * 902 * Therefore you cannot make any OBP calls, not even prom_printf, 903 * from these two routines. 904 */ 905 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) 906 { 907 unsigned long num_entries = (qmask + 1) / 64; 908 unsigned long status; 909 910 status = sun4v_cpu_qconf(type, paddr, num_entries); 911 if (status != HV_EOK) { 912 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " 913 "err %lu\n", type, paddr, num_entries, status); 914 prom_halt(); 915 } 916 } 917 918 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu) 919 { 920 struct trap_per_cpu *tb = &trap_block[this_cpu]; 921 922 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, 923 tb->cpu_mondo_qmask); 924 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, 925 tb->dev_mondo_qmask); 926 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, 927 tb->resum_qmask); 928 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, 929 tb->nonresum_qmask); 930 } 931 932 static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) 933 { 934 unsigned long size = PAGE_ALIGN(qmask + 1); 935 void *p = __alloc_bootmem(size, size, 0); 936 if (!p) { 937 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); 938 prom_halt(); 939 } 940 941 *pa_ptr = __pa(p); 942 } 943 944 static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) 945 { 946 unsigned long size = PAGE_ALIGN(qmask + 1); 947 void *p = __alloc_bootmem(size, size, 0); 948 949 if (!p) { 950 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); 951 prom_halt(); 952 } 953 954 *pa_ptr = __pa(p); 955 } 956 957 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) 958 { 959 #ifdef CONFIG_SMP 960 void *page; 961 962 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); 963 964 page = alloc_bootmem_pages(PAGE_SIZE); 965 if (!page) { 966 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); 967 prom_halt(); 968 } 969 970 tb->cpu_mondo_block_pa = __pa(page); 971 tb->cpu_list_pa = __pa(page + 64); 972 #endif 973 } 974 975 /* Allocate mondo and error queues for all possible cpus. */ 976 static void __init sun4v_init_mondo_queues(void) 977 { 978 int cpu; 979 980 for_each_possible_cpu(cpu) { 981 struct trap_per_cpu *tb = &trap_block[cpu]; 982 983 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); 984 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); 985 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); 986 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); 987 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); 988 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, 989 tb->nonresum_qmask); 990 } 991 } 992 993 static void __init init_send_mondo_info(void) 994 { 995 int cpu; 996 997 for_each_possible_cpu(cpu) { 998 struct trap_per_cpu *tb = &trap_block[cpu]; 999 1000 init_cpu_send_mondo_info(tb); 1001 } 1002 } 1003 1004 static struct irqaction timer_irq_action = { 1005 .name = "timer", 1006 }; 1007 1008 /* Only invoked on boot processor. */ 1009 void __init init_IRQ(void) 1010 { 1011 unsigned long size; 1012 1013 map_prom_timers(); 1014 kill_prom_timer(); 1015 1016 size = sizeof(struct ino_bucket) * NUM_IVECS; 1017 ivector_table = alloc_bootmem(size); 1018 if (!ivector_table) { 1019 prom_printf("Fatal error, cannot allocate ivector_table\n"); 1020 prom_halt(); 1021 } 1022 __flush_dcache_range((unsigned long) ivector_table, 1023 ((unsigned long) ivector_table) + size); 1024 1025 ivector_table_pa = __pa(ivector_table); 1026 1027 if (tlb_type == hypervisor) 1028 sun4v_init_mondo_queues(); 1029 1030 init_send_mondo_info(); 1031 1032 if (tlb_type == hypervisor) { 1033 /* Load up the boot cpu's entries. */ 1034 sun4v_register_mondo_queues(hard_smp_processor_id()); 1035 } 1036 1037 /* We need to clear any IRQ's pending in the soft interrupt 1038 * registers, a spurious one could be left around from the 1039 * PROM timer which we just disabled. 1040 */ 1041 clear_softint(get_softint()); 1042 1043 /* Now that ivector table is initialized, it is safe 1044 * to receive IRQ vector traps. We will normally take 1045 * one or two right now, in case some device PROM used 1046 * to boot us wants to speak to us. We just ignore them. 1047 */ 1048 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" 1049 "or %%g1, %0, %%g1\n\t" 1050 "wrpr %%g1, 0x0, %%pstate" 1051 : /* No outputs */ 1052 : "i" (PSTATE_IE) 1053 : "g1"); 1054 1055 irq_desc[0].action = &timer_irq_action; 1056 } 1057