1d670bd4fSSam Ravnborg /* 2fd49bf48SSam Ravnborg * Interrupt request handling routines. On the 3d670bd4fSSam Ravnborg * Sparc the IRQs are basically 'cast in stone' 4d670bd4fSSam Ravnborg * and you are supposed to probe the prom's device 5d670bd4fSSam Ravnborg * node trees to find out who's got which IRQ. 6d670bd4fSSam Ravnborg * 7d670bd4fSSam Ravnborg * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 8d670bd4fSSam Ravnborg * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx) 9d670bd4fSSam Ravnborg * Copyright (C) 1995,2002 Pete A. Zaitcev (zaitcev@yahoo.com) 10d670bd4fSSam Ravnborg * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk) 11d670bd4fSSam Ravnborg * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org) 12d670bd4fSSam Ravnborg */ 13d670bd4fSSam Ravnborg 14d670bd4fSSam Ravnborg #include <linux/kernel_stat.h> 15d670bd4fSSam Ravnborg #include <linux/seq_file.h> 16d670bd4fSSam Ravnborg 17a2a211cbSSam Ravnborg #include <asm/cacheflush.h> 186baa9b20SSam Ravnborg #include <asm/cpudata.h> 19d670bd4fSSam Ravnborg #include <asm/pcic.h> 200fd7ef1fSKonrad Eisele #include <asm/leon.h> 21d670bd4fSSam Ravnborg 2281265fd9SSam Ravnborg #include "kernel.h" 23d670bd4fSSam Ravnborg #include "irq.h" 24d670bd4fSSam Ravnborg 25d670bd4fSSam Ravnborg #ifdef CONFIG_SMP 26d670bd4fSSam Ravnborg #define SMP_NOP2 "nop; nop;\n\t" 27d670bd4fSSam Ravnborg #define SMP_NOP3 "nop; nop; nop;\n\t" 28d670bd4fSSam Ravnborg #else 29d670bd4fSSam Ravnborg #define SMP_NOP2 30d670bd4fSSam Ravnborg #define SMP_NOP3 31d670bd4fSSam Ravnborg #endif /* SMP */ 32fd49bf48SSam Ravnborg 33bbdc2661SSam Ravnborg /* platform specific irq setup */ 34bbdc2661SSam Ravnborg struct sparc_irq_config sparc_irq_config; 35bbdc2661SSam Ravnborg 36df9ee292SDavid Howells unsigned long arch_local_irq_save(void) 37d670bd4fSSam Ravnborg { 38d670bd4fSSam Ravnborg unsigned long retval; 39d670bd4fSSam Ravnborg unsigned long tmp; 40d670bd4fSSam Ravnborg 41d670bd4fSSam Ravnborg __asm__ __volatile__( 42d670bd4fSSam Ravnborg "rd %%psr, %0\n\t" 43d670bd4fSSam Ravnborg SMP_NOP3 /* Sun4m + Cypress + SMP bug */ 44d670bd4fSSam Ravnborg "or %0, %2, %1\n\t" 45d670bd4fSSam Ravnborg "wr %1, 0, %%psr\n\t" 46d670bd4fSSam Ravnborg "nop; nop; nop\n" 47d670bd4fSSam Ravnborg : "=&r" (retval), "=r" (tmp) 48d670bd4fSSam Ravnborg : "i" (PSR_PIL) 49d670bd4fSSam Ravnborg : "memory"); 50d670bd4fSSam Ravnborg 51d670bd4fSSam Ravnborg return retval; 52d670bd4fSSam Ravnborg } 53df9ee292SDavid Howells EXPORT_SYMBOL(arch_local_irq_save); 54d670bd4fSSam Ravnborg 55df9ee292SDavid Howells void arch_local_irq_enable(void) 56d670bd4fSSam Ravnborg { 57d670bd4fSSam Ravnborg unsigned long tmp; 58d670bd4fSSam Ravnborg 59d670bd4fSSam Ravnborg __asm__ __volatile__( 60d670bd4fSSam Ravnborg "rd %%psr, %0\n\t" 61d670bd4fSSam Ravnborg SMP_NOP3 /* Sun4m + Cypress + SMP bug */ 62d670bd4fSSam Ravnborg "andn %0, %1, %0\n\t" 63d670bd4fSSam Ravnborg "wr %0, 0, %%psr\n\t" 64d670bd4fSSam Ravnborg "nop; nop; nop\n" 65d670bd4fSSam Ravnborg : "=&r" (tmp) 66d670bd4fSSam Ravnborg : "i" (PSR_PIL) 67d670bd4fSSam Ravnborg : "memory"); 68d670bd4fSSam Ravnborg } 69df9ee292SDavid Howells EXPORT_SYMBOL(arch_local_irq_enable); 70d670bd4fSSam Ravnborg 71df9ee292SDavid Howells void arch_local_irq_restore(unsigned long old_psr) 72d670bd4fSSam Ravnborg { 73d670bd4fSSam Ravnborg unsigned long tmp; 74d670bd4fSSam Ravnborg 75d670bd4fSSam Ravnborg __asm__ __volatile__( 76d670bd4fSSam Ravnborg "rd %%psr, %0\n\t" 77d670bd4fSSam Ravnborg "and %2, %1, %2\n\t" 78d670bd4fSSam Ravnborg SMP_NOP2 /* Sun4m + Cypress + SMP bug */ 79d670bd4fSSam Ravnborg "andn %0, %1, %0\n\t" 80d670bd4fSSam Ravnborg "wr %0, %2, %%psr\n\t" 81d670bd4fSSam Ravnborg "nop; nop; nop\n" 82d670bd4fSSam Ravnborg : "=&r" (tmp) 83d670bd4fSSam Ravnborg : "i" (PSR_PIL), "r" (old_psr) 84d670bd4fSSam Ravnborg : "memory"); 85d670bd4fSSam Ravnborg } 86df9ee292SDavid Howells EXPORT_SYMBOL(arch_local_irq_restore); 87d670bd4fSSam Ravnborg 88d670bd4fSSam Ravnborg /* 89d670bd4fSSam Ravnborg * Dave Redman (djhr@tadpole.co.uk) 90d670bd4fSSam Ravnborg * 91d670bd4fSSam Ravnborg * IRQ numbers.. These are no longer restricted to 15.. 92d670bd4fSSam Ravnborg * 93d670bd4fSSam Ravnborg * this is done to enable SBUS cards and onboard IO to be masked 94d670bd4fSSam Ravnborg * correctly. using the interrupt level isn't good enough. 95d670bd4fSSam Ravnborg * 96d670bd4fSSam Ravnborg * For example: 97d670bd4fSSam Ravnborg * A device interrupting at sbus level6 and the Floppy both come in 98d670bd4fSSam Ravnborg * at IRQ11, but enabling and disabling them requires writing to 99d670bd4fSSam Ravnborg * different bits in the SLAVIO/SEC. 100d670bd4fSSam Ravnborg * 101d670bd4fSSam Ravnborg * As a result of these changes sun4m machines could now support 102d670bd4fSSam Ravnborg * directed CPU interrupts using the existing enable/disable irq code 103d670bd4fSSam Ravnborg * with tweaks. 104d670bd4fSSam Ravnborg * 1056baa9b20SSam Ravnborg * Sun4d complicates things even further. IRQ numbers are arbitrary 1066baa9b20SSam Ravnborg * 32-bit values in that case. Since this is similar to sparc64, 1076baa9b20SSam Ravnborg * we adopt a virtual IRQ numbering scheme as is done there. 1086baa9b20SSam Ravnborg * Virutal interrupt numbers are allocated by build_irq(). So NR_IRQS 1096baa9b20SSam Ravnborg * just becomes a limit of how many interrupt sources we can handle in 1106baa9b20SSam Ravnborg * a single system. Even fully loaded SS2000 machines top off at 1116baa9b20SSam Ravnborg * about 32 interrupt sources or so, therefore a NR_IRQS value of 64 1126baa9b20SSam Ravnborg * is more than enough. 1136baa9b20SSam Ravnborg * 1146baa9b20SSam Ravnborg * We keep a map of per-PIL enable interrupts. These get wired 1156baa9b20SSam Ravnborg * up via the irq_chip->startup() method which gets invoked by 1166baa9b20SSam Ravnborg * the generic IRQ layer during request_irq(). 117d670bd4fSSam Ravnborg */ 118d670bd4fSSam Ravnborg 119d670bd4fSSam Ravnborg 1206baa9b20SSam Ravnborg /* Table of allocated irqs. Unused entries has irq == 0 */ 1216baa9b20SSam Ravnborg static struct irq_bucket irq_table[NR_IRQS]; 1226baa9b20SSam Ravnborg /* Protect access to irq_table */ 1236baa9b20SSam Ravnborg static DEFINE_SPINLOCK(irq_table_lock); 124d670bd4fSSam Ravnborg 1256baa9b20SSam Ravnborg /* Map between the irq identifier used in hw to the irq_bucket. */ 1266baa9b20SSam Ravnborg struct irq_bucket *irq_map[SUN4D_MAX_IRQ]; 1276baa9b20SSam Ravnborg /* Protect access to irq_map */ 1286baa9b20SSam Ravnborg static DEFINE_SPINLOCK(irq_map_lock); 129d670bd4fSSam Ravnborg 1306baa9b20SSam Ravnborg /* Allocate a new irq from the irq_table */ 1316baa9b20SSam Ravnborg unsigned int irq_alloc(unsigned int real_irq, unsigned int pil) 132d670bd4fSSam Ravnborg { 133d670bd4fSSam Ravnborg unsigned long flags; 1346baa9b20SSam Ravnborg unsigned int i; 135d670bd4fSSam Ravnborg 1366baa9b20SSam Ravnborg spin_lock_irqsave(&irq_table_lock, flags); 1376baa9b20SSam Ravnborg for (i = 1; i < NR_IRQS; i++) { 1386baa9b20SSam Ravnborg if (irq_table[i].real_irq == real_irq && irq_table[i].pil == pil) 1396baa9b20SSam Ravnborg goto found; 1406baa9b20SSam Ravnborg } 141fd49bf48SSam Ravnborg 1426baa9b20SSam Ravnborg for (i = 1; i < NR_IRQS; i++) { 1436baa9b20SSam Ravnborg if (!irq_table[i].irq) 1446baa9b20SSam Ravnborg break; 1456baa9b20SSam Ravnborg } 1466baa9b20SSam Ravnborg 147d670bd4fSSam Ravnborg if (i < NR_IRQS) { 1486baa9b20SSam Ravnborg irq_table[i].real_irq = real_irq; 1496baa9b20SSam Ravnborg irq_table[i].irq = i; 1506baa9b20SSam Ravnborg irq_table[i].pil = pil; 1516baa9b20SSam Ravnborg } else { 1526baa9b20SSam Ravnborg printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); 1536baa9b20SSam Ravnborg i = 0; 154d670bd4fSSam Ravnborg } 1556baa9b20SSam Ravnborg found: 1566baa9b20SSam Ravnborg spin_unlock_irqrestore(&irq_table_lock, flags); 1576baa9b20SSam Ravnborg 1586baa9b20SSam Ravnborg return i; 159d670bd4fSSam Ravnborg } 1606baa9b20SSam Ravnborg 1616baa9b20SSam Ravnborg /* Based on a single pil handler_irq may need to call several 1626baa9b20SSam Ravnborg * interrupt handlers. Use irq_map as entry to irq_table, 1636baa9b20SSam Ravnborg * and let each entry in irq_table point to the next entry. 1646baa9b20SSam Ravnborg */ 1656baa9b20SSam Ravnborg void irq_link(unsigned int irq) 1666baa9b20SSam Ravnborg { 1676baa9b20SSam Ravnborg struct irq_bucket *p; 1686baa9b20SSam Ravnborg unsigned long flags; 1696baa9b20SSam Ravnborg unsigned int pil; 1706baa9b20SSam Ravnborg 1716baa9b20SSam Ravnborg BUG_ON(irq >= NR_IRQS); 1726baa9b20SSam Ravnborg 1736baa9b20SSam Ravnborg spin_lock_irqsave(&irq_map_lock, flags); 1746baa9b20SSam Ravnborg 1756baa9b20SSam Ravnborg p = &irq_table[irq]; 1766baa9b20SSam Ravnborg pil = p->pil; 1776baa9b20SSam Ravnborg BUG_ON(pil > SUN4D_MAX_IRQ); 1786baa9b20SSam Ravnborg p->next = irq_map[pil]; 1796baa9b20SSam Ravnborg irq_map[pil] = p; 1806baa9b20SSam Ravnborg 1816baa9b20SSam Ravnborg spin_unlock_irqrestore(&irq_map_lock, flags); 182d670bd4fSSam Ravnborg } 1836baa9b20SSam Ravnborg 1846baa9b20SSam Ravnborg void irq_unlink(unsigned int irq) 1856baa9b20SSam Ravnborg { 1866baa9b20SSam Ravnborg struct irq_bucket *p, **pnext; 1876baa9b20SSam Ravnborg unsigned long flags; 1886baa9b20SSam Ravnborg 1896baa9b20SSam Ravnborg BUG_ON(irq >= NR_IRQS); 1906baa9b20SSam Ravnborg 1916baa9b20SSam Ravnborg spin_lock_irqsave(&irq_map_lock, flags); 1926baa9b20SSam Ravnborg 1936baa9b20SSam Ravnborg p = &irq_table[irq]; 1946baa9b20SSam Ravnborg BUG_ON(p->pil > SUN4D_MAX_IRQ); 1956baa9b20SSam Ravnborg pnext = &irq_map[p->pil]; 1966baa9b20SSam Ravnborg while (*pnext != p) 1976baa9b20SSam Ravnborg pnext = &(*pnext)->next; 1986baa9b20SSam Ravnborg *pnext = p->next; 1996baa9b20SSam Ravnborg 2006baa9b20SSam Ravnborg spin_unlock_irqrestore(&irq_map_lock, flags); 2016baa9b20SSam Ravnborg } 2026baa9b20SSam Ravnborg 2036baa9b20SSam Ravnborg 2046baa9b20SSam Ravnborg /* /proc/interrupts printing */ 2056baa9b20SSam Ravnborg int arch_show_interrupts(struct seq_file *p, int prec) 2066baa9b20SSam Ravnborg { 2076baa9b20SSam Ravnborg int j; 2086baa9b20SSam Ravnborg 209d6d04819SDaniel Hellstrom #ifdef CONFIG_SMP 210d6d04819SDaniel Hellstrom seq_printf(p, "RES: "); 211d6d04819SDaniel Hellstrom for_each_online_cpu(j) 212d6d04819SDaniel Hellstrom seq_printf(p, "%10u ", cpu_data(j).irq_resched_count); 213d6d04819SDaniel Hellstrom seq_printf(p, " IPI rescheduling interrupts\n"); 214d6d04819SDaniel Hellstrom seq_printf(p, "CAL: "); 215d6d04819SDaniel Hellstrom for_each_online_cpu(j) 216d6d04819SDaniel Hellstrom seq_printf(p, "%10u ", cpu_data(j).irq_call_count); 217d6d04819SDaniel Hellstrom seq_printf(p, " IPI function call interrupts\n"); 218d6d04819SDaniel Hellstrom #endif 2196baa9b20SSam Ravnborg seq_printf(p, "NMI: "); 2206baa9b20SSam Ravnborg for_each_online_cpu(j) 2216baa9b20SSam Ravnborg seq_printf(p, "%10u ", cpu_data(j).counter); 2226baa9b20SSam Ravnborg seq_printf(p, " Non-maskable interrupts\n"); 223d670bd4fSSam Ravnborg return 0; 224d670bd4fSSam Ravnborg } 225d670bd4fSSam Ravnborg 2266baa9b20SSam Ravnborg void handler_irq(unsigned int pil, struct pt_regs *regs) 227d670bd4fSSam Ravnborg { 228d670bd4fSSam Ravnborg struct pt_regs *old_regs; 2296baa9b20SSam Ravnborg struct irq_bucket *p; 230d670bd4fSSam Ravnborg 2316baa9b20SSam Ravnborg BUG_ON(pil > 15); 232d670bd4fSSam Ravnborg old_regs = set_irq_regs(regs); 233d670bd4fSSam Ravnborg irq_enter(); 2346baa9b20SSam Ravnborg 2356baa9b20SSam Ravnborg p = irq_map[pil]; 2366baa9b20SSam Ravnborg while (p) { 2376baa9b20SSam Ravnborg struct irq_bucket *next = p->next; 2386baa9b20SSam Ravnborg 2396baa9b20SSam Ravnborg generic_handle_irq(p->irq); 2406baa9b20SSam Ravnborg p = next; 2416baa9b20SSam Ravnborg } 242d670bd4fSSam Ravnborg irq_exit(); 243d670bd4fSSam Ravnborg set_irq_regs(old_regs); 244d670bd4fSSam Ravnborg } 245d670bd4fSSam Ravnborg 246d670bd4fSSam Ravnborg #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE) 2476baa9b20SSam Ravnborg static unsigned int floppy_irq; 248d670bd4fSSam Ravnborg 2496baa9b20SSam Ravnborg int sparc_floppy_request_irq(unsigned int irq, irq_handler_t irq_handler) 250d670bd4fSSam Ravnborg { 251d670bd4fSSam Ravnborg unsigned int cpu_irq; 2526baa9b20SSam Ravnborg int err; 2536baa9b20SSam Ravnborg 25451672321SNamhyung Kim #if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON 255d670bd4fSSam Ravnborg struct tt_entry *trap_table; 256d670bd4fSSam Ravnborg #endif 257d670bd4fSSam Ravnborg 2586baa9b20SSam Ravnborg err = request_irq(irq, irq_handler, 0, "floppy", NULL); 2596baa9b20SSam Ravnborg if (err) 2606baa9b20SSam Ravnborg return -1; 261d670bd4fSSam Ravnborg 2626baa9b20SSam Ravnborg /* Save for later use in floppy interrupt handler */ 2636baa9b20SSam Ravnborg floppy_irq = irq; 264d670bd4fSSam Ravnborg 2656baa9b20SSam Ravnborg cpu_irq = (irq & (NR_IRQS - 1)); 266d670bd4fSSam Ravnborg 267d670bd4fSSam Ravnborg /* Dork with trap table if we get this far. */ 268d670bd4fSSam Ravnborg #define INSTANTIATE(table) \ 269d670bd4fSSam Ravnborg table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_one = SPARC_RD_PSR_L0; \ 270d670bd4fSSam Ravnborg table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two = \ 2716baa9b20SSam Ravnborg SPARC_BRANCH((unsigned long) floppy_hardint, \ 272d670bd4fSSam Ravnborg (unsigned long) &table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two);\ 273d670bd4fSSam Ravnborg table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_three = SPARC_RD_WIM_L3; \ 274d670bd4fSSam Ravnborg table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP; 275d670bd4fSSam Ravnborg 276d670bd4fSSam Ravnborg INSTANTIATE(sparc_ttable) 27751672321SNamhyung Kim #if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON 278fd49bf48SSam Ravnborg trap_table = &trapbase_cpu1; 279fd49bf48SSam Ravnborg INSTANTIATE(trap_table) 280fd49bf48SSam Ravnborg trap_table = &trapbase_cpu2; 281fd49bf48SSam Ravnborg INSTANTIATE(trap_table) 282fd49bf48SSam Ravnborg trap_table = &trapbase_cpu3; 283fd49bf48SSam Ravnborg INSTANTIATE(trap_table) 284d670bd4fSSam Ravnborg #endif 285d670bd4fSSam Ravnborg #undef INSTANTIATE 286d670bd4fSSam Ravnborg /* 287d670bd4fSSam Ravnborg * XXX Correct thing whould be to flush only I- and D-cache lines 288d670bd4fSSam Ravnborg * which contain the handler in question. But as of time of the 289d670bd4fSSam Ravnborg * writing we have no CPU-neutral interface to fine-grained flushes. 290d670bd4fSSam Ravnborg */ 291d670bd4fSSam Ravnborg flush_cache_all(); 2926baa9b20SSam Ravnborg return 0; 293d670bd4fSSam Ravnborg } 2946baa9b20SSam Ravnborg EXPORT_SYMBOL(sparc_floppy_request_irq); 295d670bd4fSSam Ravnborg 296fd49bf48SSam Ravnborg /* 297fd49bf48SSam Ravnborg * These variables are used to access state from the assembler 298d670bd4fSSam Ravnborg * interrupt handler, floppy_hardint, so we cannot put these in 299d670bd4fSSam Ravnborg * the floppy driver image because that would not work in the 300d670bd4fSSam Ravnborg * modular case. 301d670bd4fSSam Ravnborg */ 302d670bd4fSSam Ravnborg volatile unsigned char *fdc_status; 303d670bd4fSSam Ravnborg EXPORT_SYMBOL(fdc_status); 304d670bd4fSSam Ravnborg 305d670bd4fSSam Ravnborg char *pdma_vaddr; 306d670bd4fSSam Ravnborg EXPORT_SYMBOL(pdma_vaddr); 307d670bd4fSSam Ravnborg 308d670bd4fSSam Ravnborg unsigned long pdma_size; 309d670bd4fSSam Ravnborg EXPORT_SYMBOL(pdma_size); 310d670bd4fSSam Ravnborg 311d670bd4fSSam Ravnborg volatile int doing_pdma; 312d670bd4fSSam Ravnborg EXPORT_SYMBOL(doing_pdma); 313d670bd4fSSam Ravnborg 314d670bd4fSSam Ravnborg char *pdma_base; 315d670bd4fSSam Ravnborg EXPORT_SYMBOL(pdma_base); 316d670bd4fSSam Ravnborg 317d670bd4fSSam Ravnborg unsigned long pdma_areasize; 318d670bd4fSSam Ravnborg EXPORT_SYMBOL(pdma_areasize); 319d670bd4fSSam Ravnborg 3206baa9b20SSam Ravnborg /* Use the generic irq support to call floppy_interrupt 3216baa9b20SSam Ravnborg * which was setup using request_irq() in sparc_floppy_request_irq(). 3226baa9b20SSam Ravnborg * We only have one floppy interrupt so we do not need to check 3236baa9b20SSam Ravnborg * for additional handlers being wired up by irq_link() 3246baa9b20SSam Ravnborg */ 325d670bd4fSSam Ravnborg void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs) 326d670bd4fSSam Ravnborg { 327d670bd4fSSam Ravnborg struct pt_regs *old_regs; 328d670bd4fSSam Ravnborg 329d670bd4fSSam Ravnborg old_regs = set_irq_regs(regs); 330d670bd4fSSam Ravnborg irq_enter(); 3316baa9b20SSam Ravnborg generic_handle_irq(floppy_irq); 332d670bd4fSSam Ravnborg irq_exit(); 333d670bd4fSSam Ravnborg set_irq_regs(old_regs); 334d670bd4fSSam Ravnborg } 335d670bd4fSSam Ravnborg #endif 336d670bd4fSSam Ravnborg 337d670bd4fSSam Ravnborg /* djhr 338d670bd4fSSam Ravnborg * This could probably be made indirect too and assigned in the CPU 339d670bd4fSSam Ravnborg * bits of the code. That would be much nicer I think and would also 340d670bd4fSSam Ravnborg * fit in with the idea of being able to tune your kernel for your machine 341d670bd4fSSam Ravnborg * by removing unrequired machine and device support. 342d670bd4fSSam Ravnborg * 343d670bd4fSSam Ravnborg */ 344d670bd4fSSam Ravnborg 345d670bd4fSSam Ravnborg void __init init_IRQ(void) 346d670bd4fSSam Ravnborg { 347d670bd4fSSam Ravnborg switch (sparc_cpu_model) { 348d670bd4fSSam Ravnborg case sun4c: 349d670bd4fSSam Ravnborg case sun4: 350d670bd4fSSam Ravnborg sun4c_init_IRQ(); 351d670bd4fSSam Ravnborg break; 352d670bd4fSSam Ravnborg 353d670bd4fSSam Ravnborg case sun4m: 354d670bd4fSSam Ravnborg pcic_probe(); 35506010fb5SSam Ravnborg if (pcic_present()) 356d670bd4fSSam Ravnborg sun4m_pci_init_IRQ(); 35706010fb5SSam Ravnborg else 358d670bd4fSSam Ravnborg sun4m_init_IRQ(); 359d670bd4fSSam Ravnborg break; 360d670bd4fSSam Ravnborg 361d670bd4fSSam Ravnborg case sun4d: 362d670bd4fSSam Ravnborg sun4d_init_IRQ(); 363d670bd4fSSam Ravnborg break; 364d670bd4fSSam Ravnborg 3650fd7ef1fSKonrad Eisele case sparc_leon: 3660fd7ef1fSKonrad Eisele leon_init_IRQ(); 3670fd7ef1fSKonrad Eisele break; 3680fd7ef1fSKonrad Eisele 369d670bd4fSSam Ravnborg default: 370d670bd4fSSam Ravnborg prom_printf("Cannot initialize IRQs on this Sun machine..."); 371d670bd4fSSam Ravnborg break; 372d670bd4fSSam Ravnborg } 373d670bd4fSSam Ravnborg btfixup(); 374d670bd4fSSam Ravnborg } 375d670bd4fSSam Ravnborg 376