1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 2a88b5ba8SSam Ravnborg/* hvtramp.S: Hypervisor start-cpu trampoline code. 3a88b5ba8SSam Ravnborg * 4a88b5ba8SSam Ravnborg * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net> 5a88b5ba8SSam Ravnborg */ 6a88b5ba8SSam Ravnborg 7a88b5ba8SSam Ravnborg 8a88b5ba8SSam Ravnborg#include <asm/thread_info.h> 9a88b5ba8SSam Ravnborg#include <asm/hypervisor.h> 10a88b5ba8SSam Ravnborg#include <asm/scratchpad.h> 11a88b5ba8SSam Ravnborg#include <asm/spitfire.h> 12a88b5ba8SSam Ravnborg#include <asm/hvtramp.h> 13a88b5ba8SSam Ravnborg#include <asm/pstate.h> 14a88b5ba8SSam Ravnborg#include <asm/ptrace.h> 15a88b5ba8SSam Ravnborg#include <asm/head.h> 16a88b5ba8SSam Ravnborg#include <asm/asi.h> 17a88b5ba8SSam Ravnborg#include <asm/pil.h> 18a88b5ba8SSam Ravnborg 19a88b5ba8SSam Ravnborg .align 8 20a88b5ba8SSam Ravnborg .globl hv_cpu_startup, hv_cpu_startup_end 21a88b5ba8SSam Ravnborg 22a88b5ba8SSam Ravnborg /* This code executes directly out of the hypervisor 23a88b5ba8SSam Ravnborg * with physical addressing (va==pa). %o0 contains 24a88b5ba8SSam Ravnborg * our client argument which for Linux points to 25a88b5ba8SSam Ravnborg * a descriptor data structure which defines the 26a88b5ba8SSam Ravnborg * MMU entries we need to load up. 27a88b5ba8SSam Ravnborg * 28a88b5ba8SSam Ravnborg * After we set things up we enable the MMU and call 29a88b5ba8SSam Ravnborg * into the kernel. 30a88b5ba8SSam Ravnborg * 31a88b5ba8SSam Ravnborg * First setup basic privileged cpu state. 32a88b5ba8SSam Ravnborg */ 33a88b5ba8SSam Ravnborghv_cpu_startup: 34a88b5ba8SSam Ravnborg SET_GL(0) 35a88b5ba8SSam Ravnborg wrpr %g0, PIL_NORMAL_MAX, %pil 36a88b5ba8SSam Ravnborg wrpr %g0, 0, %canrestore 37a88b5ba8SSam Ravnborg wrpr %g0, 0, %otherwin 38a88b5ba8SSam Ravnborg wrpr %g0, 6, %cansave 39a88b5ba8SSam Ravnborg wrpr %g0, 6, %cleanwin 40a88b5ba8SSam Ravnborg wrpr %g0, 0, %cwp 41a88b5ba8SSam Ravnborg wrpr %g0, 0, %wstate 42a88b5ba8SSam Ravnborg wrpr %g0, 0, %tl 43a88b5ba8SSam Ravnborg 44a88b5ba8SSam Ravnborg sethi %hi(sparc64_ttable_tl0), %g1 45a88b5ba8SSam Ravnborg wrpr %g1, %tba 46a88b5ba8SSam Ravnborg 47a88b5ba8SSam Ravnborg mov %o0, %l0 48a88b5ba8SSam Ravnborg 49a88b5ba8SSam Ravnborg lduw [%l0 + HVTRAMP_DESCR_CPU], %g1 50a88b5ba8SSam Ravnborg mov SCRATCHPAD_CPUID, %g2 51a88b5ba8SSam Ravnborg stxa %g1, [%g2] ASI_SCRATCHPAD 52a88b5ba8SSam Ravnborg 53a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2 54a88b5ba8SSam Ravnborg stxa %g2, [%g0] ASI_SCRATCHPAD 55a88b5ba8SSam Ravnborg 56a88b5ba8SSam Ravnborg mov 0, %l1 57a88b5ba8SSam Ravnborg lduw [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2 58a88b5ba8SSam Ravnborg add %l0, HVTRAMP_DESCR_MAPS, %l3 59a88b5ba8SSam Ravnborg 60a88b5ba8SSam Ravnborg1: ldx [%l3 + HVTRAMP_MAPPING_VADDR], %o0 61a88b5ba8SSam Ravnborg clr %o1 62a88b5ba8SSam Ravnborg ldx [%l3 + HVTRAMP_MAPPING_TTE], %o2 63a88b5ba8SSam Ravnborg mov HV_MMU_IMMU | HV_MMU_DMMU, %o3 64a88b5ba8SSam Ravnborg mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 65a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 66a88b5ba8SSam Ravnborg 67a88b5ba8SSam Ravnborg brnz,pn %o0, 80f 68a88b5ba8SSam Ravnborg nop 69a88b5ba8SSam Ravnborg 70a88b5ba8SSam Ravnborg add %l1, 1, %l1 71a88b5ba8SSam Ravnborg cmp %l1, %l2 72a88b5ba8SSam Ravnborg blt,a,pt %xcc, 1b 73a88b5ba8SSam Ravnborg add %l3, HVTRAMP_MAPPING_SIZE, %l3 74a88b5ba8SSam Ravnborg 75a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0 76a88b5ba8SSam Ravnborg mov HV_FAST_MMU_FAULT_AREA_CONF, %o5 77a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 78a88b5ba8SSam Ravnborg 79a88b5ba8SSam Ravnborg brnz,pn %o0, 80f 80a88b5ba8SSam Ravnborg nop 81a88b5ba8SSam Ravnborg 82a88b5ba8SSam Ravnborg wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate 83a88b5ba8SSam Ravnborg 84a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6 85a88b5ba8SSam Ravnborg 86a88b5ba8SSam Ravnborg mov 1, %o0 87a88b5ba8SSam Ravnborg set 1f, %o1 88a88b5ba8SSam Ravnborg mov HV_FAST_MMU_ENABLE, %o5 89a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 90a88b5ba8SSam Ravnborg 91a88b5ba8SSam Ravnborg ba,pt %xcc, 80f 92a88b5ba8SSam Ravnborg nop 93a88b5ba8SSam Ravnborg 94a88b5ba8SSam Ravnborg1: 95a88b5ba8SSam Ravnborg wr %g0, 0, %fprs 96a88b5ba8SSam Ravnborg wr %g0, ASI_P, %asi 97a88b5ba8SSam Ravnborg 98a88b5ba8SSam Ravnborg mov PRIMARY_CONTEXT, %g7 99a88b5ba8SSam Ravnborg stxa %g0, [%g7] ASI_MMU 100a88b5ba8SSam Ravnborg membar #Sync 101a88b5ba8SSam Ravnborg 102a88b5ba8SSam Ravnborg mov SECONDARY_CONTEXT, %g7 103a88b5ba8SSam Ravnborg stxa %g0, [%g7] ASI_MMU 104a88b5ba8SSam Ravnborg membar #Sync 105a88b5ba8SSam Ravnborg 106a88b5ba8SSam Ravnborg mov %l6, %g6 107a88b5ba8SSam Ravnborg ldx [%g6 + TI_TASK], %g4 108a88b5ba8SSam Ravnborg 109a88b5ba8SSam Ravnborg mov 1, %g5 110a88b5ba8SSam Ravnborg sllx %g5, THREAD_SHIFT, %g5 111a88b5ba8SSam Ravnborg sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 112a88b5ba8SSam Ravnborg add %g6, %g5, %sp 113a88b5ba8SSam Ravnborg 114a88b5ba8SSam Ravnborg call init_irqwork_curcpu 115a88b5ba8SSam Ravnborg nop 116a88b5ba8SSam Ravnborg call hard_smp_processor_id 117a88b5ba8SSam Ravnborg nop 118a88b5ba8SSam Ravnborg 119a88b5ba8SSam Ravnborg call sun4v_register_mondo_queues 120a88b5ba8SSam Ravnborg nop 121a88b5ba8SSam Ravnborg 122a88b5ba8SSam Ravnborg call init_cur_cpu_trap 123a88b5ba8SSam Ravnborg mov %g6, %o0 124a88b5ba8SSam Ravnborg 125a88b5ba8SSam Ravnborg wrpr %g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate 126a88b5ba8SSam Ravnborg 127a88b5ba8SSam Ravnborg call smp_callin 128a88b5ba8SSam Ravnborg nop 12987fa05aeSSam Ravnborg 130a88b5ba8SSam Ravnborg call cpu_panic 131a88b5ba8SSam Ravnborg nop 132a88b5ba8SSam Ravnborg 133a88b5ba8SSam Ravnborg80: ba,pt %xcc, 80b 134a88b5ba8SSam Ravnborg nop 135a88b5ba8SSam Ravnborg 136a88b5ba8SSam Ravnborg .align 8 137a88b5ba8SSam Ravnborghv_cpu_startup_end: 138