1a88b5ba8SSam Ravnborg/* hvtramp.S: Hypervisor start-cpu trampoline code. 2a88b5ba8SSam Ravnborg * 3a88b5ba8SSam Ravnborg * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net> 4a88b5ba8SSam Ravnborg */ 5a88b5ba8SSam Ravnborg 6a88b5ba8SSam Ravnborg#include <linux/init.h> 7a88b5ba8SSam Ravnborg 8a88b5ba8SSam Ravnborg#include <asm/thread_info.h> 9a88b5ba8SSam Ravnborg#include <asm/hypervisor.h> 10a88b5ba8SSam Ravnborg#include <asm/scratchpad.h> 11a88b5ba8SSam Ravnborg#include <asm/spitfire.h> 12a88b5ba8SSam Ravnborg#include <asm/hvtramp.h> 13a88b5ba8SSam Ravnborg#include <asm/pstate.h> 14a88b5ba8SSam Ravnborg#include <asm/ptrace.h> 15a88b5ba8SSam Ravnborg#include <asm/head.h> 16a88b5ba8SSam Ravnborg#include <asm/asi.h> 17a88b5ba8SSam Ravnborg#include <asm/pil.h> 18a88b5ba8SSam Ravnborg 19a88b5ba8SSam Ravnborg __CPUINIT 20a88b5ba8SSam Ravnborg .align 8 21a88b5ba8SSam Ravnborg .globl hv_cpu_startup, hv_cpu_startup_end 22a88b5ba8SSam Ravnborg 23a88b5ba8SSam Ravnborg /* This code executes directly out of the hypervisor 24a88b5ba8SSam Ravnborg * with physical addressing (va==pa). %o0 contains 25a88b5ba8SSam Ravnborg * our client argument which for Linux points to 26a88b5ba8SSam Ravnborg * a descriptor data structure which defines the 27a88b5ba8SSam Ravnborg * MMU entries we need to load up. 28a88b5ba8SSam Ravnborg * 29a88b5ba8SSam Ravnborg * After we set things up we enable the MMU and call 30a88b5ba8SSam Ravnborg * into the kernel. 31a88b5ba8SSam Ravnborg * 32a88b5ba8SSam Ravnborg * First setup basic privileged cpu state. 33a88b5ba8SSam Ravnborg */ 34a88b5ba8SSam Ravnborghv_cpu_startup: 35a88b5ba8SSam Ravnborg SET_GL(0) 36a88b5ba8SSam Ravnborg wrpr %g0, PIL_NORMAL_MAX, %pil 37a88b5ba8SSam Ravnborg wrpr %g0, 0, %canrestore 38a88b5ba8SSam Ravnborg wrpr %g0, 0, %otherwin 39a88b5ba8SSam Ravnborg wrpr %g0, 6, %cansave 40a88b5ba8SSam Ravnborg wrpr %g0, 6, %cleanwin 41a88b5ba8SSam Ravnborg wrpr %g0, 0, %cwp 42a88b5ba8SSam Ravnborg wrpr %g0, 0, %wstate 43a88b5ba8SSam Ravnborg wrpr %g0, 0, %tl 44a88b5ba8SSam Ravnborg 45a88b5ba8SSam Ravnborg sethi %hi(sparc64_ttable_tl0), %g1 46a88b5ba8SSam Ravnborg wrpr %g1, %tba 47a88b5ba8SSam Ravnborg 48a88b5ba8SSam Ravnborg mov %o0, %l0 49a88b5ba8SSam Ravnborg 50a88b5ba8SSam Ravnborg lduw [%l0 + HVTRAMP_DESCR_CPU], %g1 51a88b5ba8SSam Ravnborg mov SCRATCHPAD_CPUID, %g2 52a88b5ba8SSam Ravnborg stxa %g1, [%g2] ASI_SCRATCHPAD 53a88b5ba8SSam Ravnborg 54a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2 55a88b5ba8SSam Ravnborg stxa %g2, [%g0] ASI_SCRATCHPAD 56a88b5ba8SSam Ravnborg 57a88b5ba8SSam Ravnborg mov 0, %l1 58a88b5ba8SSam Ravnborg lduw [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2 59a88b5ba8SSam Ravnborg add %l0, HVTRAMP_DESCR_MAPS, %l3 60a88b5ba8SSam Ravnborg 61a88b5ba8SSam Ravnborg1: ldx [%l3 + HVTRAMP_MAPPING_VADDR], %o0 62a88b5ba8SSam Ravnborg clr %o1 63a88b5ba8SSam Ravnborg ldx [%l3 + HVTRAMP_MAPPING_TTE], %o2 64a88b5ba8SSam Ravnborg mov HV_MMU_IMMU | HV_MMU_DMMU, %o3 65a88b5ba8SSam Ravnborg mov HV_FAST_MMU_MAP_PERM_ADDR, %o5 66a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 67a88b5ba8SSam Ravnborg 68a88b5ba8SSam Ravnborg brnz,pn %o0, 80f 69a88b5ba8SSam Ravnborg nop 70a88b5ba8SSam Ravnborg 71a88b5ba8SSam Ravnborg add %l1, 1, %l1 72a88b5ba8SSam Ravnborg cmp %l1, %l2 73a88b5ba8SSam Ravnborg blt,a,pt %xcc, 1b 74a88b5ba8SSam Ravnborg add %l3, HVTRAMP_MAPPING_SIZE, %l3 75a88b5ba8SSam Ravnborg 76a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0 77a88b5ba8SSam Ravnborg mov HV_FAST_MMU_FAULT_AREA_CONF, %o5 78a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 79a88b5ba8SSam Ravnborg 80a88b5ba8SSam Ravnborg brnz,pn %o0, 80f 81a88b5ba8SSam Ravnborg nop 82a88b5ba8SSam Ravnborg 83a88b5ba8SSam Ravnborg wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate 84a88b5ba8SSam Ravnborg 85a88b5ba8SSam Ravnborg ldx [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6 86a88b5ba8SSam Ravnborg 87a88b5ba8SSam Ravnborg mov 1, %o0 88a88b5ba8SSam Ravnborg set 1f, %o1 89a88b5ba8SSam Ravnborg mov HV_FAST_MMU_ENABLE, %o5 90a88b5ba8SSam Ravnborg ta HV_FAST_TRAP 91a88b5ba8SSam Ravnborg 92a88b5ba8SSam Ravnborg ba,pt %xcc, 80f 93a88b5ba8SSam Ravnborg nop 94a88b5ba8SSam Ravnborg 95a88b5ba8SSam Ravnborg1: 96a88b5ba8SSam Ravnborg wr %g0, 0, %fprs 97a88b5ba8SSam Ravnborg wr %g0, ASI_P, %asi 98a88b5ba8SSam Ravnborg 99a88b5ba8SSam Ravnborg mov PRIMARY_CONTEXT, %g7 100a88b5ba8SSam Ravnborg stxa %g0, [%g7] ASI_MMU 101a88b5ba8SSam Ravnborg membar #Sync 102a88b5ba8SSam Ravnborg 103a88b5ba8SSam Ravnborg mov SECONDARY_CONTEXT, %g7 104a88b5ba8SSam Ravnborg stxa %g0, [%g7] ASI_MMU 105a88b5ba8SSam Ravnborg membar #Sync 106a88b5ba8SSam Ravnborg 107a88b5ba8SSam Ravnborg mov %l6, %g6 108a88b5ba8SSam Ravnborg ldx [%g6 + TI_TASK], %g4 109a88b5ba8SSam Ravnborg 110a88b5ba8SSam Ravnborg mov 1, %g5 111a88b5ba8SSam Ravnborg sllx %g5, THREAD_SHIFT, %g5 112a88b5ba8SSam Ravnborg sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 113a88b5ba8SSam Ravnborg add %g6, %g5, %sp 114a88b5ba8SSam Ravnborg mov 0, %fp 115a88b5ba8SSam Ravnborg 116a88b5ba8SSam Ravnborg call init_irqwork_curcpu 117a88b5ba8SSam Ravnborg nop 118a88b5ba8SSam Ravnborg call hard_smp_processor_id 119a88b5ba8SSam Ravnborg nop 120a88b5ba8SSam Ravnborg 121a88b5ba8SSam Ravnborg call sun4v_register_mondo_queues 122a88b5ba8SSam Ravnborg nop 123a88b5ba8SSam Ravnborg 124a88b5ba8SSam Ravnborg call init_cur_cpu_trap 125a88b5ba8SSam Ravnborg mov %g6, %o0 126a88b5ba8SSam Ravnborg 127a88b5ba8SSam Ravnborg wrpr %g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate 128a88b5ba8SSam Ravnborg 129a88b5ba8SSam Ravnborg call smp_callin 130a88b5ba8SSam Ravnborg nop 131a88b5ba8SSam Ravnborg call cpu_idle 132a88b5ba8SSam Ravnborg mov 0, %o0 133a88b5ba8SSam Ravnborg call cpu_panic 134a88b5ba8SSam Ravnborg nop 135a88b5ba8SSam Ravnborg 136a88b5ba8SSam Ravnborg80: ba,pt %xcc, 80b 137a88b5ba8SSam Ravnborg nop 138a88b5ba8SSam Ravnborg 139a88b5ba8SSam Ravnborg .align 8 140a88b5ba8SSam Ravnborghv_cpu_startup_end: 141