xref: /openbmc/linux/arch/sparc/kernel/head_32.S (revision 4da722ca)
1/*
2 * head.S: The initial boot code for the Sparc port of Linux.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,1999 Pete Zaitcev   (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1997 Jakub Jelinek   (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
9 *
10 * CompactPCI platform by Eric Brower, 1999.
11 */
12
13#include <linux/version.h>
14#include <linux/init.h>
15
16#include <asm/head.h>
17#include <asm/asi.h>
18#include <asm/contregs.h>
19#include <asm/ptrace.h>
20#include <asm/psr.h>
21#include <asm/page.h>
22#include <asm/kdebug.h>
23#include <asm/winmacro.h>
24#include <asm/thread_info.h>	/* TI_UWINMASK */
25#include <asm/errno.h>
26#include <asm/pgtsrmmu.h>	/* SRMMU_PGDIR_SHIFT */
27#include <asm/export.h>
28
29	.data
30/* The following are used with the prom_vector node-ops to figure out
31 * the cpu-type
32 */
33	.align 4
34	.globl cputypval
35cputypval:
36	.asciz "sun4m"
37	.ascii "     "
38
39/* Tested on SS-5, SS-10 */
40	.align 4
41cputypvar:
42	.asciz "compatible"
43
44	.align 4
45
46notsup:
47	.asciz	"Sparc-Linux sun4/sun4c or MMU-less not supported\n\n"
48	.align 4
49
50sun4e_notsup:
51        .asciz  "Sparc-Linux sun4e support does not exist\n\n"
52	.align 4
53
54/* The trap-table - located in the __HEAD section */
55#include "ttable_32.S"
56
57	.align PAGE_SIZE
58
59/* This was the only reasonable way I could think of to properly align
60 * these page-table data structures.
61 */
62	.globl empty_zero_page
63empty_zero_page:	.skip PAGE_SIZE
64EXPORT_SYMBOL(empty_zero_page)
65
66	.global root_flags
67	.global ram_flags
68	.global root_dev
69	.global sparc_ramdisk_image
70	.global sparc_ramdisk_size
71
72/* This stuff has to be in sync with SILO and other potential boot loaders
73 * Fields should be kept upward compatible and whenever any change is made,
74 * HdrS version should be incremented.
75 */
76	.ascii	"HdrS"
77	.word	LINUX_VERSION_CODE
78	.half	0x0203		/* HdrS version */
79root_flags:
80	.half	1
81root_dev:
82	.half	0
83ram_flags:
84	.half	0
85sparc_ramdisk_image:
86	.word	0
87sparc_ramdisk_size:
88	.word	0
89	.word	reboot_command
90	.word	0, 0, 0
91	.word	_end
92
93/* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in
94 * %g7 and at prom_vector_p. And also quickly check whether we are on
95 * a v0, v2, or v3 prom.
96 */
97gokernel:
98		/* Ok, it's nice to know, as early as possible, if we
99		 * are already mapped where we expect to be in virtual
100		 * memory.  The Solaris /boot elf format bootloader
101		 * will peek into our elf header and load us where
102		 * we want to be, otherwise we have to re-map.
103		 *
104		 * Some boot loaders don't place the jmp'rs address
105		 * in %o7, so we do a pc-relative call to a local
106		 * label, then see what %o7 has.
107		 */
108
109		mov	%o7, %g4		! Save %o7
110
111		/* Jump to it, and pray... */
112current_pc:
113		call	1f
114		 nop
115
1161:
117		mov	%o7, %g3
118
119		tst	%o0
120		be	no_sun4u_here
121		 mov	%g4, %o7		/* Previous %o7. */
122
123		mov	%o0, %l0		! stash away romvec
124		mov	%o0, %g7		! put it here too
125		mov	%o1, %l1		! stash away debug_vec too
126
127		/* Ok, let's check out our run time program counter. */
128		set	current_pc, %g5
129		cmp	%g3, %g5
130		be	already_mapped
131		 nop
132
133		/* %l6 will hold the offset we have to subtract
134		 * from absolute symbols in order to access areas
135		 * in our own image.  If already mapped this is
136		 * just plain zero, else it is KERNBASE.
137		 */
138		set	KERNBASE, %l6
139		b	copy_prom_lvl14
140		 nop
141
142already_mapped:
143		mov	0, %l6
144
145		/* Copy over the Prom's level 14 clock handler. */
146copy_prom_lvl14:
147#if 1
148		/* DJHR
149		 * preserve our linked/calculated instructions
150		 */
151		set	lvl14_save, %g1
152		set	t_irq14, %g3
153		sub	%g1, %l6, %g1		! translate to physical
154		sub	%g3, %l6, %g3		! translate to physical
155		ldd	[%g3], %g4
156		std	%g4, [%g1]
157		ldd	[%g3+8], %g4
158		std	%g4, [%g1+8]
159#endif
160		rd	%tbr, %g1
161		andn	%g1, 0xfff, %g1		! proms trap table base
162		or	%g0, (0x1e<<4), %g2	! offset to lvl14 intr
163		or	%g1, %g2, %g2
164		set	t_irq14, %g3
165		sub	%g3, %l6, %g3
166		ldd	[%g2], %g4
167		std	%g4, [%g3]
168		ldd	[%g2 + 0x8], %g4
169		std	%g4, [%g3 + 0x8]	! Copy proms handler
170
171/* DON'T TOUCH %l0 thru %l5 in these remapping routines,
172 * we need their values afterwards!
173 */
174
175		/* Now check whether we are already mapped, if we
176		 * are we can skip all this garbage coming up.
177		 */
178copy_prom_done:
179		cmp	%l6, 0
180		be	go_to_highmem		! this will be a nop then
181		 nop
182
183		/* Validate that we are in fact running on an
184		 * SRMMU based cpu.
185		 */
186		set	0x4000, %g6
187		cmp	%g7, %g6
188		bne	not_a_sun4
189		 nop
190
191halt_notsup:
192		ld	[%g7 + 0x68], %o1
193		set	notsup, %o0
194		sub	%o0, %l6, %o0
195		call	%o1
196		 nop
197		ba	halt_me
198		 nop
199
200not_a_sun4:
201		/* It looks like this is a machine we support.
202		 * Now find out what MMU we are dealing with
203		 * LEON - identified by the psr.impl field
204		 * Viking - identified by the psr.impl field
205		 * In all other cases a sun4m srmmu.
206		 * We check that the MMU is enabled in all cases.
207		 */
208
209		/* Check if this is a LEON CPU */
210		rd	%psr, %g3
211		srl	%g3, PSR_IMPL_SHIFT, %g3
212		and	%g3, PSR_IMPL_SHIFTED_MASK, %g3
213		cmp	%g3, PSR_IMPL_LEON
214		be	leon_remap		/* It is a LEON - jump */
215		 nop
216
217		/* Sanity-check, is MMU enabled */
218		lda	[%g0] ASI_M_MMUREGS, %g1
219		andcc	%g1, 1, %g0
220		be	halt_notsup
221		 nop
222
223		/* Check for a viking (TI) module. */
224		cmp	%g3, PSR_IMPL_TI
225		bne	srmmu_not_viking
226		 nop
227
228		/* Figure out what kind of viking we are on.
229		 * We need to know if we have to play with the
230		 * AC bit and disable traps or not.
231		 */
232
233		/* I've only seen MicroSparc's on SparcClassics with this
234		 * bit set.
235		 */
236		set	0x800, %g2
237		lda	[%g0] ASI_M_MMUREGS, %g3	! peek in the control reg
238		and	%g2, %g3, %g3
239		subcc	%g3, 0x0, %g0
240		bnz	srmmu_not_viking			! is in mbus mode
241		 nop
242
243		rd	%psr, %g3			! DO NOT TOUCH %g3
244		andn	%g3, PSR_ET, %g2
245		wr	%g2, 0x0, %psr
246		WRITE_PAUSE
247
248		/* Get context table pointer, then convert to
249		 * a physical address, which is 36 bits.
250		 */
251		set	AC_M_CTPR, %g4
252		lda	[%g4] ASI_M_MMUREGS, %g4
253		sll	%g4, 0x4, %g4			! We use this below
254							! DO NOT TOUCH %g4
255
256		/* Set the AC bit in the Viking's MMU control reg. */
257		lda	[%g0] ASI_M_MMUREGS, %g5	! DO NOT TOUCH %g5
258		set	0x8000, %g6			! AC bit mask
259		or	%g5, %g6, %g6			! Or it in...
260		sta	%g6, [%g0] ASI_M_MMUREGS	! Close your eyes...
261
262		/* Grrr, why does it seem like every other load/store
263		 * on the sun4m is in some ASI space...
264		 * Fine with me, let's get the pointer to the level 1
265		 * page table directory and fetch its entry.
266		 */
267		lda	[%g4] ASI_M_BYPASS, %o1		! This is a level 1 ptr
268		srl	%o1, 0x4, %o1			! Clear low 4 bits
269		sll	%o1, 0x8, %o1			! Make physical
270
271		/* Ok, pull in the PTD. */
272		lda	[%o1] ASI_M_BYPASS, %o2		! This is the 0x0 16MB pgd
273
274		/* Calculate to KERNBASE entry. */
275		add	%o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3
276
277		/* Poke the entry into the calculated address. */
278		sta	%o2, [%o3] ASI_M_BYPASS
279
280		/* I don't get it Sun, if you engineered all these
281		 * boot loaders and the PROM (thank you for the debugging
282		 * features btw) why did you not have them load kernel
283		 * images up in high address space, since this is necessary
284		 * for ABI compliance anyways?  Does this low-mapping provide
285		 * enhanced interoperability?
286		 *
287		 * "The PROM is the computer."
288		 */
289
290		/* Ok, restore the MMU control register we saved in %g5 */
291		sta	%g5, [%g0] ASI_M_MMUREGS	! POW... ouch
292
293		/* Turn traps back on.  We saved it in %g3 earlier. */
294		wr	%g3, 0x0, %psr			! tick tock, tick tock
295
296		/* Now we burn precious CPU cycles due to bad engineering. */
297		WRITE_PAUSE
298
299		/* Wow, all that just to move a 32-bit value from one
300		 * place to another...  Jump to high memory.
301		 */
302		b	go_to_highmem
303		 nop
304
305srmmu_not_viking:
306		/* This works on viking's in Mbus mode and all
307		 * other MBUS modules.  It is virtually the same as
308		 * the above madness sans turning traps off and flipping
309		 * the AC bit.
310		 */
311		set	AC_M_CTPR, %g1
312		lda	[%g1] ASI_M_MMUREGS, %g1	! get ctx table ptr
313		sll	%g1, 0x4, %g1			! make physical addr
314		lda	[%g1] ASI_M_BYPASS, %g1		! ptr to level 1 pg_table
315		srl	%g1, 0x4, %g1
316		sll	%g1, 0x8, %g1			! make phys addr for l1 tbl
317
318		lda	[%g1] ASI_M_BYPASS, %g2		! get level1 entry for 0x0
319		add	%g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
320		sta	%g2, [%g3] ASI_M_BYPASS		! place at KERNBASE entry
321		b	go_to_highmem
322		 nop					! wheee....
323
324
325leon_remap:
326		/* Sanity-check, is MMU enabled */
327		lda	[%g0] ASI_LEON_MMUREGS, %g1
328		andcc	%g1, 1, %g0
329		be	halt_notsup
330		 nop
331
332		/* Same code as in the srmmu_not_viking case,
333		 * with the LEON ASI for mmuregs
334		 */
335		set	AC_M_CTPR, %g1
336		lda	[%g1] ASI_LEON_MMUREGS, %g1	! get ctx table ptr
337		sll	%g1, 0x4, %g1			! make physical addr
338		lda	[%g1] ASI_M_BYPASS, %g1		! ptr to level 1 pg_table
339		srl	%g1, 0x4, %g1
340		sll	%g1, 0x8, %g1			! make phys addr for l1 tbl
341
342		lda	[%g1] ASI_M_BYPASS, %g2		! get level1 entry for 0x0
343		add	%g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
344		sta	%g2, [%g3] ASI_M_BYPASS		! place at KERNBASE entry
345		b	go_to_highmem
346		 nop					! wheee....
347
348/* Now do a non-relative jump so that PC is in high-memory */
349go_to_highmem:
350		set	execute_in_high_mem, %g1
351		jmpl	%g1, %g0
352		 nop
353
354/* The code above should be at beginning and we have to take care about
355 * short jumps, as branching to .init.text section from .text is usually
356 * impossible */
357		__INIT
358/* Acquire boot time privileged register values, this will help debugging.
359 * I figure out and store nwindows and nwindowsm1 later on.
360 */
361execute_in_high_mem:
362		mov	%l0, %o0		! put back romvec
363		mov	%l1, %o1		! and debug_vec
364
365		sethi	%hi(prom_vector_p), %g1
366		st	%o0, [%g1 + %lo(prom_vector_p)]
367
368		sethi	%hi(linux_dbvec), %g1
369		st	%o1, [%g1 + %lo(linux_dbvec)]
370
371		/* Get the machine type via the romvec
372		 * getprops node operation
373		 */
374		add	%g7, 0x1c, %l1
375		ld	[%l1], %l0
376		ld	[%l0], %l0
377		call	%l0
378		 or	%g0, %g0, %o0		! next_node(0) = first_node
379		or	%o0, %g0, %g6
380
381		sethi	%hi(cputypvar), %o1	! First node has cpu-arch
382		or	%o1, %lo(cputypvar), %o1
383		sethi	%hi(cputypval), %o2	! information, the string
384		or	%o2, %lo(cputypval), %o2
385		ld	[%l1], %l0		! 'compatible' tells
386		ld	[%l0 + 0xc], %l0	! that we want 'sun4x' where
387		call	%l0			! x is one of 'm', 'd' or 'e'.
388		 nop				! %o2 holds pointer
389						! to a buf where above string
390						! will get stored by the prom.
391
392
393		/* Check value of "compatible" property.
394		 * "value" => "model"
395		 * leon => sparc_leon
396		 * sun4m => sun4m
397		 * sun4s => sun4m
398		 * sun4d => sun4d
399		 * sun4e => "no_sun4e_here"
400		 * '*'   => "no_sun4u_here"
401		 * Check single letters only
402		 */
403
404		set	cputypval, %o2
405		/* If cputypval[0] == 'l' (lower case letter L) this is leon */
406		ldub	[%o2], %l1
407		cmp	%l1, 'l'
408		be	leon_init
409		 nop
410
411		/* Check cputypval[4] to find the sun model */
412		ldub	[%o2 + 0x4], %l1
413
414		cmp	%l1, 'm'
415		be	sun4m_init
416		 cmp	%l1, 's'
417		be	sun4m_init
418		 cmp	%l1, 'd'
419		be	sun4d_init
420		 cmp	%l1, 'e'
421		be	no_sun4e_here		! Could be a sun4e.
422		 nop
423		b	no_sun4u_here		! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
424		 nop
425
426leon_init:
427		/* LEON CPU - set boot_cpu_id */
428		sethi	%hi(boot_cpu_id), %g2	! boot-cpu index
429
430#ifdef CONFIG_SMP
431		ldub	[%g2 + %lo(boot_cpu_id)], %g1
432		cmp	%g1, 0xff		! unset means first CPU
433		bne	leon_smp_cpu_startup	! continue only with master
434		 nop
435#endif
436		/* Get CPU-ID from most significant 4-bit of ASR17 */
437		rd     %asr17, %g1
438		srl    %g1, 28, %g1
439
440		/* Update boot_cpu_id only on boot cpu */
441		stub	%g1, [%g2 + %lo(boot_cpu_id)]
442
443		ba continue_boot
444		 nop
445
446/* CPUID in bootbus can be found at PA 0xff0140000 */
447#define SUN4D_BOOTBUS_CPUID     0xf0140000
448
449sun4d_init:
450	/* Need to patch call to handler_irq */
451	set	patch_handler_irq, %g4
452	set	sun4d_handler_irq, %g5
453	sethi	%hi(0x40000000), %g3		! call
454	sub	%g5, %g4, %g5
455	srl	%g5, 2, %g5
456	or	%g5, %g3, %g5
457	st	%g5, [%g4]
458
459#ifdef CONFIG_SMP
460	/* Get our CPU id out of bootbus */
461	set     SUN4D_BOOTBUS_CPUID, %g3
462	lduba   [%g3] ASI_M_CTL, %g3
463	and     %g3, 0xf8, %g3
464	srl     %g3, 3, %g4
465	sta     %g4, [%g0] ASI_M_VIKING_TMP1
466	sethi	%hi(boot_cpu_id), %g5
467	stb	%g4, [%g5 + %lo(boot_cpu_id)]
468#endif
469
470	/* Fall through to sun4m_init */
471
472sun4m_init:
473/* Ok, the PROM could have done funny things and apple cider could still
474 * be sitting in the fault status/address registers.  Read them all to
475 * clear them so we don't get magic faults later on.
476 */
477/* This sucks, apparently this makes Vikings call prom panic, will fix later */
4782:
479		rd	%psr, %o1
480		srl	%o1, PSR_IMPL_SHIFT, %o1	! Get a type of the CPU
481
482		subcc	%o1, PSR_IMPL_TI, %g0		! TI: Viking or MicroSPARC
483		be	continue_boot
484		 nop
485
486		set	AC_M_SFSR, %o0
487		lda	[%o0] ASI_M_MMUREGS, %g0
488		set	AC_M_SFAR, %o0
489		lda	[%o0] ASI_M_MMUREGS, %g0
490
491		/* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
492		subcc	%o1, 0, %g0
493		be	continue_boot
494		 nop
495
496		set	AC_M_AFSR, %o0
497		lda	[%o0] ASI_M_MMUREGS, %g0
498		set	AC_M_AFAR, %o0
499		lda	[%o0] ASI_M_MMUREGS, %g0
500		 nop
501
502
503continue_boot:
504
505/* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
506 * show-time!
507 */
508		/* Turn on Supervisor, EnableFloating, and all the PIL bits.
509		 * Also puts us in register window zero with traps off.
510		 */
511		set	(PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
512		wr	%g2, 0x0, %psr
513		WRITE_PAUSE
514
515		/* I want a kernel stack NOW! */
516		set	init_thread_union, %g1
517		set	(THREAD_SIZE - STACKFRAME_SZ), %g2
518		add	%g1, %g2, %sp
519		mov	0, %fp			/* And for good luck */
520
521		/* Zero out our BSS section. */
522		set	__bss_start , %o0	! First address of BSS
523		set	_end , %o1		! Last address of BSS
524		add	%o0, 0x1, %o0
5251:
526		stb	%g0, [%o0]
527		subcc	%o0, %o1, %g0
528		bl	1b
529		 add	%o0, 0x1, %o0
530
531		/* If boot_cpu_id has not been setup by machine specific
532		 * init-code above we default it to zero.
533		 */
534		sethi	%hi(boot_cpu_id), %g2
535		ldub	[%g2 + %lo(boot_cpu_id)], %g3
536		cmp	%g3, 0xff
537		bne	1f
538		 nop
539		mov	%g0, %g3
540		stub	%g3, [%g2 + %lo(boot_cpu_id)]
541
5421:		sll	%g3, 2, %g3
543
544		/* Initialize the uwinmask value for init task just in case.
545		 * But first make current_set[boot_cpu_id] point to something useful.
546		 */
547		set	init_thread_union, %g6
548		set	current_set, %g2
549#ifdef CONFIG_SMP
550		st	%g6, [%g2]
551		add	%g2, %g3, %g2
552#endif
553		st	%g6, [%g2]
554
555		st	%g0, [%g6 + TI_UWINMASK]
556
557/* Compute NWINDOWS and stash it away. Now uses %wim trick explained
558 * in the V8 manual. Ok, this method seems to work, Sparc is cool...
559 * No, it doesn't work, have to play the save/readCWP/restore trick.
560 */
561
562		wr	%g0, 0x0, %wim			! so we do not get a trap
563		WRITE_PAUSE
564
565		save
566
567		rd	%psr, %g3
568
569		restore
570
571		and	%g3, 0x1f, %g3
572		add	%g3, 0x1, %g3
573
574		mov	2, %g1
575		wr	%g1, 0x0, %wim			! make window 1 invalid
576		WRITE_PAUSE
577
578		cmp	%g3, 0x7
579		bne	2f
580		 nop
581
582		/* Adjust our window handling routines to
583		 * do things correctly on 7 window Sparcs.
584		 */
585
586#define		PATCH_INSN(src, dest) \
587		set	src, %g5; \
588		set	dest, %g2; \
589		ld	[%g5], %g4; \
590		st	%g4, [%g2];
591
592		/* Patch for window spills... */
593		PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
594		PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
595		PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
596
597		/* Patch for window fills... */
598		PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
599		PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
600
601		/* Patch for trap entry setup... */
602		PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
603		PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
604		PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
605		PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
606		PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
607		PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
608
609		/* Patch for returning from traps... */
610		PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
611		PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
612		PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
613		PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
614		PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
615
616		/* Patch for killing user windows from the register file. */
617		PATCH_INSN(kuw_patch1_7win, kuw_patch1)
618
619		/* Now patch the kernel window flush sequences.
620		 * This saves 2 traps on every switch and fork.
621		 */
622		set	0x01000000, %g4
623		set	flush_patch_one, %g5
624		st	%g4, [%g5 + 0x18]
625		st	%g4, [%g5 + 0x1c]
626		set	flush_patch_two, %g5
627		st	%g4, [%g5 + 0x18]
628		st	%g4, [%g5 + 0x1c]
629		set	flush_patch_three, %g5
630		st	%g4, [%g5 + 0x18]
631		st	%g4, [%g5 + 0x1c]
632		set	flush_patch_four, %g5
633		st	%g4, [%g5 + 0x18]
634		st	%g4, [%g5 + 0x1c]
635		set	flush_patch_exception, %g5
636		st	%g4, [%g5 + 0x18]
637		st	%g4, [%g5 + 0x1c]
638		set	flush_patch_switch, %g5
639		st	%g4, [%g5 + 0x18]
640		st	%g4, [%g5 + 0x1c]
641
6422:
643		sethi	%hi(nwindows), %g4
644		st	%g3, [%g4 + %lo(nwindows)]	! store final value
645		sub	%g3, 0x1, %g3
646		sethi	%hi(nwindowsm1), %g4
647		st	%g3, [%g4 + %lo(nwindowsm1)]
648
649		/* Here we go, start using Linux's trap table... */
650		set	trapbase, %g3
651		wr	%g3, 0x0, %tbr
652		WRITE_PAUSE
653
654		/* Finally, turn on traps so that we can call c-code. */
655		rd	%psr, %g3
656		wr	%g3, 0x0, %psr
657		WRITE_PAUSE
658
659		wr	%g3, PSR_ET, %psr
660		WRITE_PAUSE
661
662		/* Call sparc32_start_kernel(struct linux_romvec *rp) */
663		sethi	%hi(prom_vector_p), %g5
664		ld	[%g5 + %lo(prom_vector_p)], %o0
665		call	sparc32_start_kernel
666		 nop
667
668		/* We should not get here. */
669		call	halt_me
670		 nop
671
672no_sun4e_here:
673		ld	[%g7 + 0x68], %o1
674		set	sun4e_notsup, %o0
675		call	%o1
676		 nop
677		b	halt_me
678		 nop
679
680		__INITDATA
681
682sun4u_1:
683		.asciz "finddevice"
684		.align	4
685sun4u_2:
686		.asciz "/chosen"
687		.align	4
688sun4u_3:
689		.asciz "getprop"
690		.align	4
691sun4u_4:
692		.asciz "stdout"
693		.align	4
694sun4u_5:
695		.asciz "write"
696		.align	4
697sun4u_6:
698		.asciz  "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r"
699sun4u_6e:
700		.align	4
701sun4u_7:
702		.asciz "exit"
703		.align	8
704sun4u_a1:
705		.word	0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0
706sun4u_r1:
707		.word	0
708sun4u_a2:
709		.word	0, sun4u_3, 0, 4, 0, 1, 0
710sun4u_i2:
711		.word	0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0
712sun4u_r2:
713		.word	0
714sun4u_a3:
715		.word	0, sun4u_5, 0, 3, 0, 1, 0
716sun4u_i3:
717		.word	0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0
718sun4u_r3:
719		.word	0
720sun4u_a4:
721		.word	0, sun4u_7, 0, 0, 0, 0
722sun4u_r4:
723
724		__INIT
725no_sun4u_here:
726		set	sun4u_a1, %o0
727		set	current_pc, %l2
728		cmp	%l2, %g3
729		be	1f
730		 mov	%o4, %l0
731		sub	%g3, %l2, %l6
732		add	%o0, %l6, %o0
733		mov	%o0, %l4
734		mov	sun4u_r4 - sun4u_a1, %l3
735		ld	[%l4], %l5
7362:
737		add	%l4, 4, %l4
738		cmp	%l5, %l2
739		add	%l5, %l6, %l5
740		bgeu,a	3f
741		 st	%l5, [%l4 - 4]
7423:
743		subcc	%l3, 4, %l3
744		bne	2b
745		 ld	[%l4], %l5
7461:
747		call	%l0
748		 mov	%o0, %l1
749
750		ld	[%l1 + (sun4u_r1 - sun4u_a1)], %o1
751		add	%l1, (sun4u_a2 - sun4u_a1), %o0
752		call	%l0
753		 st	%o1, [%o0 + (sun4u_i2 - sun4u_a2)]
754
755		ld	[%l1 + (sun4u_1 - sun4u_a1)], %o1
756		add	%l1, (sun4u_a3 - sun4u_a1), %o0
757		call	%l0
758		st	%o1, [%o0 + (sun4u_i3 - sun4u_a3)]
759
760		call	%l0
761		 add	%l1, (sun4u_a4 - sun4u_a1), %o0
762
763		/* Not reached */
764halt_me:
765		ld	[%g7 + 0x74], %o0
766		call	%o0			! Get us out of here...
767		 nop				! Apparently Solaris is better.
768
769/* Ok, now we continue in the .data/.text sections */
770
771	.data
772	.align 4
773
774/*
775 * Fill up the prom vector, note in particular the kind first element,
776 * no joke. I don't need all of them in here as the entire prom vector
777 * gets initialized in c-code so all routines can use it.
778 */
779
780prom_vector_p:
781		.word 0
782
783/* We calculate the following at boot time, window fills/spills and trap entry
784 * code uses these to keep track of the register windows.
785 */
786
787	.align 4
788	.globl	nwindows
789	.globl	nwindowsm1
790nwindows:
791	.word	8
792nwindowsm1:
793	.word	7
794
795/* Boot time debugger vector value.  We need this later on. */
796
797	.align 4
798	.globl	linux_dbvec
799linux_dbvec:
800	.word	0
801	.word	0
802
803	.align 8
804
805	.globl	lvl14_save
806lvl14_save:
807	.word	0
808	.word	0
809	.word	0
810	.word	0
811	.word	t_irq14
812