1 #ifndef _ENTRY_H 2 #define _ENTRY_H 3 4 #include <linux/kernel.h> 5 #include <linux/types.h> 6 #include <linux/init.h> 7 8 /* irq */ 9 void handler_irq(int irq, struct pt_regs *regs); 10 11 #ifdef CONFIG_SPARC32 12 /* traps */ 13 void do_hw_interrupt(struct pt_regs *regs, unsigned long type); 14 void do_illegal_instruction(struct pt_regs *regs, unsigned long pc, 15 unsigned long npc, unsigned long psr); 16 17 void do_priv_instruction(struct pt_regs *regs, unsigned long pc, 18 unsigned long npc, unsigned long psr); 19 void do_memaccess_unaligned(struct pt_regs *regs, unsigned long pc, 20 unsigned long npc, unsigned long psr); 21 void do_fpd_trap(struct pt_regs *regs, unsigned long pc, 22 unsigned long npc, unsigned long psr); 23 void do_fpe_trap(struct pt_regs *regs, unsigned long pc, 24 unsigned long npc, unsigned long psr); 25 void handle_tag_overflow(struct pt_regs *regs, unsigned long pc, 26 unsigned long npc, unsigned long psr); 27 void handle_watchpoint(struct pt_regs *regs, unsigned long pc, 28 unsigned long npc, unsigned long psr); 29 void handle_reg_access(struct pt_regs *regs, unsigned long pc, 30 unsigned long npc, unsigned long psr); 31 void handle_cp_disabled(struct pt_regs *regs, unsigned long pc, 32 unsigned long npc, unsigned long psr); 33 void handle_cp_exception(struct pt_regs *regs, unsigned long pc, 34 unsigned long npc, unsigned long psr); 35 36 37 38 /* entry.S */ 39 void fpsave(unsigned long *fpregs, unsigned long *fsr, 40 void *fpqueue, unsigned long *fpqdepth); 41 void fpload(unsigned long *fpregs, unsigned long *fsr); 42 43 #else /* CONFIG_SPARC32 */ 44 45 #include <asm/trap_block.h> 46 47 struct popc_3insn_patch_entry { 48 unsigned int addr; 49 unsigned int insns[3]; 50 }; 51 extern struct popc_3insn_patch_entry __popc_3insn_patch, 52 __popc_3insn_patch_end; 53 54 struct popc_6insn_patch_entry { 55 unsigned int addr; 56 unsigned int insns[6]; 57 }; 58 extern struct popc_6insn_patch_entry __popc_6insn_patch, 59 __popc_6insn_patch_end; 60 61 struct pause_patch_entry { 62 unsigned int addr; 63 unsigned int insns[3]; 64 }; 65 extern struct pause_patch_entry __pause_3insn_patch, 66 __pause_3insn_patch_end; 67 68 void __init per_cpu_patch(void); 69 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *, 70 struct sun4v_1insn_patch_entry *); 71 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *, 72 struct sun4v_2insn_patch_entry *); 73 void __init sun4v_patch(void); 74 void __init boot_cpu_id_too_large(int cpu); 75 extern unsigned int dcache_parity_tl1_occurred; 76 extern unsigned int icache_parity_tl1_occurred; 77 78 asmlinkage void sparc_breakpoint(struct pt_regs *regs); 79 void timer_interrupt(int irq, struct pt_regs *regs); 80 81 void do_notify_resume(struct pt_regs *regs, 82 unsigned long orig_i0, 83 unsigned long thread_info_flags); 84 85 asmlinkage int syscall_trace_enter(struct pt_regs *regs); 86 asmlinkage void syscall_trace_leave(struct pt_regs *regs); 87 88 void bad_trap_tl1(struct pt_regs *regs, long lvl); 89 90 void do_fpieee(struct pt_regs *regs); 91 void do_fpother(struct pt_regs *regs); 92 void do_tof(struct pt_regs *regs); 93 void do_div0(struct pt_regs *regs); 94 void do_illegal_instruction(struct pt_regs *regs); 95 void mem_address_unaligned(struct pt_regs *regs, 96 unsigned long sfar, 97 unsigned long sfsr); 98 void sun4v_do_mna(struct pt_regs *regs, 99 unsigned long addr, 100 unsigned long type_ctx); 101 void do_privop(struct pt_regs *regs); 102 void do_privact(struct pt_regs *regs); 103 void do_cee(struct pt_regs *regs); 104 void do_cee_tl1(struct pt_regs *regs); 105 void do_dae_tl1(struct pt_regs *regs); 106 void do_iae_tl1(struct pt_regs *regs); 107 void do_div0_tl1(struct pt_regs *regs); 108 void do_fpdis_tl1(struct pt_regs *regs); 109 void do_fpieee_tl1(struct pt_regs *regs); 110 void do_fpother_tl1(struct pt_regs *regs); 111 void do_ill_tl1(struct pt_regs *regs); 112 void do_irq_tl1(struct pt_regs *regs); 113 void do_lddfmna_tl1(struct pt_regs *regs); 114 void do_stdfmna_tl1(struct pt_regs *regs); 115 void do_paw(struct pt_regs *regs); 116 void do_paw_tl1(struct pt_regs *regs); 117 void do_vaw(struct pt_regs *regs); 118 void do_vaw_tl1(struct pt_regs *regs); 119 void do_tof_tl1(struct pt_regs *regs); 120 void do_getpsr(struct pt_regs *regs); 121 122 void spitfire_insn_access_exception(struct pt_regs *regs, 123 unsigned long sfsr, 124 unsigned long sfar); 125 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, 126 unsigned long sfsr, 127 unsigned long sfar); 128 void spitfire_data_access_exception(struct pt_regs *regs, 129 unsigned long sfsr, 130 unsigned long sfar); 131 void spitfire_data_access_exception_tl1(struct pt_regs *regs, 132 unsigned long sfsr, 133 unsigned long sfar); 134 void spitfire_access_error(struct pt_regs *regs, 135 unsigned long status_encoded, 136 unsigned long afar); 137 138 void cheetah_fecc_handler(struct pt_regs *regs, 139 unsigned long afsr, 140 unsigned long afar); 141 void cheetah_cee_handler(struct pt_regs *regs, 142 unsigned long afsr, 143 unsigned long afar); 144 void cheetah_deferred_handler(struct pt_regs *regs, 145 unsigned long afsr, 146 unsigned long afar); 147 void cheetah_plus_parity_error(int type, struct pt_regs *regs); 148 149 void sun4v_insn_access_exception(struct pt_regs *regs, 150 unsigned long addr, 151 unsigned long type_ctx); 152 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, 153 unsigned long addr, 154 unsigned long type_ctx); 155 void sun4v_data_access_exception(struct pt_regs *regs, 156 unsigned long addr, 157 unsigned long type_ctx); 158 void sun4v_data_access_exception_tl1(struct pt_regs *regs, 159 unsigned long addr, 160 unsigned long type_ctx); 161 void sun4v_resum_error(struct pt_regs *regs, 162 unsigned long offset); 163 void sun4v_resum_overflow(struct pt_regs *regs); 164 void sun4v_nonresum_error(struct pt_regs *regs, 165 unsigned long offset); 166 void sun4v_nonresum_overflow(struct pt_regs *regs); 167 168 extern unsigned long sun4v_err_itlb_vaddr; 169 extern unsigned long sun4v_err_itlb_ctx; 170 extern unsigned long sun4v_err_itlb_pte; 171 extern unsigned long sun4v_err_itlb_error; 172 173 void sun4v_itlb_error_report(struct pt_regs *regs, int tl); 174 175 extern unsigned long sun4v_err_dtlb_vaddr; 176 extern unsigned long sun4v_err_dtlb_ctx; 177 extern unsigned long sun4v_err_dtlb_pte; 178 extern unsigned long sun4v_err_dtlb_error; 179 180 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl); 181 void hypervisor_tlbop_error(unsigned long err, 182 unsigned long op); 183 void hypervisor_tlbop_error_xcall(unsigned long err, 184 unsigned long op); 185 186 /* WARNING: The error trap handlers in assembly know the precise 187 * layout of the following structure. 188 * 189 * C-level handlers in traps.c use this information to log the 190 * error and then determine how to recover (if possible). 191 */ 192 struct cheetah_err_info { 193 /*0x00*/u64 afsr; 194 /*0x08*/u64 afar; 195 196 /* D-cache state */ 197 /*0x10*/u64 dcache_data[4]; /* The actual data */ 198 /*0x30*/u64 dcache_index; /* D-cache index */ 199 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */ 200 /*0x40*/u64 dcache_utag; /* D-cache microtag */ 201 /*0x48*/u64 dcache_stag; /* D-cache snooptag */ 202 203 /* I-cache state */ 204 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */ 205 /*0x90*/u64 icache_index; /* I-cache index */ 206 /*0x98*/u64 icache_tag; /* I-cache phys tag */ 207 /*0xa0*/u64 icache_utag; /* I-cache microtag */ 208 /*0xa8*/u64 icache_stag; /* I-cache snooptag */ 209 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */ 210 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */ 211 212 /* E-cache state */ 213 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */ 214 /*0xe0*/u64 ecache_index; /* E-cache index */ 215 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */ 216 217 /*0xf0*/u64 __pad[32 - 30]; 218 }; 219 #define CHAFSR_INVALID ((u64)-1L) 220 221 /* This is allocated at boot time based upon the largest hardware 222 * cpu ID in the system. We allocate two entries per cpu, one for 223 * TL==0 logging and one for TL >= 1 logging. 224 */ 225 extern struct cheetah_err_info *cheetah_error_log; 226 227 /* UPA nodes send interrupt packet to UltraSparc with first data reg 228 * value low 5 (7 on Starfire) bits holding the IRQ identifier being 229 * delivered. We must translate this into a non-vector IRQ so we can 230 * set the softint on this cpu. 231 * 232 * To make processing these packets efficient and race free we use 233 * an array of irq buckets below. The interrupt vector handler in 234 * entry.S feeds incoming packets into per-cpu pil-indexed lists. 235 * 236 * If you make changes to ino_bucket, please update hand coded assembler 237 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S 238 */ 239 struct ino_bucket { 240 /*0x00*/unsigned long __irq_chain_pa; 241 242 /* Interrupt number assigned to this INO. */ 243 /*0x08*/unsigned int __irq; 244 /*0x0c*/unsigned int __pad; 245 }; 246 247 extern struct ino_bucket *ivector_table; 248 extern unsigned long ivector_table_pa; 249 250 void init_irqwork_curcpu(void); 251 void sun4v_register_mondo_queues(int this_cpu); 252 253 #endif /* CONFIG_SPARC32 */ 254 #endif /* _ENTRY_H */ 255