1 /* These get patched into the trap table at boot time 2 * once we know we have a cheetah processor. 3 */ 4 .globl cheetah_fecc_trap_vector 5 .type cheetah_fecc_trap_vector,#function 6cheetah_fecc_trap_vector: 7 membar #Sync 8 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 9 andn %g1, DCU_DC | DCU_IC, %g1 10 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 11 membar #Sync 12 sethi %hi(cheetah_fast_ecc), %g2 13 jmpl %g2 + %lo(cheetah_fast_ecc), %g0 14 mov 0, %g1 15 .size cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector 16 17 .globl cheetah_fecc_trap_vector_tl1 18 .type cheetah_fecc_trap_vector_tl1,#function 19cheetah_fecc_trap_vector_tl1: 20 membar #Sync 21 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 22 andn %g1, DCU_DC | DCU_IC, %g1 23 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 24 membar #Sync 25 sethi %hi(cheetah_fast_ecc), %g2 26 jmpl %g2 + %lo(cheetah_fast_ecc), %g0 27 mov 1, %g1 28 .size cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1 29 30 .globl cheetah_cee_trap_vector 31 .type cheetah_cee_trap_vector,#function 32cheetah_cee_trap_vector: 33 membar #Sync 34 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 35 andn %g1, DCU_IC, %g1 36 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 37 membar #Sync 38 sethi %hi(cheetah_cee), %g2 39 jmpl %g2 + %lo(cheetah_cee), %g0 40 mov 0, %g1 41 .size cheetah_cee_trap_vector,.-cheetah_cee_trap_vector 42 43 .globl cheetah_cee_trap_vector_tl1 44 .type cheetah_cee_trap_vector_tl1,#function 45cheetah_cee_trap_vector_tl1: 46 membar #Sync 47 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 48 andn %g1, DCU_IC, %g1 49 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 50 membar #Sync 51 sethi %hi(cheetah_cee), %g2 52 jmpl %g2 + %lo(cheetah_cee), %g0 53 mov 1, %g1 54 .size cheetah_cee_trap_vector_tl1,.-cheetah_cee_trap_vector_tl1 55 56 .globl cheetah_deferred_trap_vector 57 .type cheetah_deferred_trap_vector,#function 58cheetah_deferred_trap_vector: 59 membar #Sync 60 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; 61 andn %g1, DCU_DC | DCU_IC, %g1; 62 stxa %g1, [%g0] ASI_DCU_CONTROL_REG; 63 membar #Sync; 64 sethi %hi(cheetah_deferred_trap), %g2 65 jmpl %g2 + %lo(cheetah_deferred_trap), %g0 66 mov 0, %g1 67 .size cheetah_deferred_trap_vector,.-cheetah_deferred_trap_vector 68 69 .globl cheetah_deferred_trap_vector_tl1 70 .type cheetah_deferred_trap_vector_tl1,#function 71cheetah_deferred_trap_vector_tl1: 72 membar #Sync; 73 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; 74 andn %g1, DCU_DC | DCU_IC, %g1; 75 stxa %g1, [%g0] ASI_DCU_CONTROL_REG; 76 membar #Sync; 77 sethi %hi(cheetah_deferred_trap), %g2 78 jmpl %g2 + %lo(cheetah_deferred_trap), %g0 79 mov 1, %g1 80 .size cheetah_deferred_trap_vector_tl1,.-cheetah_deferred_trap_vector_tl1 81 82 /* Cheetah+ specific traps. These are for the new I/D cache parity 83 * error traps. The first argument to cheetah_plus_parity_handler 84 * is encoded as follows: 85 * 86 * Bit0: 0=dcache,1=icache 87 * Bit1: 0=recoverable,1=unrecoverable 88 */ 89 .globl cheetah_plus_dcpe_trap_vector 90 .type cheetah_plus_dcpe_trap_vector,#function 91cheetah_plus_dcpe_trap_vector: 92 membar #Sync 93 sethi %hi(do_cheetah_plus_data_parity), %g7 94 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0 95 nop 96 nop 97 nop 98 nop 99 nop 100 .size cheetah_plus_dcpe_trap_vector,.-cheetah_plus_dcpe_trap_vector 101 102 .type do_cheetah_plus_data_parity,#function 103do_cheetah_plus_data_parity: 104 rdpr %pil, %g2 105 wrpr %g0, PIL_NORMAL_MAX, %pil 106 ba,pt %xcc, etrap_irq 107 rd %pc, %g7 108#ifdef CONFIG_TRACE_IRQFLAGS 109 call trace_hardirqs_off 110 nop 111#endif 112 mov 0x0, %o0 113 call cheetah_plus_parity_error 114 add %sp, PTREGS_OFF, %o1 115 ba,a,pt %xcc, rtrap_irq 116 .size do_cheetah_plus_data_parity,.-do_cheetah_plus_data_parity 117 118 .globl cheetah_plus_dcpe_trap_vector_tl1 119 .type cheetah_plus_dcpe_trap_vector_tl1,#function 120cheetah_plus_dcpe_trap_vector_tl1: 121 membar #Sync 122 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate 123 sethi %hi(do_dcpe_tl1), %g3 124 jmpl %g3 + %lo(do_dcpe_tl1), %g0 125 nop 126 nop 127 nop 128 nop 129 .size cheetah_plus_dcpe_trap_vector_tl1,.-cheetah_plus_dcpe_trap_vector_tl1 130 131 .globl cheetah_plus_icpe_trap_vector 132 .type cheetah_plus_icpe_trap_vector,#function 133cheetah_plus_icpe_trap_vector: 134 membar #Sync 135 sethi %hi(do_cheetah_plus_insn_parity), %g7 136 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0 137 nop 138 nop 139 nop 140 nop 141 nop 142 .size cheetah_plus_icpe_trap_vector,.-cheetah_plus_icpe_trap_vector 143 144 .type do_cheetah_plus_insn_parity,#function 145do_cheetah_plus_insn_parity: 146 rdpr %pil, %g2 147 wrpr %g0, PIL_NORMAL_MAX, %pil 148 ba,pt %xcc, etrap_irq 149 rd %pc, %g7 150#ifdef CONFIG_TRACE_IRQFLAGS 151 call trace_hardirqs_off 152 nop 153#endif 154 mov 0x1, %o0 155 call cheetah_plus_parity_error 156 add %sp, PTREGS_OFF, %o1 157 ba,a,pt %xcc, rtrap_irq 158 .size do_cheetah_plus_insn_parity,.-do_cheetah_plus_insn_parity 159 160 .globl cheetah_plus_icpe_trap_vector_tl1 161 .type cheetah_plus_icpe_trap_vector_tl1,#function 162cheetah_plus_icpe_trap_vector_tl1: 163 membar #Sync 164 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate 165 sethi %hi(do_icpe_tl1), %g3 166 jmpl %g3 + %lo(do_icpe_tl1), %g0 167 nop 168 nop 169 nop 170 nop 171 .size cheetah_plus_icpe_trap_vector_tl1,.-cheetah_plus_icpe_trap_vector_tl1 172 173 /* If we take one of these traps when tl >= 1, then we 174 * jump to interrupt globals. If some trap level above us 175 * was also using interrupt globals, we cannot recover. 176 * We may use all interrupt global registers except %g6. 177 */ 178 .globl do_dcpe_tl1 179 .type do_dcpe_tl1,#function 180do_dcpe_tl1: 181 rdpr %tl, %g1 ! Save original trap level 182 mov 1, %g2 ! Setup TSTATE checking loop 183 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit 1841: wrpr %g2, %tl ! Set trap level to check 185 rdpr %tstate, %g4 ! Read TSTATE for this level 186 andcc %g4, %g3, %g0 ! Interrupt globals in use? 187 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable 188 wrpr %g1, %tl ! Restore original trap level 189 add %g2, 1, %g2 ! Next trap level 190 cmp %g2, %g1 ! Hit them all yet? 191 ble,pt %icc, 1b ! Not yet 192 nop 193 wrpr %g1, %tl ! Restore original trap level 194do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ 195 sethi %hi(dcache_parity_tl1_occurred), %g2 196 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1 197 add %g1, 1, %g1 198 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)] 199 /* Reset D-cache parity */ 200 sethi %hi(1 << 16), %g1 ! D-cache size 201 mov (1 << 5), %g2 ! D-cache line size 202 sub %g1, %g2, %g1 ! Move down 1 cacheline 2031: srl %g1, 14, %g3 ! Compute UTAG 204 membar #Sync 205 stxa %g3, [%g1] ASI_DCACHE_UTAG 206 membar #Sync 207 sub %g2, 8, %g3 ! 64-bit data word within line 2082: membar #Sync 209 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA 210 membar #Sync 211 subcc %g3, 8, %g3 ! Next 64-bit data word 212 bge,pt %icc, 2b 213 nop 214 subcc %g1, %g2, %g1 ! Next cacheline 215 bge,pt %icc, 1b 216 nop 217 ba,a,pt %xcc, dcpe_icpe_tl1_common 218 219do_dcpe_tl1_fatal: 220 sethi %hi(1f), %g7 221 ba,pt %xcc, etraptl1 2221: or %g7, %lo(1b), %g7 223 mov 0x2, %o0 224 call cheetah_plus_parity_error 225 add %sp, PTREGS_OFF, %o1 226 ba,a,pt %xcc, rtrap 227 .size do_dcpe_tl1,.-do_dcpe_tl1 228 229 .globl do_icpe_tl1 230 .type do_icpe_tl1,#function 231do_icpe_tl1: 232 rdpr %tl, %g1 ! Save original trap level 233 mov 1, %g2 ! Setup TSTATE checking loop 234 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit 2351: wrpr %g2, %tl ! Set trap level to check 236 rdpr %tstate, %g4 ! Read TSTATE for this level 237 andcc %g4, %g3, %g0 ! Interrupt globals in use? 238 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable 239 wrpr %g1, %tl ! Restore original trap level 240 add %g2, 1, %g2 ! Next trap level 241 cmp %g2, %g1 ! Hit them all yet? 242 ble,pt %icc, 1b ! Not yet 243 nop 244 wrpr %g1, %tl ! Restore original trap level 245do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ 246 sethi %hi(icache_parity_tl1_occurred), %g2 247 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1 248 add %g1, 1, %g1 249 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)] 250 /* Flush I-cache */ 251 sethi %hi(1 << 15), %g1 ! I-cache size 252 mov (1 << 5), %g2 ! I-cache line size 253 sub %g1, %g2, %g1 2541: or %g1, (2 << 3), %g3 255 stxa %g0, [%g3] ASI_IC_TAG 256 membar #Sync 257 subcc %g1, %g2, %g1 258 bge,pt %icc, 1b 259 nop 260 ba,a,pt %xcc, dcpe_icpe_tl1_common 261 262do_icpe_tl1_fatal: 263 sethi %hi(1f), %g7 264 ba,pt %xcc, etraptl1 2651: or %g7, %lo(1b), %g7 266 mov 0x3, %o0 267 call cheetah_plus_parity_error 268 add %sp, PTREGS_OFF, %o1 269 ba,a,pt %xcc, rtrap 270 .size do_icpe_tl1,.-do_icpe_tl1 271 272 .type dcpe_icpe_tl1_common,#function 273dcpe_icpe_tl1_common: 274 /* Flush D-cache, re-enable D/I caches in DCU and finally 275 * retry the trapping instruction. 276 */ 277 sethi %hi(1 << 16), %g1 ! D-cache size 278 mov (1 << 5), %g2 ! D-cache line size 279 sub %g1, %g2, %g1 2801: stxa %g0, [%g1] ASI_DCACHE_TAG 281 membar #Sync 282 subcc %g1, %g2, %g1 283 bge,pt %icc, 1b 284 nop 285 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 286 or %g1, (DCU_DC | DCU_IC), %g1 287 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 288 membar #Sync 289 retry 290 .size dcpe_icpe_tl1_common,.-dcpe_icpe_tl1_common 291 292 /* Capture I/D/E-cache state into per-cpu error scoreboard. 293 * 294 * %g1: (TL>=0) ? 1 : 0 295 * %g2: scratch 296 * %g3: scratch 297 * %g4: AFSR 298 * %g5: AFAR 299 * %g6: unused, will have current thread ptr after etrap 300 * %g7: scratch 301 */ 302 .type __cheetah_log_error,#function 303__cheetah_log_error: 304 /* Put "TL1" software bit into AFSR. */ 305 and %g1, 0x1, %g1 306 sllx %g1, 63, %g2 307 or %g4, %g2, %g4 308 309 /* Get log entry pointer for this cpu at this trap level. */ 310 BRANCH_IF_JALAPENO(g2,g3,50f) 311 ldxa [%g0] ASI_SAFARI_CONFIG, %g2 312 srlx %g2, 17, %g2 313 ba,pt %xcc, 60f 314 and %g2, 0x3ff, %g2 315 31650: ldxa [%g0] ASI_JBUS_CONFIG, %g2 317 srlx %g2, 17, %g2 318 and %g2, 0x1f, %g2 319 32060: sllx %g2, 9, %g2 321 sethi %hi(cheetah_error_log), %g3 322 ldx [%g3 + %lo(cheetah_error_log)], %g3 323 brz,pn %g3, 80f 324 nop 325 326 add %g3, %g2, %g3 327 sllx %g1, 8, %g1 328 add %g3, %g1, %g1 329 330 /* %g1 holds pointer to the top of the logging scoreboard */ 331 ldx [%g1 + 0x0], %g7 332 cmp %g7, -1 333 bne,pn %xcc, 80f 334 nop 335 336 stx %g4, [%g1 + 0x0] 337 stx %g5, [%g1 + 0x8] 338 add %g1, 0x10, %g1 339 340 /* %g1 now points to D-cache logging area */ 341 set 0x3ff8, %g2 /* DC_addr mask */ 342 and %g5, %g2, %g2 /* DC_addr bits of AFAR */ 343 srlx %g5, 12, %g3 344 or %g3, 1, %g3 /* PHYS tag + valid */ 345 34610: ldxa [%g2] ASI_DCACHE_TAG, %g7 347 cmp %g3, %g7 /* TAG match? */ 348 bne,pt %xcc, 13f 349 nop 350 351 /* Yep, what we want, capture state. */ 352 stx %g2, [%g1 + 0x20] 353 stx %g7, [%g1 + 0x28] 354 355 /* A membar Sync is required before and after utag access. */ 356 membar #Sync 357 ldxa [%g2] ASI_DCACHE_UTAG, %g7 358 membar #Sync 359 stx %g7, [%g1 + 0x30] 360 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7 361 stx %g7, [%g1 + 0x38] 362 clr %g3 363 36412: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7 365 stx %g7, [%g1] 366 add %g3, (1 << 5), %g3 367 cmp %g3, (4 << 5) 368 bl,pt %xcc, 12b 369 add %g1, 0x8, %g1 370 371 ba,pt %xcc, 20f 372 add %g1, 0x20, %g1 373 37413: sethi %hi(1 << 14), %g7 375 add %g2, %g7, %g2 376 srlx %g2, 14, %g7 377 cmp %g7, 4 378 bl,pt %xcc, 10b 379 nop 380 381 add %g1, 0x40, %g1 382 383 /* %g1 now points to I-cache logging area */ 38420: set 0x1fe0, %g2 /* IC_addr mask */ 385 and %g5, %g2, %g2 /* IC_addr bits of AFAR */ 386 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */ 387 srlx %g5, (13 - 8), %g3 /* Make PTAG */ 388 andn %g3, 0xff, %g3 /* Mask off undefined bits */ 389 39021: ldxa [%g2] ASI_IC_TAG, %g7 391 andn %g7, 0xff, %g7 392 cmp %g3, %g7 393 bne,pt %xcc, 23f 394 nop 395 396 /* Yep, what we want, capture state. */ 397 stx %g2, [%g1 + 0x40] 398 stx %g7, [%g1 + 0x48] 399 add %g2, (1 << 3), %g2 400 ldxa [%g2] ASI_IC_TAG, %g7 401 add %g2, (1 << 3), %g2 402 stx %g7, [%g1 + 0x50] 403 ldxa [%g2] ASI_IC_TAG, %g7 404 add %g2, (1 << 3), %g2 405 stx %g7, [%g1 + 0x60] 406 ldxa [%g2] ASI_IC_TAG, %g7 407 stx %g7, [%g1 + 0x68] 408 sub %g2, (3 << 3), %g2 409 ldxa [%g2] ASI_IC_STAG, %g7 410 stx %g7, [%g1 + 0x58] 411 clr %g3 412 srlx %g2, 2, %g2 413 41422: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7 415 stx %g7, [%g1] 416 add %g3, (1 << 3), %g3 417 cmp %g3, (8 << 3) 418 bl,pt %xcc, 22b 419 add %g1, 0x8, %g1 420 421 ba,pt %xcc, 30f 422 add %g1, 0x30, %g1 423 42423: sethi %hi(1 << 14), %g7 425 add %g2, %g7, %g2 426 srlx %g2, 14, %g7 427 cmp %g7, 4 428 bl,pt %xcc, 21b 429 nop 430 431 add %g1, 0x70, %g1 432 433 /* %g1 now points to E-cache logging area */ 43430: andn %g5, (32 - 1), %g2 435 stx %g2, [%g1 + 0x20] 436 ldxa [%g2] ASI_EC_TAG_DATA, %g7 437 stx %g7, [%g1 + 0x28] 438 ldxa [%g2] ASI_EC_R, %g0 439 clr %g3 440 44131: ldxa [%g3] ASI_EC_DATA, %g7 442 stx %g7, [%g1 + %g3] 443 add %g3, 0x8, %g3 444 cmp %g3, 0x20 445 446 bl,pt %xcc, 31b 447 nop 44880: 449 rdpr %tt, %g2 450 cmp %g2, 0x70 451 be c_fast_ecc 452 cmp %g2, 0x63 453 be c_cee 454 nop 455 ba,a,pt %xcc, c_deferred 456 .size __cheetah_log_error,.-__cheetah_log_error 457 458 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc 459 * in the trap table. That code has done a memory barrier 460 * and has disabled both the I-cache and D-cache in the DCU 461 * control register. The I-cache is disabled so that we may 462 * capture the corrupted cache line, and the D-cache is disabled 463 * because corrupt data may have been placed there and we don't 464 * want to reference it. 465 * 466 * %g1 is one if this trap occurred at %tl >= 1. 467 * 468 * Next, we turn off error reporting so that we don't recurse. 469 */ 470 .globl cheetah_fast_ecc 471 .type cheetah_fast_ecc,#function 472cheetah_fast_ecc: 473 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 474 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2 475 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN 476 membar #Sync 477 478 /* Fetch and clear AFSR/AFAR */ 479 ldxa [%g0] ASI_AFSR, %g4 480 ldxa [%g0] ASI_AFAR, %g5 481 stxa %g4, [%g0] ASI_AFSR 482 membar #Sync 483 484 ba,pt %xcc, __cheetah_log_error 485 nop 486 .size cheetah_fast_ecc,.-cheetah_fast_ecc 487 488 .type c_fast_ecc,#function 489c_fast_ecc: 490 rdpr %pil, %g2 491 wrpr %g0, PIL_NORMAL_MAX, %pil 492 ba,pt %xcc, etrap_irq 493 rd %pc, %g7 494#ifdef CONFIG_TRACE_IRQFLAGS 495 call trace_hardirqs_off 496 nop 497#endif 498 mov %l4, %o1 499 mov %l5, %o2 500 call cheetah_fecc_handler 501 add %sp, PTREGS_OFF, %o0 502 ba,a,pt %xcc, rtrap_irq 503 .size c_fast_ecc,.-c_fast_ecc 504 505 /* Our caller has disabled I-cache and performed membar Sync. */ 506 .globl cheetah_cee 507 .type cheetah_cee,#function 508cheetah_cee: 509 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 510 andn %g2, ESTATE_ERROR_CEEN, %g2 511 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN 512 membar #Sync 513 514 /* Fetch and clear AFSR/AFAR */ 515 ldxa [%g0] ASI_AFSR, %g4 516 ldxa [%g0] ASI_AFAR, %g5 517 stxa %g4, [%g0] ASI_AFSR 518 membar #Sync 519 520 ba,pt %xcc, __cheetah_log_error 521 nop 522 .size cheetah_cee,.-cheetah_cee 523 524 .type c_cee,#function 525c_cee: 526 rdpr %pil, %g2 527 wrpr %g0, PIL_NORMAL_MAX, %pil 528 ba,pt %xcc, etrap_irq 529 rd %pc, %g7 530#ifdef CONFIG_TRACE_IRQFLAGS 531 call trace_hardirqs_off 532 nop 533#endif 534 mov %l4, %o1 535 mov %l5, %o2 536 call cheetah_cee_handler 537 add %sp, PTREGS_OFF, %o0 538 ba,a,pt %xcc, rtrap_irq 539 .size c_cee,.-c_cee 540 541 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */ 542 .globl cheetah_deferred_trap 543 .type cheetah_deferred_trap,#function 544cheetah_deferred_trap: 545 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 546 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2 547 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN 548 membar #Sync 549 550 /* Fetch and clear AFSR/AFAR */ 551 ldxa [%g0] ASI_AFSR, %g4 552 ldxa [%g0] ASI_AFAR, %g5 553 stxa %g4, [%g0] ASI_AFSR 554 membar #Sync 555 556 ba,pt %xcc, __cheetah_log_error 557 nop 558 .size cheetah_deferred_trap,.-cheetah_deferred_trap 559 560 .type c_deferred,#function 561c_deferred: 562 rdpr %pil, %g2 563 wrpr %g0, PIL_NORMAL_MAX, %pil 564 ba,pt %xcc, etrap_irq 565 rd %pc, %g7 566#ifdef CONFIG_TRACE_IRQFLAGS 567 call trace_hardirqs_off 568 nop 569#endif 570 mov %l4, %o1 571 mov %l5, %o2 572 call cheetah_deferred_handler 573 add %sp, PTREGS_OFF, %o0 574 ba,a,pt %xcc, rtrap_irq 575 .size c_deferred,.-c_deferred 576