154579826SDavid Howells /*---------------------------------------- 254579826SDavid Howells PERFORMANCE INSTRUMENTATION 354579826SDavid Howells Guillaume Thouvenin 08/10/98 454579826SDavid Howells David S. Miller 10/06/98 554579826SDavid Howells ---------------------------------------*/ 654579826SDavid Howells #ifndef PERF_COUNTER_API 754579826SDavid Howells #define PERF_COUNTER_API 854579826SDavid Howells 954579826SDavid Howells /* sys_perfctr() interface. First arg is operation code 1054579826SDavid Howells * from enumeration below. The meaning of further arguments 1154579826SDavid Howells * are determined by the operation code. 1254579826SDavid Howells * 1354579826SDavid Howells * NOTE: This system call is no longer provided, use the perf_events 1454579826SDavid Howells * infrastructure. 1554579826SDavid Howells * 1654579826SDavid Howells * Pointers which are passed by the user are pointers to 64-bit 1754579826SDavid Howells * integers. 1854579826SDavid Howells * 1954579826SDavid Howells * Once enabled, performance counter state is retained until the 2054579826SDavid Howells * process either exits or performs an exec. That is, performance 2154579826SDavid Howells * counters remain enabled for fork/clone children. 2254579826SDavid Howells */ 2354579826SDavid Howells enum perfctr_opcode { 2454579826SDavid Howells /* Enable UltraSparc performance counters, ARG0 is pointer 2554579826SDavid Howells * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer 2654579826SDavid Howells * to 64-bit accumulator for D1 counter. ARG2 is a pointer to 2754579826SDavid Howells * the initial PCR register value to use. 2854579826SDavid Howells */ 2954579826SDavid Howells PERFCTR_ON, 3054579826SDavid Howells 3154579826SDavid Howells /* Disable UltraSparc performance counters. The PCR is written 3254579826SDavid Howells * with zero and the user counter accumulator pointers and 3354579826SDavid Howells * working PCR register value are forgotten. 3454579826SDavid Howells */ 3554579826SDavid Howells PERFCTR_OFF, 3654579826SDavid Howells 3754579826SDavid Howells /* Add current D0 and D1 PIC values into user pointers given 3854579826SDavid Howells * in PERFCTR_ON operation. The PIC is cleared before returning. 3954579826SDavid Howells */ 4054579826SDavid Howells PERFCTR_READ, 4154579826SDavid Howells 4254579826SDavid Howells /* Clear the PIC register. */ 4354579826SDavid Howells PERFCTR_CLRPIC, 4454579826SDavid Howells 4554579826SDavid Howells /* Begin using a new PCR value, the pointer to which is passed 4654579826SDavid Howells * in ARG0. The PIC is also cleared after the new PCR value is 4754579826SDavid Howells * written. 4854579826SDavid Howells */ 4954579826SDavid Howells PERFCTR_SETPCR, 5054579826SDavid Howells 5154579826SDavid Howells /* Store in pointer given in ARG0 the current PCR register value 5254579826SDavid Howells * being used. 5354579826SDavid Howells */ 5454579826SDavid Howells PERFCTR_GETPCR 5554579826SDavid Howells }; 5654579826SDavid Howells 5754579826SDavid Howells #define PRIV 0x00000001 5854579826SDavid Howells #define SYS 0x00000002 5954579826SDavid Howells #define USR 0x00000004 6054579826SDavid Howells 6154579826SDavid Howells /* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */ 6254579826SDavid Howells #define CYCLE_CNT 0x00000000 6354579826SDavid Howells #define INSTR_CNT 0x00000010 6454579826SDavid Howells #define DISPATCH0_IC_MISS 0x00000020 6554579826SDavid Howells #define DISPATCH0_STOREBUF 0x00000030 6654579826SDavid Howells #define IC_REF 0x00000080 6754579826SDavid Howells #define DC_RD 0x00000090 6854579826SDavid Howells #define DC_WR 0x000000A0 6954579826SDavid Howells #define LOAD_USE 0x000000B0 7054579826SDavid Howells #define EC_REF 0x000000C0 7154579826SDavid Howells #define EC_WRITE_HIT_RDO 0x000000D0 7254579826SDavid Howells #define EC_SNOOP_INV 0x000000E0 7354579826SDavid Howells #define EC_RD_HIT 0x000000F0 7454579826SDavid Howells 7554579826SDavid Howells /* Pic.S0 Selection Bit Field Encoding, Ultra-III */ 7654579826SDavid Howells #define US3_CYCLE_CNT 0x00000000 7754579826SDavid Howells #define US3_INSTR_CNT 0x00000010 7854579826SDavid Howells #define US3_DISPATCH0_IC_MISS 0x00000020 7954579826SDavid Howells #define US3_DISPATCH0_BR_TGT 0x00000030 8054579826SDavid Howells #define US3_DISPATCH0_2ND_BR 0x00000040 8154579826SDavid Howells #define US3_RSTALL_STOREQ 0x00000050 8254579826SDavid Howells #define US3_RSTALL_IU_USE 0x00000060 8354579826SDavid Howells #define US3_IC_REF 0x00000080 8454579826SDavid Howells #define US3_DC_RD 0x00000090 8554579826SDavid Howells #define US3_DC_WR 0x000000a0 8654579826SDavid Howells #define US3_EC_REF 0x000000c0 8754579826SDavid Howells #define US3_EC_WR_HIT_RTO 0x000000d0 8854579826SDavid Howells #define US3_EC_SNOOP_INV 0x000000e0 8954579826SDavid Howells #define US3_EC_RD_MISS 0x000000f0 9054579826SDavid Howells #define US3_PC_PORT0_RD 0x00000100 9154579826SDavid Howells #define US3_SI_SNOOP 0x00000110 9254579826SDavid Howells #define US3_SI_CIQ_FLOW 0x00000120 9354579826SDavid Howells #define US3_SI_OWNED 0x00000130 9454579826SDavid Howells #define US3_SW_COUNT_0 0x00000140 9554579826SDavid Howells #define US3_IU_BR_MISS_TAKEN 0x00000150 9654579826SDavid Howells #define US3_IU_BR_COUNT_TAKEN 0x00000160 9754579826SDavid Howells #define US3_DISP_RS_MISPRED 0x00000170 9854579826SDavid Howells #define US3_FA_PIPE_COMPL 0x00000180 9954579826SDavid Howells #define US3_MC_READS_0 0x00000200 10054579826SDavid Howells #define US3_MC_READS_1 0x00000210 10154579826SDavid Howells #define US3_MC_READS_2 0x00000220 10254579826SDavid Howells #define US3_MC_READS_3 0x00000230 10354579826SDavid Howells #define US3_MC_STALLS_0 0x00000240 10454579826SDavid Howells #define US3_MC_STALLS_2 0x00000250 10554579826SDavid Howells 10654579826SDavid Howells /* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */ 10754579826SDavid Howells #define CYCLE_CNT_D1 0x00000000 10854579826SDavid Howells #define INSTR_CNT_D1 0x00000800 10954579826SDavid Howells #define DISPATCH0_IC_MISPRED 0x00001000 11054579826SDavid Howells #define DISPATCH0_FP_USE 0x00001800 11154579826SDavid Howells #define IC_HIT 0x00004000 11254579826SDavid Howells #define DC_RD_HIT 0x00004800 11354579826SDavid Howells #define DC_WR_HIT 0x00005000 11454579826SDavid Howells #define LOAD_USE_RAW 0x00005800 11554579826SDavid Howells #define EC_HIT 0x00006000 11654579826SDavid Howells #define EC_WB 0x00006800 11754579826SDavid Howells #define EC_SNOOP_CB 0x00007000 11854579826SDavid Howells #define EC_IT_HIT 0x00007800 11954579826SDavid Howells 12054579826SDavid Howells /* Pic.S1 Selection Bit Field Encoding, Ultra-III */ 12154579826SDavid Howells #define US3_CYCLE_CNT_D1 0x00000000 12254579826SDavid Howells #define US3_INSTR_CNT_D1 0x00000800 12354579826SDavid Howells #define US3_DISPATCH0_MISPRED 0x00001000 12454579826SDavid Howells #define US3_IC_MISS_CANCELLED 0x00001800 12554579826SDavid Howells #define US3_RE_ENDIAN_MISS 0x00002000 12654579826SDavid Howells #define US3_RE_FPU_BYPASS 0x00002800 12754579826SDavid Howells #define US3_RE_DC_MISS 0x00003000 12854579826SDavid Howells #define US3_RE_EC_MISS 0x00003800 12954579826SDavid Howells #define US3_IC_MISS 0x00004000 13054579826SDavid Howells #define US3_DC_RD_MISS 0x00004800 13154579826SDavid Howells #define US3_DC_WR_MISS 0x00005000 13254579826SDavid Howells #define US3_RSTALL_FP_USE 0x00005800 13354579826SDavid Howells #define US3_EC_MISSES 0x00006000 13454579826SDavid Howells #define US3_EC_WB 0x00006800 13554579826SDavid Howells #define US3_EC_SNOOP_CB 0x00007000 13654579826SDavid Howells #define US3_EC_IC_MISS 0x00007800 13754579826SDavid Howells #define US3_RE_PC_MISS 0x00008000 13854579826SDavid Howells #define US3_ITLB_MISS 0x00008800 13954579826SDavid Howells #define US3_DTLB_MISS 0x00009000 14054579826SDavid Howells #define US3_WC_MISS 0x00009800 14154579826SDavid Howells #define US3_WC_SNOOP_CB 0x0000a000 14254579826SDavid Howells #define US3_WC_SCRUBBED 0x0000a800 14354579826SDavid Howells #define US3_WC_WB_WO_READ 0x0000b000 14454579826SDavid Howells #define US3_PC_SOFT_HIT 0x0000c000 14554579826SDavid Howells #define US3_PC_SNOOP_INV 0x0000c800 14654579826SDavid Howells #define US3_PC_HARD_HIT 0x0000d000 14754579826SDavid Howells #define US3_PC_PORT1_RD 0x0000d800 14854579826SDavid Howells #define US3_SW_COUNT_1 0x0000e000 14954579826SDavid Howells #define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800 15054579826SDavid Howells #define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000 15154579826SDavid Howells #define US3_PC_MS_MISSES 0x0000f800 15254579826SDavid Howells #define US3_MC_WRITES_0 0x00010800 15354579826SDavid Howells #define US3_MC_WRITES_1 0x00011000 15454579826SDavid Howells #define US3_MC_WRITES_2 0x00011800 15554579826SDavid Howells #define US3_MC_WRITES_3 0x00012000 15654579826SDavid Howells #define US3_MC_STALLS_1 0x00012800 15754579826SDavid Howells #define US3_MC_STALLS_3 0x00013000 15854579826SDavid Howells #define US3_RE_RAW_MISS 0x00013800 15954579826SDavid Howells #define US3_FM_PIPE_COMPLETION 0x00014000 16054579826SDavid Howells 16154579826SDavid Howells struct vcounter_struct { 16254579826SDavid Howells unsigned long long vcnt0; 16354579826SDavid Howells unsigned long long vcnt1; 16454579826SDavid Howells }; 16554579826SDavid Howells 16654579826SDavid Howells #endif /* !(PERF_COUNTER_API) */ 167