1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg /* 3a439fe51SSam Ravnborg * winmacro.h: Window loading-unloading macros. 4a439fe51SSam Ravnborg * 5a439fe51SSam Ravnborg * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 6a439fe51SSam Ravnborg */ 7a439fe51SSam Ravnborg 8a439fe51SSam Ravnborg #ifndef _SPARC_WINMACRO_H 9a439fe51SSam Ravnborg #define _SPARC_WINMACRO_H 10a439fe51SSam Ravnborg 11a439fe51SSam Ravnborg #include <asm/ptrace.h> 12a439fe51SSam Ravnborg 13a439fe51SSam Ravnborg /* Store the register window onto the 8-byte aligned area starting 14a439fe51SSam Ravnborg * at %reg. It might be %sp, it might not, we don't care. 15a439fe51SSam Ravnborg */ 16a439fe51SSam Ravnborg #define STORE_WINDOW(reg) \ 17a439fe51SSam Ravnborg std %l0, [%reg + RW_L0]; \ 18a439fe51SSam Ravnborg std %l2, [%reg + RW_L2]; \ 19a439fe51SSam Ravnborg std %l4, [%reg + RW_L4]; \ 20a439fe51SSam Ravnborg std %l6, [%reg + RW_L6]; \ 21a439fe51SSam Ravnborg std %i0, [%reg + RW_I0]; \ 22a439fe51SSam Ravnborg std %i2, [%reg + RW_I2]; \ 23a439fe51SSam Ravnborg std %i4, [%reg + RW_I4]; \ 24a439fe51SSam Ravnborg std %i6, [%reg + RW_I6]; 25a439fe51SSam Ravnborg 26a439fe51SSam Ravnborg /* Load a register window from the area beginning at %reg. */ 27a439fe51SSam Ravnborg #define LOAD_WINDOW(reg) \ 28a439fe51SSam Ravnborg ldd [%reg + RW_L0], %l0; \ 29a439fe51SSam Ravnborg ldd [%reg + RW_L2], %l2; \ 30a439fe51SSam Ravnborg ldd [%reg + RW_L4], %l4; \ 31a439fe51SSam Ravnborg ldd [%reg + RW_L6], %l6; \ 32a439fe51SSam Ravnborg ldd [%reg + RW_I0], %i0; \ 33a439fe51SSam Ravnborg ldd [%reg + RW_I2], %i2; \ 34a439fe51SSam Ravnborg ldd [%reg + RW_I4], %i4; \ 35a439fe51SSam Ravnborg ldd [%reg + RW_I6], %i6; 36a439fe51SSam Ravnborg 37a439fe51SSam Ravnborg /* Loading and storing struct pt_reg trap frames. */ 38a439fe51SSam Ravnborg #define LOAD_PT_INS(base_reg) \ 39a439fe51SSam Ravnborg ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \ 40a439fe51SSam Ravnborg ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \ 41a439fe51SSam Ravnborg ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \ 42a439fe51SSam Ravnborg ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6; 43a439fe51SSam Ravnborg 44a439fe51SSam Ravnborg #define LOAD_PT_GLOBALS(base_reg) \ 45a439fe51SSam Ravnborg ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \ 46a439fe51SSam Ravnborg ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \ 47a439fe51SSam Ravnborg ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \ 48a439fe51SSam Ravnborg ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6; 49a439fe51SSam Ravnborg 50a439fe51SSam Ravnborg #define LOAD_PT_YREG(base_reg, scratch) \ 51a439fe51SSam Ravnborg ld [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \ 52a439fe51SSam Ravnborg wr %scratch, 0x0, %y; 53a439fe51SSam Ravnborg 54a439fe51SSam Ravnborg #define LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \ 55a439fe51SSam Ravnborg ld [%base_reg + STACKFRAME_SZ + PT_PSR], %pt_psr; \ 56a439fe51SSam Ravnborg ld [%base_reg + STACKFRAME_SZ + PT_PC], %pt_pc; \ 57a439fe51SSam Ravnborg ld [%base_reg + STACKFRAME_SZ + PT_NPC], %pt_npc; 58a439fe51SSam Ravnborg 59a439fe51SSam Ravnborg #define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \ 60a439fe51SSam Ravnborg LOAD_PT_YREG(base_reg, scratch) \ 61a439fe51SSam Ravnborg LOAD_PT_INS(base_reg) \ 62a439fe51SSam Ravnborg LOAD_PT_GLOBALS(base_reg) \ 63a439fe51SSam Ravnborg LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) 64a439fe51SSam Ravnborg 65a439fe51SSam Ravnborg #define STORE_PT_INS(base_reg) \ 66a439fe51SSam Ravnborg std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \ 67a439fe51SSam Ravnborg std %i2, [%base_reg + STACKFRAME_SZ + PT_I2]; \ 68a439fe51SSam Ravnborg std %i4, [%base_reg + STACKFRAME_SZ + PT_I4]; \ 69a439fe51SSam Ravnborg std %i6, [%base_reg + STACKFRAME_SZ + PT_I6]; 70a439fe51SSam Ravnborg 71a439fe51SSam Ravnborg #define STORE_PT_GLOBALS(base_reg) \ 72a439fe51SSam Ravnborg st %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \ 73a439fe51SSam Ravnborg std %g2, [%base_reg + STACKFRAME_SZ + PT_G2]; \ 74a439fe51SSam Ravnborg std %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \ 75a439fe51SSam Ravnborg std %g6, [%base_reg + STACKFRAME_SZ + PT_G6]; 76a439fe51SSam Ravnborg 77a439fe51SSam Ravnborg #define STORE_PT_YREG(base_reg, scratch) \ 78a439fe51SSam Ravnborg rd %y, %scratch; \ 79a439fe51SSam Ravnborg st %scratch, [%base_reg + STACKFRAME_SZ + PT_Y]; 80a439fe51SSam Ravnborg 81a439fe51SSam Ravnborg #define STORE_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \ 82a439fe51SSam Ravnborg st %pt_psr, [%base_reg + STACKFRAME_SZ + PT_PSR]; \ 83a439fe51SSam Ravnborg st %pt_pc, [%base_reg + STACKFRAME_SZ + PT_PC]; \ 84a439fe51SSam Ravnborg st %pt_npc, [%base_reg + STACKFRAME_SZ + PT_NPC]; 85a439fe51SSam Ravnborg 86a439fe51SSam Ravnborg #define STORE_PT_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \ 87a439fe51SSam Ravnborg STORE_PT_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \ 88a439fe51SSam Ravnborg STORE_PT_GLOBALS(base_reg) \ 89a439fe51SSam Ravnborg STORE_PT_YREG(base_reg, g_scratch) \ 90a439fe51SSam Ravnborg STORE_PT_INS(base_reg) 91a439fe51SSam Ravnborg 92a439fe51SSam Ravnborg #define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \ 93a439fe51SSam Ravnborg ld [%cur_reg + TI_W_SAVED], %scratch; \ 94a439fe51SSam Ravnborg sll %scratch, 2, %scratch; \ 95a439fe51SSam Ravnborg add %scratch, %cur_reg, %scratch; \ 96a439fe51SSam Ravnborg st %sp, [%scratch + TI_RWIN_SPTRS]; \ 97a439fe51SSam Ravnborg sub %scratch, %cur_reg, %scratch; \ 98a439fe51SSam Ravnborg sll %scratch, 4, %scratch; \ 99a439fe51SSam Ravnborg add %scratch, %cur_reg, %scratch; \ 100a439fe51SSam Ravnborg STORE_WINDOW(scratch + TI_REG_WINDOW); \ 101a439fe51SSam Ravnborg sub %scratch, %cur_reg, %scratch; \ 102a439fe51SSam Ravnborg srl %scratch, 6, %scratch; \ 103a439fe51SSam Ravnborg add %scratch, 1, %scratch; \ 104a439fe51SSam Ravnborg st %scratch, [%cur_reg + TI_W_SAVED]; 105a439fe51SSam Ravnborg 106a439fe51SSam Ravnborg #ifdef CONFIG_SMP 107a439fe51SSam Ravnborg #define LOAD_CURRENT(dest_reg, idreg) \ 108c68e5d39SDavid S. Miller 661: rd %tbr, %idreg; \ 109c68e5d39SDavid S. Miller srl %idreg, 10, %idreg; \ 110c68e5d39SDavid S. Miller and %idreg, 0xc, %idreg; \ 111c68e5d39SDavid S. Miller .section .cpuid_patch, "ax"; \ 112c68e5d39SDavid S. Miller /* Instruction location. */ \ 113c68e5d39SDavid S. Miller .word 661b; \ 114c68e5d39SDavid S. Miller /* SUN4D implementation. */ \ 115c68e5d39SDavid S. Miller lda [%g0] ASI_M_VIKING_TMP1, %idreg; \ 116c68e5d39SDavid S. Miller sll %idreg, 2, %idreg; \ 117c68e5d39SDavid S. Miller nop; \ 118c68e5d39SDavid S. Miller /* LEON implementation. */ \ 119c68e5d39SDavid S. Miller rd %asr17, %idreg; \ 120c68e5d39SDavid S. Miller srl %idreg, 0x1c, %idreg; \ 121c68e5d39SDavid S. Miller sll %idreg, 0x02, %idreg; \ 122c68e5d39SDavid S. Miller .previous; \ 123a439fe51SSam Ravnborg sethi %hi(current_set), %dest_reg; \ 124a439fe51SSam Ravnborg or %dest_reg, %lo(current_set), %dest_reg;\ 125a439fe51SSam Ravnborg ld [%idreg + %dest_reg], %dest_reg; 126a439fe51SSam Ravnborg #else 127a439fe51SSam Ravnborg #define LOAD_CURRENT(dest_reg, idreg) \ 128a439fe51SSam Ravnborg sethi %hi(current_set), %idreg; \ 129a439fe51SSam Ravnborg ld [%idreg + %lo(current_set)], %dest_reg; 130a439fe51SSam Ravnborg #endif 131a439fe51SSam Ravnborg 132a439fe51SSam Ravnborg #endif /* !(_SPARC_WINMACRO_H) */ 133