1 /* 2 * turbosparc.h: Defines specific to the TurboSparc module. 3 * This is SRMMU stuff. 4 * 5 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 #ifndef _SPARC_TURBOSPARC_H 8 #define _SPARC_TURBOSPARC_H 9 10 #include <asm/asi.h> 11 #include <asm/pgtsrmmu.h> 12 13 /* Bits in the SRMMU control register for TurboSparc modules. 14 * 15 * ------------------------------------------------------------------- 16 * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME| 17 * ------------------------------------------------------------------- 18 * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0 19 * 20 * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode 21 * 22 * This indicates whether the TurboSparc is in boot-mode or not. 23 * 24 * IC: Instruction Cache -- 0 = off, 1 = on 25 * DC: Data Cache -- 0 = off, 1 = 0n 26 * 27 * These bits enable the on-cpu TurboSparc split I/D caches. 28 * 29 * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache 30 * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap 31 * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating 32 * 33 */ 34 35 #define TURBOSPARC_MMUENABLE 0x00000001 36 #define TURBOSPARC_NOFAULT 0x00000002 37 #define TURBOSPARC_ICSNOOP 0x00000004 38 #define TURBOSPARC_PSO 0x00000080 39 #define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */ 40 #define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */ 41 #define TURBOSPARC_BMODE 0x00004000 42 #define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */ 43 #define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */ 44 45 /* Bits in the CPU configuration register for TurboSparc modules. 46 * 47 * ------------------------------------------------------- 48 * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC| 49 * ------------------------------------------------------- 50 * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0 51 * 52 */ 53 54 #define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */ 55 #define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */ 56 #define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */ 57 #define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */ 58 59 #ifndef __ASSEMBLY__ 60 61 /* Bits [13:5] select one of 512 instruction cache tags */ 62 static inline void turbosparc_inv_insn_tag(unsigned long addr) 63 { 64 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" 65 : /* no outputs */ 66 : "r" (addr), "i" (ASI_M_TXTC_TAG) 67 : "memory"); 68 } 69 70 /* Bits [13:5] select one of 512 data cache tags */ 71 static inline void turbosparc_inv_data_tag(unsigned long addr) 72 { 73 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" 74 : /* no outputs */ 75 : "r" (addr), "i" (ASI_M_DATAC_TAG) 76 : "memory"); 77 } 78 79 static inline void turbosparc_flush_icache(void) 80 { 81 unsigned long addr; 82 83 for (addr = 0; addr < 0x4000; addr += 0x20) 84 turbosparc_inv_insn_tag(addr); 85 } 86 87 static inline void turbosparc_flush_dcache(void) 88 { 89 unsigned long addr; 90 91 for (addr = 0; addr < 0x4000; addr += 0x20) 92 turbosparc_inv_data_tag(addr); 93 } 94 95 static inline void turbosparc_idflash_clear(void) 96 { 97 unsigned long addr; 98 99 for (addr = 0; addr < 0x4000; addr += 0x20) { 100 turbosparc_inv_insn_tag(addr); 101 turbosparc_inv_data_tag(addr); 102 } 103 } 104 105 static inline void turbosparc_set_ccreg(unsigned long regval) 106 { 107 __asm__ __volatile__("sta %0, [%1] %2\n\t" 108 : /* no outputs */ 109 : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS) 110 : "memory"); 111 } 112 113 static inline unsigned long turbosparc_get_ccreg(void) 114 { 115 unsigned long regval; 116 117 __asm__ __volatile__("lda [%1] %2, %0\n\t" 118 : "=r" (regval) 119 : "r" (0x600), "i" (ASI_M_MMUREGS)); 120 return regval; 121 } 122 123 #endif /* !__ASSEMBLY__ */ 124 125 #endif /* !(_SPARC_TURBOSPARC_H) */ 126