1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * turbosparc.h:  Defines specific to the TurboSparc module.
4  *            This is SRMMU stuff.
5  *
6  * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7  */
8 #ifndef _SPARC_TURBOSPARC_H
9 #define _SPARC_TURBOSPARC_H
10 
11 #include <asm/asi.h>
12 #include <asm/pgtsrmmu.h>
13 
14 /* Bits in the SRMMU control register for TurboSparc modules.
15  *
16  * -------------------------------------------------------------------
17  * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
18  * -------------------------------------------------------------------
19  *  31    24 23-21 20-19 18 17 16-15 14 13-10  9  8  7  6-3   2  1  0
20  *
21  * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
22  *
23  * This indicates whether the TurboSparc is in boot-mode or not.
24  *
25  * IC: Instruction Cache -- 0 = off, 1 = on
26  * DC: Data Cache -- 0 = off, 1 = 0n
27  *
28  * These bits enable the on-cpu TurboSparc split I/D caches.
29  *
30  * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
31  * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
32  * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
33  *
34  */
35 
36 #define TURBOSPARC_MMUENABLE    0x00000001
37 #define TURBOSPARC_NOFAULT      0x00000002
38 #define TURBOSPARC_ICSNOOP	0x00000004
39 #define TURBOSPARC_PSO          0x00000080
40 #define TURBOSPARC_DCENABLE     0x00000100   /* Enable data cache */
41 #define TURBOSPARC_ICENABLE     0x00000200   /* Enable instruction cache */
42 #define TURBOSPARC_BMODE        0x00004000
43 #define TURBOSPARC_PARITYODD	0x00020000   /* Parity odd, if enabled */
44 #define TURBOSPARC_PCENABLE	0x00040000   /* Enable parity checking */
45 
46 /* Bits in the CPU configuration register for TurboSparc modules.
47  *
48  * -------------------------------------------------------
49  * |IOClk|SNP|AXClk| RAH |  WS |  RSV  |SBC|WT|uS2|SE|SCC|
50  * -------------------------------------------------------
51  *    31   30 29-28 27-26 25-23   22-8  7-6  5  4   3 2-0
52  *
53  */
54 
55 #define TURBOSPARC_SCENABLE 0x00000008	 /* Secondary cache enable */
56 #define TURBOSPARC_uS2	    0x00000010   /* Swift compatibility mode */
57 #define TURBOSPARC_WTENABLE 0x00000020	 /* Write thru for dcache */
58 #define TURBOSPARC_SNENABLE 0x40000000	 /* DVMA snoop enable */
59 
60 #ifndef __ASSEMBLY__
61 
62 /* Bits [13:5] select one of 512 instruction cache tags */
63 static inline void turbosparc_inv_insn_tag(unsigned long addr)
64 {
65         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
66 			     : /* no outputs */
67 			     : "r" (addr), "i" (ASI_M_TXTC_TAG)
68 			     : "memory");
69 }
70 
71 /* Bits [13:5] select one of 512 data cache tags */
72 static inline void turbosparc_inv_data_tag(unsigned long addr)
73 {
74         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
75 			     : /* no outputs */
76 			     : "r" (addr), "i" (ASI_M_DATAC_TAG)
77 			     : "memory");
78 }
79 
80 static inline void turbosparc_flush_icache(void)
81 {
82 	unsigned long addr;
83 
84         for (addr = 0; addr < 0x4000; addr += 0x20)
85                 turbosparc_inv_insn_tag(addr);
86 }
87 
88 static inline void turbosparc_flush_dcache(void)
89 {
90 	unsigned long addr;
91 
92         for (addr = 0; addr < 0x4000; addr += 0x20)
93                 turbosparc_inv_data_tag(addr);
94 }
95 
96 static inline void turbosparc_idflash_clear(void)
97 {
98 	unsigned long addr;
99 
100         for (addr = 0; addr < 0x4000; addr += 0x20) {
101                 turbosparc_inv_insn_tag(addr);
102                 turbosparc_inv_data_tag(addr);
103 	}
104 }
105 
106 static inline void turbosparc_set_ccreg(unsigned long regval)
107 {
108 	__asm__ __volatile__("sta %0, [%1] %2\n\t"
109 			     : /* no outputs */
110 			     : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
111 			     : "memory");
112 }
113 
114 static inline unsigned long turbosparc_get_ccreg(void)
115 {
116 	unsigned long regval;
117 
118 	__asm__ __volatile__("lda [%1] %2, %0\n\t"
119 			     : "=r" (regval)
120 			     : "r" (0x600), "i" (ASI_M_MMUREGS));
121 	return regval;
122 }
123 
124 #endif /* !__ASSEMBLY__ */
125 
126 #endif /* !(_SPARC_TURBOSPARC_H) */
127