1 #ifndef _SPARC64_TSB_H 2 #define _SPARC64_TSB_H 3 4 /* The sparc64 TSB is similar to the powerpc hashtables. It's a 5 * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes 6 * pointers into this table for 8K and 64K page sizes, and also a 7 * comparison TAG based upon the virtual address and context which 8 * faults. 9 * 10 * TLB miss trap handler software does the actual lookup via something 11 * of the form: 12 * 13 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1 14 * ldxa [%g0] ASI_{D,I}MMU, %g6 15 * sllx %g6, 22, %g6 16 * srlx %g6, 22, %g6 17 * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4 18 * cmp %g4, %g6 19 * bne,pn %xcc, tsb_miss_{d,i}tlb 20 * mov FAULT_CODE_{D,I}TLB, %g3 21 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN 22 * retry 23 * 24 * 25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte 26 * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu 27 * register which is: 28 * 29 * ------------------------------------------------- 30 * | - | CONTEXT | - | VADDR bits 63:22 | 31 * ------------------------------------------------- 32 * 63 61 60 48 47 42 41 0 33 * 34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT 35 * field. 36 * 37 * Like the powerpc hashtables we need to use locking in order to 38 * synchronize while we update the entries. PTE updates need locking 39 * as well. 40 * 41 * We need to carefully choose a lock bits for the TSB entry. We 42 * choose to use bit 47 in the tag. Also, since we never map anything 43 * at page zero in context zero, we use zero as an invalid tag entry. 44 * When the lock bit is set, this forces a tag comparison failure. 45 */ 46 47 #define TSB_TAG_LOCK_BIT 47 48 #define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32)) 49 50 #define TSB_TAG_INVALID_BIT 46 51 #define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32)) 52 53 /* Some cpus support physical address quad loads. We want to use 54 * those if possible so we don't need to hard-lock the TSB mapping 55 * into the TLB. We encode some instruction patching in order to 56 * support this. 57 * 58 * The kernel TSB is locked into the TLB by virtue of being in the 59 * kernel image, so we don't play these games for swapper_tsb access. 60 */ 61 #ifndef __ASSEMBLY__ 62 struct tsb_ldquad_phys_patch_entry { 63 unsigned int addr; 64 unsigned int sun4u_insn; 65 unsigned int sun4v_insn; 66 }; 67 extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch, 68 __tsb_ldquad_phys_patch_end; 69 70 struct tsb_phys_patch_entry { 71 unsigned int addr; 72 unsigned int insn; 73 }; 74 extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; 75 #endif 76 #define TSB_LOAD_QUAD(TSB, REG) \ 77 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \ 78 .section .tsb_ldquad_phys_patch, "ax"; \ 79 .word 661b; \ 80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \ 81 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \ 82 .previous 83 84 #define TSB_LOAD_TAG_HIGH(TSB, REG) \ 85 661: lduwa [TSB] ASI_N, REG; \ 86 .section .tsb_phys_patch, "ax"; \ 87 .word 661b; \ 88 lduwa [TSB] ASI_PHYS_USE_EC, REG; \ 89 .previous 90 91 #define TSB_LOAD_TAG(TSB, REG) \ 92 661: ldxa [TSB] ASI_N, REG; \ 93 .section .tsb_phys_patch, "ax"; \ 94 .word 661b; \ 95 ldxa [TSB] ASI_PHYS_USE_EC, REG; \ 96 .previous 97 98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \ 99 661: casa [TSB] ASI_N, REG1, REG2; \ 100 .section .tsb_phys_patch, "ax"; \ 101 .word 661b; \ 102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \ 103 .previous 104 105 #define TSB_CAS_TAG(TSB, REG1, REG2) \ 106 661: casxa [TSB] ASI_N, REG1, REG2; \ 107 .section .tsb_phys_patch, "ax"; \ 108 .word 661b; \ 109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \ 110 .previous 111 112 #define TSB_STORE(ADDR, VAL) \ 113 661: stxa VAL, [ADDR] ASI_N; \ 114 .section .tsb_phys_patch, "ax"; \ 115 .word 661b; \ 116 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \ 117 .previous 118 119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \ 120 99: TSB_LOAD_TAG_HIGH(TSB, REG1); \ 121 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\ 122 andcc REG1, REG2, %g0; \ 123 bne,pn %icc, 99b; \ 124 nop; \ 125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \ 126 cmp REG1, REG2; \ 127 bne,pn %icc, 99b; \ 128 nop; \ 129 130 #define TSB_WRITE(TSB, TTE, TAG) \ 131 add TSB, 0x8, TSB; \ 132 TSB_STORE(TSB, TTE); \ 133 sub TSB, 0x8, TSB; \ 134 TSB_STORE(TSB, TAG); 135 136 /* Do a kernel page table walk. Leaves physical PTE pointer in 137 * REG1. Jumps to FAIL_LABEL on early page table walk termination. 138 * VADDR will not be clobbered, but REG2 will. 139 */ 140 #define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \ 141 sethi %hi(swapper_pg_dir), REG1; \ 142 or REG1, %lo(swapper_pg_dir), REG1; \ 143 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \ 144 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 145 andn REG2, 0x7, REG2; \ 146 ldx [REG1 + REG2], REG1; \ 147 brz,pn REG1, FAIL_LABEL; \ 148 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \ 149 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 150 andn REG2, 0x7, REG2; \ 151 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \ 152 brz,pn REG1, FAIL_LABEL; \ 153 sllx VADDR, 64 - PMD_SHIFT, REG2; \ 154 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 155 andn REG2, 0x7, REG2; \ 156 add REG1, REG2, REG1; 157 158 /* PMD has been loaded into REG1, interpret the value, seeing 159 * if it is a HUGE PMD or a normal one. If it is not valid 160 * then jump to FAIL_LABEL. If it is a HUGE PMD, and it 161 * translates to a valid PTE, branch to PTE_LABEL. 162 * 163 * We have to propagate the 4MB bit of the virtual address 164 * because we are fabricating 8MB pages using 4MB hw pages. 165 */ 166 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 167 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \ 168 brz,pn REG1, FAIL_LABEL; \ 169 sethi %uhi(_PAGE_PMD_HUGE), REG2; \ 170 sllx REG2, 32, REG2; \ 171 andcc REG1, REG2, %g0; \ 172 be,pt %xcc, 700f; \ 173 sethi %hi(4 * 1024 * 1024), REG2; \ 174 andn REG1, REG2, REG1; \ 175 and VADDR, REG2, REG2; \ 176 brlz,pt REG1, PTE_LABEL; \ 177 or REG1, REG2, REG1; \ 178 700: 179 #else 180 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \ 181 brz,pn REG1, FAIL_LABEL; \ 182 nop; 183 #endif 184 185 /* Do a user page table walk in MMU globals. Leaves final, 186 * valid, PTE value in REG1. Jumps to FAIL_LABEL on early 187 * page table walk termination or if the PTE is not valid. 188 * 189 * Physical base of page tables is in PHYS_PGD which will not 190 * be modified. 191 * 192 * VADDR will not be clobbered, but REG1 and REG2 will. 193 */ 194 #define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \ 195 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \ 196 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 197 andn REG2, 0x7, REG2; \ 198 ldxa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \ 199 brz,pn REG1, FAIL_LABEL; \ 200 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \ 201 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 202 andn REG2, 0x7, REG2; \ 203 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \ 204 USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \ 205 sllx VADDR, 64 - PMD_SHIFT, REG2; \ 206 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 207 andn REG2, 0x7, REG2; \ 208 add REG1, REG2, REG1; \ 209 ldxa [REG1] ASI_PHYS_USE_EC, REG1; \ 210 brgez,pn REG1, FAIL_LABEL; \ 211 nop; \ 212 800: 213 214 /* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0. 215 * If no entry is found, FAIL_LABEL will be branched to. On success 216 * the resulting PTE value will be left in REG1. VADDR is preserved 217 * by this routine. 218 */ 219 #define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \ 220 sethi %hi(prom_trans), REG1; \ 221 or REG1, %lo(prom_trans), REG1; \ 222 97: ldx [REG1 + 0x00], REG2; \ 223 brz,pn REG2, FAIL_LABEL; \ 224 nop; \ 225 ldx [REG1 + 0x08], REG3; \ 226 add REG2, REG3, REG3; \ 227 cmp REG2, VADDR; \ 228 bgu,pt %xcc, 98f; \ 229 cmp VADDR, REG3; \ 230 bgeu,pt %xcc, 98f; \ 231 ldx [REG1 + 0x10], REG3; \ 232 sub VADDR, REG2, REG2; \ 233 ba,pt %xcc, 99f; \ 234 add REG3, REG2, REG1; \ 235 98: ba,pt %xcc, 97b; \ 236 add REG1, (3 * 8), REG1; \ 237 99: 238 239 /* We use a 32K TSB for the whole kernel, this allows to 240 * handle about 16MB of modules and vmalloc mappings without 241 * incurring many hash conflicts. 242 */ 243 #define KERNEL_TSB_SIZE_BYTES (32 * 1024) 244 #define KERNEL_TSB_NENTRIES \ 245 (KERNEL_TSB_SIZE_BYTES / 16) 246 #define KERNEL_TSB4M_NENTRIES 4096 247 248 #define KTSB_PHYS_SHIFT 15 249 250 /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL 251 * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries 252 * and the found TTE will be left in REG1. REG3 and REG4 must 253 * be an even/odd pair of registers. 254 * 255 * VADDR and TAG will be preserved and not clobbered by this macro. 256 */ 257 #define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \ 258 661: sethi %hi(swapper_tsb), REG1; \ 259 or REG1, %lo(swapper_tsb), REG1; \ 260 .section .swapper_tsb_phys_patch, "ax"; \ 261 .word 661b; \ 262 .previous; \ 263 661: nop; \ 264 .section .tsb_ldquad_phys_patch, "ax"; \ 265 .word 661b; \ 266 sllx REG1, KTSB_PHYS_SHIFT, REG1; \ 267 sllx REG1, KTSB_PHYS_SHIFT, REG1; \ 268 .previous; \ 269 srlx VADDR, PAGE_SHIFT, REG2; \ 270 and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \ 271 sllx REG2, 4, REG2; \ 272 add REG1, REG2, REG2; \ 273 TSB_LOAD_QUAD(REG2, REG3); \ 274 cmp REG3, TAG; \ 275 be,a,pt %xcc, OK_LABEL; \ 276 mov REG4, REG1; 277 278 #ifndef CONFIG_DEBUG_PAGEALLOC 279 /* This version uses a trick, the TAG is already (VADDR >> 22) so 280 * we can make use of that for the index computation. 281 */ 282 #define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \ 283 661: sethi %hi(swapper_4m_tsb), REG1; \ 284 or REG1, %lo(swapper_4m_tsb), REG1; \ 285 .section .swapper_4m_tsb_phys_patch, "ax"; \ 286 .word 661b; \ 287 .previous; \ 288 661: nop; \ 289 .section .tsb_ldquad_phys_patch, "ax"; \ 290 .word 661b; \ 291 sllx REG1, KTSB_PHYS_SHIFT, REG1; \ 292 sllx REG1, KTSB_PHYS_SHIFT, REG1; \ 293 .previous; \ 294 and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \ 295 sllx REG2, 4, REG2; \ 296 add REG1, REG2, REG2; \ 297 TSB_LOAD_QUAD(REG2, REG3); \ 298 cmp REG3, TAG; \ 299 be,a,pt %xcc, OK_LABEL; \ 300 mov REG4, REG1; 301 #endif 302 303 #endif /* !(_SPARC64_TSB_H) */ 304