1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg /* 3a439fe51SSam Ravnborg * timer.h: Definitions for the timer chips on the Sparc. 4a439fe51SSam Ravnborg * 5a439fe51SSam Ravnborg * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 6a439fe51SSam Ravnborg */ 7a439fe51SSam Ravnborg 8a439fe51SSam Ravnborg 9a439fe51SSam Ravnborg #ifndef _SPARC_TIMER_H 10a439fe51SSam Ravnborg #define _SPARC_TIMER_H 11a439fe51SSam Ravnborg 1262f08283STkhai Kirill #include <linux/clocksource.h> 1362f08283STkhai Kirill #include <linux/irqreturn.h> 1462f08283STkhai Kirill 1562f08283STkhai Kirill #include <asm-generic/percpu.h> 1662f08283STkhai Kirill 17d550bbd4SDavid Howells #include <asm/cpu_type.h> /* For SUN4M_NCPUS */ 18a439fe51SSam Ravnborg 1962f08283STkhai Kirill #define SBUS_CLOCK_RATE 2000000 /* 2MHz */ 2062f08283STkhai Kirill #define TIMER_VALUE_SHIFT 9 2162f08283STkhai Kirill #define TIMER_VALUE_MASK 0x3fffff 2262f08283STkhai Kirill #define TIMER_LIMIT_BIT (1 << 31) /* Bit 31 in Counter-Timer register */ 2362f08283STkhai Kirill 2462f08283STkhai Kirill /* The counter timer register has the value offset by 9 bits. 2562f08283STkhai Kirill * From sun4m manual: 2662f08283STkhai Kirill * When a counter reaches the value in the corresponding limit register, 2762f08283STkhai Kirill * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200). 2862f08283STkhai Kirill * 2962f08283STkhai Kirill * To compensate for this add one to the value. 3062f08283STkhai Kirill */ timer_value(unsigned int value)3162f08283STkhai Kirillstatic inline unsigned int timer_value(unsigned int value) 3262f08283STkhai Kirill { 3362f08283STkhai Kirill return (value + 1) << TIMER_VALUE_SHIFT; 3462f08283STkhai Kirill } 3562f08283STkhai Kirill 36fcea8b27SSam Ravnborg extern volatile u32 __iomem *master_l10_counter; 37a439fe51SSam Ravnborg 38f05a6865SSam Ravnborg irqreturn_t notrace timer_interrupt(int dummy, void *dev_id); 3962f08283STkhai Kirill 4062f08283STkhai Kirill #ifdef CONFIG_SMP 4162f08283STkhai Kirill DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent); 42f05a6865SSam Ravnborg void register_percpu_ce(int cpu); 4362f08283STkhai Kirill #endif 4462f08283STkhai Kirill 45a439fe51SSam Ravnborg #endif /* !(_SPARC_TIMER_H) */ 46