1 #ifndef __SPARC64_SWITCH_TO_64_H
2 #define __SPARC64_SWITCH_TO_64_H
3 
4 #include <asm/visasm.h>
5 
6 #define prepare_arch_switch(next)		\
7 do {						\
8 	flushw_all();				\
9 } while (0)
10 
11 	/* See what happens when you design the chip correctly?
12 	 *
13 	 * We tell gcc we clobber all non-fixed-usage registers except
14 	 * for l0/l1.  It will use one for 'next' and the other to hold
15 	 * the output value of 'last'.  'next' is not referenced again
16 	 * past the invocation of switch_to in the scheduler, so we need
17 	 * not preserve it's value.  Hairy, but it lets us remove 2 loads
18 	 * and 2 stores in this critical code path.  -DaveM
19 	 */
20 #define switch_to(prev, next, last)					\
21 do {	save_and_clear_fpu();						\
22 	/* If you are tempted to conditionalize the following */	\
23 	/* so that ASI is only written if it changes, think again. */	\
24 	__asm__ __volatile__("wr %%g0, %0, %%asi"			\
25 	: : "r" (task_thread_info(next)->current_ds));\
26 	trap_block[current_thread_info()->cpu].thread =			\
27 		task_thread_info(next);					\
28 	__asm__ __volatile__(						\
29 	"mov	%%g4, %%g7\n\t"						\
30 	"stx	%%i6, [%%sp + 2047 + 0x70]\n\t"				\
31 	"stx	%%i7, [%%sp + 2047 + 0x78]\n\t"				\
32 	"rdpr	%%wstate, %%o5\n\t"					\
33 	"stx	%%o6, [%%g6 + %6]\n\t"					\
34 	"stb	%%o5, [%%g6 + %5]\n\t"					\
35 	"rdpr	%%cwp, %%o5\n\t"					\
36 	"stb	%%o5, [%%g6 + %8]\n\t"					\
37 	"wrpr	%%g0, 15, %%pil\n\t"					\
38 	"mov	%4, %%g6\n\t"						\
39 	"ldub	[%4 + %8], %%g1\n\t"					\
40 	"wrpr	%%g1, %%cwp\n\t"					\
41 	"ldx	[%%g6 + %6], %%o6\n\t"					\
42 	"ldub	[%%g6 + %5], %%o5\n\t"					\
43 	"ldub	[%%g6 + %7], %%o7\n\t"					\
44 	"wrpr	%%o5, 0x0, %%wstate\n\t"				\
45 	"ldx	[%%sp + 2047 + 0x70], %%i6\n\t"				\
46 	"ldx	[%%sp + 2047 + 0x78], %%i7\n\t"				\
47 	"ldx	[%%g6 + %9], %%g4\n\t"					\
48 	"wrpr	%%g0, 14, %%pil\n\t"					\
49 	"brz,pt %%o7, switch_to_pc\n\t"					\
50 	" mov	%%g7, %0\n\t"						\
51 	"sethi	%%hi(ret_from_fork), %%g1\n\t"				\
52 	"jmpl	%%g1 + %%lo(ret_from_fork), %%g0\n\t"			\
53 	" nop\n\t"							\
54 	".globl switch_to_pc\n\t"					\
55 	"switch_to_pc:\n\t"						\
56 	: "=&r" (last), "=r" (current), "=r" (current_thread_info_reg),	\
57 	  "=r" (__local_per_cpu_offset)					\
58 	: "0" (task_thread_info(next)),					\
59 	  "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
60 	  "i" (TI_CWP), "i" (TI_TASK)					\
61 	: "cc",								\
62 	        "g1", "g2", "g3",                   "g7",		\
63 	        "l1", "l2", "l3", "l4", "l5", "l6", "l7",		\
64 	  "i0", "i1", "i2", "i3", "i4", "i5",				\
65 	  "o0", "o1", "o2", "o3", "o4", "o5",       "o7");		\
66 } while(0)
67 
68 extern void synchronize_user_stack(void);
69 extern void fault_in_user_windows(void);
70 
71 #endif /* __SPARC64_SWITCH_TO_64_H */
72