1 #ifndef __SPARC_SWITCH_TO_H
2 #define __SPARC_SWITCH_TO_H
3 
4 #include <asm/smp.h>
5 
6 extern struct thread_info *current_set[NR_CPUS];
7 
8 /*
9  * Flush windows so that the VM switch which follows
10  * would not pull the stack from under us.
11  *
12  * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
13  * XXX WTF is the above comment? Found in late teen 2.4.x.
14  */
15 #ifdef CONFIG_SMP
16 #define SWITCH_ENTER(prv) \
17 	do {			\
18 	if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
19 		put_psr(get_psr() | PSR_EF); \
20 		fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
21 		       &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
22 		clear_tsk_thread_flag(prv, TIF_USEDFPU); \
23 		(prv)->thread.kregs->psr &= ~PSR_EF; \
24 	} \
25 	} while(0)
26 
27 #define SWITCH_DO_LAZY_FPU(next)	/* */
28 #else
29 #define SWITCH_ENTER(prv)		/* */
30 #define SWITCH_DO_LAZY_FPU(nxt)	\
31 	do {			\
32 	if (last_task_used_math != (nxt))		\
33 		(nxt)->thread.kregs->psr&=~PSR_EF;	\
34 	} while(0)
35 #endif
36 
37 #define prepare_arch_switch(next) do { \
38 	__asm__ __volatile__( \
39 	".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
40 	"save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
41 	"save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
42 	"save %sp, -0x40, %sp\n\t" \
43 	"restore; restore; restore; restore; restore; restore; restore"); \
44 } while(0)
45 
46 	/* Much care has gone into this code, do not touch it.
47 	 *
48 	 * We need to loadup regs l0/l1 for the newly forked child
49 	 * case because the trap return path relies on those registers
50 	 * holding certain values, gcc is told that they are clobbered.
51 	 * Gcc needs registers for 3 values in and 1 value out, so we
52 	 * clobber every non-fixed-usage register besides l2/l3/o4/o5.  -DaveM
53 	 *
54 	 * Hey Dave, that do not touch sign is too much of an incentive
55 	 * - Anton & Pete
56 	 */
57 #define switch_to(prev, next, last) do {						\
58 	SWITCH_ENTER(prev);								\
59 	SWITCH_DO_LAZY_FPU(next);							\
60 	cpumask_set_cpu(smp_processor_id(), mm_cpumask(next->active_mm));		\
61 	__asm__ __volatile__(								\
62 	"sethi	%%hi(here - 0x8), %%o7\n\t"						\
63 	"mov	%%g6, %%g3\n\t"								\
64 	"or	%%o7, %%lo(here - 0x8), %%o7\n\t"					\
65 	"rd	%%psr, %%g4\n\t"							\
66 	"std	%%sp, [%%g6 + %4]\n\t"							\
67 	"rd	%%wim, %%g5\n\t"							\
68 	"wr	%%g4, 0x20, %%psr\n\t"							\
69 	"nop\n\t"									\
70 	"std	%%g4, [%%g6 + %3]\n\t"							\
71 	"ldd	[%2 + %3], %%g4\n\t"							\
72 	"mov	%2, %%g6\n\t"								\
73 	".globl	patchme_store_new_current\n"						\
74 "patchme_store_new_current:\n\t"							\
75 	"st	%2, [%1]\n\t"								\
76 	"wr	%%g4, 0x20, %%psr\n\t"							\
77 	"nop\n\t"									\
78 	"nop\n\t"									\
79 	"nop\n\t"	/* LEON needs all 3 nops: load to %sp depends on CWP. */		\
80 	"ldd	[%%g6 + %4], %%sp\n\t"							\
81 	"wr	%%g5, 0x0, %%wim\n\t"							\
82 	"ldd	[%%sp + 0x00], %%l0\n\t"						\
83 	"ldd	[%%sp + 0x38], %%i6\n\t"						\
84 	"wr	%%g4, 0x0, %%psr\n\t"							\
85 	"nop\n\t"									\
86 	"nop\n\t"									\
87 	"jmpl	%%o7 + 0x8, %%g0\n\t"							\
88 	" ld	[%%g3 + %5], %0\n\t"							\
89 	"here:\n"									\
90         : "=&r" (last)									\
91         : "r" (&(current_set[hard_smp_processor_id()])),	\
92 	  "r" (task_thread_info(next)),				\
93 	  "i" (TI_KPSR),					\
94 	  "i" (TI_KSP),						\
95 	  "i" (TI_TASK)						\
96 	:       "g1", "g2", "g3", "g4", "g5",       "g7",	\
97 	  "l0", "l1",       "l3", "l4", "l5", "l6", "l7",	\
98 	  "i0", "i1", "i2", "i3", "i4", "i5",			\
99 	  "o0", "o1", "o2", "o3",                   "o7");	\
100 	} while(0)
101 
102 void fpsave(unsigned long *fpregs, unsigned long *fsr,
103 	    void *fpqueue, unsigned long *fpqdepth);
104 void synchronize_user_stack(void);
105 
106 #endif /* __SPARC_SWITCH_TO_H */
107