1 /* 2 * include/asm/sunbpp.h 3 */ 4 5 #ifndef _ASM_SPARC_SUNBPP_H 6 #define _ASM_SPARC_SUNBPP_H 7 8 struct bpp_regs { 9 /* DMA registers */ 10 __volatile__ __u32 p_csr; /* DMA Control/Status Register */ 11 __volatile__ __u32 p_addr; /* Address Register */ 12 __volatile__ __u32 p_bcnt; /* Byte Count Register */ 13 __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */ 14 /* Parallel Port registers */ 15 __volatile__ __u16 p_hcr; /* Hardware Configuration Register */ 16 __volatile__ __u16 p_ocr; /* Operation Configuration Register */ 17 __volatile__ __u8 p_dr; /* Parallel Data Register */ 18 __volatile__ __u8 p_tcr; /* Transfer Control Register */ 19 __volatile__ __u8 p_or; /* Output Register */ 20 __volatile__ __u8 p_ir; /* Input Register */ 21 __volatile__ __u16 p_icr; /* Interrupt Control Register */ 22 }; 23 24 /* P_HCR. Time is in increments of SBus clock. */ 25 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */ 26 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */ 27 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */ 28 29 /* P_OCR. */ 30 #define P_OCR_MEM_CLR 0x8000 31 #define P_OCR_DATA_SRC 0x4000 /* ) */ 32 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */ 33 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */ 34 #define P_OCR_ACK_DSEL 0x0800 /* ) */ 35 #define P_OCR_EN_DIAG 0x0400 36 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */ 37 #define P_OCR_ACK_OP 0x0100 /* Ack operation */ 38 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */ 39 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */ 40 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */ 41 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */ 42 43 /* P_TCR */ 44 #define P_TCR_DIR 0x08 45 #define P_TCR_BUSY 0x04 46 #define P_TCR_ACK 0x02 47 #define P_TCR_DS 0x01 /* Strobe */ 48 49 /* P_OR */ 50 #define P_OR_V3 0x20 /* ) */ 51 #define P_OR_V2 0x10 /* ) on Zebra only */ 52 #define P_OR_V1 0x08 /* ) */ 53 #define P_OR_INIT 0x04 54 #define P_OR_AFXN 0x02 /* Auto Feed */ 55 #define P_OR_SLCT_IN 0x01 56 57 /* P_IR */ 58 #define P_IR_PE 0x04 59 #define P_IR_SLCT 0x02 60 #define P_IR_ERR 0x01 61 62 /* P_ICR */ 63 #define P_DS_IRQ 0x8000 /* RW1 */ 64 #define P_ACK_IRQ 0x4000 /* RW1 */ 65 #define P_BUSY_IRQ 0x2000 /* RW1 */ 66 #define P_PE_IRQ 0x1000 /* RW1 */ 67 #define P_SLCT_IRQ 0x0800 /* RW1 */ 68 #define P_ERR_IRQ 0x0400 /* RW1 */ 69 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */ 70 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */ 71 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */ 72 #define P_BUSY_IRQ_EN 0x0040 /* RW */ 73 #define P_PE_IRP 0x0020 /* RW 1= rising edge */ 74 #define P_PE_IRQ_EN 0x0010 /* RW */ 75 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */ 76 #define P_SLCT_IRQ_EN 0x0004 /* RW */ 77 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */ 78 #define P_ERR_IRQ_EN 0x0001 /* RW */ 79 80 #endif /* !(_ASM_SPARC_SUNBPP_H) */ 81