1 /* 2 * pgtable.h: SpitFire page table operations. 3 * 4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #ifndef _SPARC64_PGTABLE_H 9 #define _SPARC64_PGTABLE_H 10 11 /* This file contains the functions and defines necessary to modify and use 12 * the SpitFire page tables. 13 */ 14 15 #include <linux/compiler.h> 16 #include <linux/const.h> 17 #include <asm/types.h> 18 #include <asm/spitfire.h> 19 #include <asm/asi.h> 20 #include <asm/page.h> 21 #include <asm/processor.h> 22 23 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 24 * The page copy blockops can use 0x6000000 to 0x8000000. 25 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. 26 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. 27 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 28 * The vmalloc area spans 0x100000000 to 0x200000000. 29 * Since modules need to be in the lowest 32-bits of the address space, 30 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 31 * There is a single static kernel PMD which maps from 0x0 to address 32 * 0x400000000. 33 */ 34 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 35 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) 36 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) 37 #define MODULES_VADDR _AC(0x0000000010000000,UL) 38 #define MODULES_LEN _AC(0x00000000e0000000,UL) 39 #define MODULES_END _AC(0x00000000f0000000,UL) 40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 42 #define VMALLOC_START _AC(0x0000000100000000,UL) 43 #define VMEMMAP_BASE VMALLOC_END 44 45 /* PMD_SHIFT determines the size of the area a second-level page 46 * table can map 47 */ 48 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 49 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 50 #define PMD_MASK (~(PMD_SIZE-1)) 51 #define PMD_BITS (PAGE_SHIFT - 3) 52 53 /* PUD_SHIFT determines the size of the area a third-level page 54 * table can map 55 */ 56 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) 57 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) 58 #define PUD_MASK (~(PUD_SIZE-1)) 59 #define PUD_BITS (PAGE_SHIFT - 3) 60 61 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 62 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) 63 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 64 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 65 #define PGDIR_BITS (PAGE_SHIFT - 3) 66 67 #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) 68 #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support 69 #endif 70 71 #if (PGDIR_SHIFT + PGDIR_BITS) != 53 72 #error Page table parameters do not cover virtual address space properly. 73 #endif 74 75 #if (PMD_SHIFT != HPAGE_SHIFT) 76 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 77 #endif 78 79 #ifndef __ASSEMBLY__ 80 81 extern unsigned long VMALLOC_END; 82 83 #define vmemmap ((struct page *)VMEMMAP_BASE) 84 85 #include <linux/sched.h> 86 87 bool kern_addr_valid(unsigned long addr); 88 89 /* Entries per page directory level. */ 90 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 91 #define PTRS_PER_PMD (1UL << PMD_BITS) 92 #define PTRS_PER_PUD (1UL << PUD_BITS) 93 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 94 95 /* Kernel has a separate 44bit address space. */ 96 #define FIRST_USER_ADDRESS 0UL 97 98 #define pmd_ERROR(e) \ 99 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ 100 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) 101 #define pud_ERROR(e) \ 102 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ 103 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) 104 #define pgd_ERROR(e) \ 105 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ 106 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) 107 108 #endif /* !(__ASSEMBLY__) */ 109 110 /* PTE bits which are the same in SUN4U and SUN4V format. */ 111 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 112 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 113 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 114 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 115 #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE 116 117 /* Advertise support for _PAGE_SPECIAL */ 118 #define __HAVE_ARCH_PTE_SPECIAL 119 120 /* SUN4U pte bits... */ 121 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 122 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 123 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 124 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 125 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 126 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 127 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 128 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 129 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 130 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 131 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 132 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 133 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 134 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 135 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 136 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 137 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 138 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 139 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 140 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 141 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 142 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 143 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 144 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 145 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 146 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 147 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 148 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 149 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 150 151 /* SUN4V pte bits... */ 152 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 153 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 154 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 155 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 156 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 157 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 158 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 159 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 160 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 161 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 162 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 163 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 164 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 165 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 166 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 167 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 168 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 169 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 170 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 171 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 172 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 173 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 174 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 175 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 176 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 177 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 178 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 179 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 180 181 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 182 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 183 184 #if REAL_HPAGE_SHIFT != 22 185 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 186 #endif 187 188 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 189 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 190 191 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 192 #define __P000 __pgprot(0) 193 #define __P001 __pgprot(0) 194 #define __P010 __pgprot(0) 195 #define __P011 __pgprot(0) 196 #define __P100 __pgprot(0) 197 #define __P101 __pgprot(0) 198 #define __P110 __pgprot(0) 199 #define __P111 __pgprot(0) 200 201 #define __S000 __pgprot(0) 202 #define __S001 __pgprot(0) 203 #define __S010 __pgprot(0) 204 #define __S011 __pgprot(0) 205 #define __S100 __pgprot(0) 206 #define __S101 __pgprot(0) 207 #define __S110 __pgprot(0) 208 #define __S111 __pgprot(0) 209 210 #ifndef __ASSEMBLY__ 211 212 pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 213 214 unsigned long pte_sz_bits(unsigned long size); 215 216 extern pgprot_t PAGE_KERNEL; 217 extern pgprot_t PAGE_KERNEL_LOCKED; 218 extern pgprot_t PAGE_COPY; 219 extern pgprot_t PAGE_SHARED; 220 221 /* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */ 222 extern unsigned long _PAGE_IE; 223 extern unsigned long _PAGE_E; 224 extern unsigned long _PAGE_CACHE; 225 226 extern unsigned long pg_iobits; 227 extern unsigned long _PAGE_ALL_SZ_BITS; 228 229 extern struct page *mem_map_zero; 230 #define ZERO_PAGE(vaddr) (mem_map_zero) 231 232 /* PFNs are real physical page numbers. However, mem_map only begins to record 233 * per-page information starting at pfn_base. This is to handle systems where 234 * the first physical page in the machine is at some huge physical address, 235 * such as 4GB. This is common on a partitioned E10000, for example. 236 */ 237 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 238 { 239 unsigned long paddr = pfn << PAGE_SHIFT; 240 241 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 242 return __pte(paddr | pgprot_val(prot)); 243 } 244 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 245 246 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 247 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 248 { 249 pte_t pte = pfn_pte(page_nr, pgprot); 250 251 return __pmd(pte_val(pte)); 252 } 253 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 254 #endif 255 256 /* This one can be done with two shifts. */ 257 static inline unsigned long pte_pfn(pte_t pte) 258 { 259 unsigned long ret; 260 261 __asm__ __volatile__( 262 "\n661: sllx %1, %2, %0\n" 263 " srlx %0, %3, %0\n" 264 " .section .sun4v_2insn_patch, \"ax\"\n" 265 " .word 661b\n" 266 " sllx %1, %4, %0\n" 267 " srlx %0, %5, %0\n" 268 " .previous\n" 269 : "=r" (ret) 270 : "r" (pte_val(pte)), 271 "i" (21), "i" (21 + PAGE_SHIFT), 272 "i" (8), "i" (8 + PAGE_SHIFT)); 273 274 return ret; 275 } 276 #define pte_page(x) pfn_to_page(pte_pfn(x)) 277 278 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 279 { 280 unsigned long mask, tmp; 281 282 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) 283 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) 284 * 285 * Even if we use negation tricks the result is still a 6 286 * instruction sequence, so don't try to play fancy and just 287 * do the most straightforward implementation. 288 * 289 * Note: We encode this into 3 sun4v 2-insn patch sequences. 290 */ 291 292 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 293 __asm__ __volatile__( 294 "\n661: sethi %%uhi(%2), %1\n" 295 " sethi %%hi(%2), %0\n" 296 "\n662: or %1, %%ulo(%2), %1\n" 297 " or %0, %%lo(%2), %0\n" 298 "\n663: sllx %1, 32, %1\n" 299 " or %0, %1, %0\n" 300 " .section .sun4v_2insn_patch, \"ax\"\n" 301 " .word 661b\n" 302 " sethi %%uhi(%3), %1\n" 303 " sethi %%hi(%3), %0\n" 304 " .word 662b\n" 305 " or %1, %%ulo(%3), %1\n" 306 " or %0, %%lo(%3), %0\n" 307 " .word 663b\n" 308 " sllx %1, 32, %1\n" 309 " or %0, %1, %0\n" 310 " .previous\n" 311 " .section .sun_m7_2insn_patch, \"ax\"\n" 312 " .word 661b\n" 313 " sethi %%uhi(%4), %1\n" 314 " sethi %%hi(%4), %0\n" 315 " .word 662b\n" 316 " or %1, %%ulo(%4), %1\n" 317 " or %0, %%lo(%4), %0\n" 318 " .word 663b\n" 319 " sllx %1, 32, %1\n" 320 " or %0, %1, %0\n" 321 " .previous\n" 322 : "=r" (mask), "=r" (tmp) 323 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 324 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | 325 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 326 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 327 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | 328 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V), 329 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 330 _PAGE_CP_4V | _PAGE_E_4V | 331 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 332 333 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 334 } 335 336 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 337 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 338 { 339 pte_t pte = __pte(pmd_val(pmd)); 340 341 pte = pte_modify(pte, newprot); 342 343 return __pmd(pte_val(pte)); 344 } 345 #endif 346 347 static inline pgprot_t pgprot_noncached(pgprot_t prot) 348 { 349 unsigned long val = pgprot_val(prot); 350 351 __asm__ __volatile__( 352 "\n661: andn %0, %2, %0\n" 353 " or %0, %3, %0\n" 354 " .section .sun4v_2insn_patch, \"ax\"\n" 355 " .word 661b\n" 356 " andn %0, %4, %0\n" 357 " or %0, %5, %0\n" 358 " .previous\n" 359 " .section .sun_m7_2insn_patch, \"ax\"\n" 360 " .word 661b\n" 361 " andn %0, %6, %0\n" 362 " or %0, %5, %0\n" 363 " .previous\n" 364 : "=r" (val) 365 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 366 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V), 367 "i" (_PAGE_CP_4V)); 368 369 return __pgprot(val); 370 } 371 /* Various pieces of code check for platform support by ifdef testing 372 * on "pgprot_noncached". That's broken and should be fixed, but for 373 * now... 374 */ 375 #define pgprot_noncached pgprot_noncached 376 377 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 378 static inline unsigned long __pte_huge_mask(void) 379 { 380 unsigned long mask; 381 382 __asm__ __volatile__( 383 "\n661: sethi %%uhi(%1), %0\n" 384 " sllx %0, 32, %0\n" 385 " .section .sun4v_2insn_patch, \"ax\"\n" 386 " .word 661b\n" 387 " mov %2, %0\n" 388 " nop\n" 389 " .previous\n" 390 : "=r" (mask) 391 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 392 393 return mask; 394 } 395 396 static inline pte_t pte_mkhuge(pte_t pte) 397 { 398 return __pte(pte_val(pte) | _PAGE_PMD_HUGE | __pte_huge_mask()); 399 } 400 401 static inline bool is_hugetlb_pte(pte_t pte) 402 { 403 return !!(pte_val(pte) & __pte_huge_mask()); 404 } 405 406 static inline bool is_hugetlb_pmd(pmd_t pmd) 407 { 408 return !!(pmd_val(pmd) & _PAGE_PMD_HUGE); 409 } 410 411 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 412 static inline pmd_t pmd_mkhuge(pmd_t pmd) 413 { 414 pte_t pte = __pte(pmd_val(pmd)); 415 416 pte = pte_mkhuge(pte); 417 pte_val(pte) |= _PAGE_PMD_HUGE; 418 419 return __pmd(pte_val(pte)); 420 } 421 #endif 422 #else 423 static inline bool is_hugetlb_pte(pte_t pte) 424 { 425 return false; 426 } 427 #endif 428 429 static inline pte_t pte_mkdirty(pte_t pte) 430 { 431 unsigned long val = pte_val(pte), tmp; 432 433 __asm__ __volatile__( 434 "\n661: or %0, %3, %0\n" 435 " nop\n" 436 "\n662: nop\n" 437 " nop\n" 438 " .section .sun4v_2insn_patch, \"ax\"\n" 439 " .word 661b\n" 440 " sethi %%uhi(%4), %1\n" 441 " sllx %1, 32, %1\n" 442 " .word 662b\n" 443 " or %1, %%lo(%4), %1\n" 444 " or %0, %1, %0\n" 445 " .previous\n" 446 : "=r" (val), "=r" (tmp) 447 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 448 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 449 450 return __pte(val); 451 } 452 453 static inline pte_t pte_mkclean(pte_t pte) 454 { 455 unsigned long val = pte_val(pte), tmp; 456 457 __asm__ __volatile__( 458 "\n661: andn %0, %3, %0\n" 459 " nop\n" 460 "\n662: nop\n" 461 " nop\n" 462 " .section .sun4v_2insn_patch, \"ax\"\n" 463 " .word 661b\n" 464 " sethi %%uhi(%4), %1\n" 465 " sllx %1, 32, %1\n" 466 " .word 662b\n" 467 " or %1, %%lo(%4), %1\n" 468 " andn %0, %1, %0\n" 469 " .previous\n" 470 : "=r" (val), "=r" (tmp) 471 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 472 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 473 474 return __pte(val); 475 } 476 477 static inline pte_t pte_mkwrite(pte_t pte) 478 { 479 unsigned long val = pte_val(pte), mask; 480 481 __asm__ __volatile__( 482 "\n661: mov %1, %0\n" 483 " nop\n" 484 " .section .sun4v_2insn_patch, \"ax\"\n" 485 " .word 661b\n" 486 " sethi %%uhi(%2), %0\n" 487 " sllx %0, 32, %0\n" 488 " .previous\n" 489 : "=r" (mask) 490 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 491 492 return __pte(val | mask); 493 } 494 495 static inline pte_t pte_wrprotect(pte_t pte) 496 { 497 unsigned long val = pte_val(pte), tmp; 498 499 __asm__ __volatile__( 500 "\n661: andn %0, %3, %0\n" 501 " nop\n" 502 "\n662: nop\n" 503 " nop\n" 504 " .section .sun4v_2insn_patch, \"ax\"\n" 505 " .word 661b\n" 506 " sethi %%uhi(%4), %1\n" 507 " sllx %1, 32, %1\n" 508 " .word 662b\n" 509 " or %1, %%lo(%4), %1\n" 510 " andn %0, %1, %0\n" 511 " .previous\n" 512 : "=r" (val), "=r" (tmp) 513 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 514 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 515 516 return __pte(val); 517 } 518 519 static inline pte_t pte_mkold(pte_t pte) 520 { 521 unsigned long mask; 522 523 __asm__ __volatile__( 524 "\n661: mov %1, %0\n" 525 " nop\n" 526 " .section .sun4v_2insn_patch, \"ax\"\n" 527 " .word 661b\n" 528 " sethi %%uhi(%2), %0\n" 529 " sllx %0, 32, %0\n" 530 " .previous\n" 531 : "=r" (mask) 532 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 533 534 mask |= _PAGE_R; 535 536 return __pte(pte_val(pte) & ~mask); 537 } 538 539 static inline pte_t pte_mkyoung(pte_t pte) 540 { 541 unsigned long mask; 542 543 __asm__ __volatile__( 544 "\n661: mov %1, %0\n" 545 " nop\n" 546 " .section .sun4v_2insn_patch, \"ax\"\n" 547 " .word 661b\n" 548 " sethi %%uhi(%2), %0\n" 549 " sllx %0, 32, %0\n" 550 " .previous\n" 551 : "=r" (mask) 552 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 553 554 mask |= _PAGE_R; 555 556 return __pte(pte_val(pte) | mask); 557 } 558 559 static inline pte_t pte_mkspecial(pte_t pte) 560 { 561 pte_val(pte) |= _PAGE_SPECIAL; 562 return pte; 563 } 564 565 static inline unsigned long pte_young(pte_t pte) 566 { 567 unsigned long mask; 568 569 __asm__ __volatile__( 570 "\n661: mov %1, %0\n" 571 " nop\n" 572 " .section .sun4v_2insn_patch, \"ax\"\n" 573 " .word 661b\n" 574 " sethi %%uhi(%2), %0\n" 575 " sllx %0, 32, %0\n" 576 " .previous\n" 577 : "=r" (mask) 578 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 579 580 return (pte_val(pte) & mask); 581 } 582 583 static inline unsigned long pte_dirty(pte_t pte) 584 { 585 unsigned long mask; 586 587 __asm__ __volatile__( 588 "\n661: mov %1, %0\n" 589 " nop\n" 590 " .section .sun4v_2insn_patch, \"ax\"\n" 591 " .word 661b\n" 592 " sethi %%uhi(%2), %0\n" 593 " sllx %0, 32, %0\n" 594 " .previous\n" 595 : "=r" (mask) 596 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 597 598 return (pte_val(pte) & mask); 599 } 600 601 static inline unsigned long pte_write(pte_t pte) 602 { 603 unsigned long mask; 604 605 __asm__ __volatile__( 606 "\n661: mov %1, %0\n" 607 " nop\n" 608 " .section .sun4v_2insn_patch, \"ax\"\n" 609 " .word 661b\n" 610 " sethi %%uhi(%2), %0\n" 611 " sllx %0, 32, %0\n" 612 " .previous\n" 613 : "=r" (mask) 614 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 615 616 return (pte_val(pte) & mask); 617 } 618 619 static inline unsigned long pte_exec(pte_t pte) 620 { 621 unsigned long mask; 622 623 __asm__ __volatile__( 624 "\n661: sethi %%hi(%1), %0\n" 625 " .section .sun4v_1insn_patch, \"ax\"\n" 626 " .word 661b\n" 627 " mov %2, %0\n" 628 " .previous\n" 629 : "=r" (mask) 630 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 631 632 return (pte_val(pte) & mask); 633 } 634 635 static inline unsigned long pte_present(pte_t pte) 636 { 637 unsigned long val = pte_val(pte); 638 639 __asm__ __volatile__( 640 "\n661: and %0, %2, %0\n" 641 " .section .sun4v_1insn_patch, \"ax\"\n" 642 " .word 661b\n" 643 " and %0, %3, %0\n" 644 " .previous\n" 645 : "=r" (val) 646 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 647 648 return val; 649 } 650 651 #define pte_accessible pte_accessible 652 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 653 { 654 return pte_val(a) & _PAGE_VALID; 655 } 656 657 static inline unsigned long pte_special(pte_t pte) 658 { 659 return pte_val(pte) & _PAGE_SPECIAL; 660 } 661 662 static inline unsigned long pmd_large(pmd_t pmd) 663 { 664 pte_t pte = __pte(pmd_val(pmd)); 665 666 return pte_val(pte) & _PAGE_PMD_HUGE; 667 } 668 669 static inline unsigned long pmd_pfn(pmd_t pmd) 670 { 671 pte_t pte = __pte(pmd_val(pmd)); 672 673 return pte_pfn(pte); 674 } 675 676 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 677 static inline unsigned long pmd_dirty(pmd_t pmd) 678 { 679 pte_t pte = __pte(pmd_val(pmd)); 680 681 return pte_dirty(pte); 682 } 683 684 static inline unsigned long pmd_young(pmd_t pmd) 685 { 686 pte_t pte = __pte(pmd_val(pmd)); 687 688 return pte_young(pte); 689 } 690 691 static inline unsigned long pmd_write(pmd_t pmd) 692 { 693 pte_t pte = __pte(pmd_val(pmd)); 694 695 return pte_write(pte); 696 } 697 698 static inline unsigned long pmd_trans_huge(pmd_t pmd) 699 { 700 pte_t pte = __pte(pmd_val(pmd)); 701 702 return pte_val(pte) & _PAGE_PMD_HUGE; 703 } 704 705 static inline pmd_t pmd_mkold(pmd_t pmd) 706 { 707 pte_t pte = __pte(pmd_val(pmd)); 708 709 pte = pte_mkold(pte); 710 711 return __pmd(pte_val(pte)); 712 } 713 714 static inline pmd_t pmd_wrprotect(pmd_t pmd) 715 { 716 pte_t pte = __pte(pmd_val(pmd)); 717 718 pte = pte_wrprotect(pte); 719 720 return __pmd(pte_val(pte)); 721 } 722 723 static inline pmd_t pmd_mkdirty(pmd_t pmd) 724 { 725 pte_t pte = __pte(pmd_val(pmd)); 726 727 pte = pte_mkdirty(pte); 728 729 return __pmd(pte_val(pte)); 730 } 731 732 static inline pmd_t pmd_mkclean(pmd_t pmd) 733 { 734 pte_t pte = __pte(pmd_val(pmd)); 735 736 pte = pte_mkclean(pte); 737 738 return __pmd(pte_val(pte)); 739 } 740 741 static inline pmd_t pmd_mkyoung(pmd_t pmd) 742 { 743 pte_t pte = __pte(pmd_val(pmd)); 744 745 pte = pte_mkyoung(pte); 746 747 return __pmd(pte_val(pte)); 748 } 749 750 static inline pmd_t pmd_mkwrite(pmd_t pmd) 751 { 752 pte_t pte = __pte(pmd_val(pmd)); 753 754 pte = pte_mkwrite(pte); 755 756 return __pmd(pte_val(pte)); 757 } 758 759 static inline pgprot_t pmd_pgprot(pmd_t entry) 760 { 761 unsigned long val = pmd_val(entry); 762 763 return __pgprot(val); 764 } 765 #endif 766 767 static inline int pmd_present(pmd_t pmd) 768 { 769 return pmd_val(pmd) != 0UL; 770 } 771 772 #define pmd_none(pmd) (!pmd_val(pmd)) 773 774 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is 775 * very simple, it's just the physical address. PTE tables are of 776 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and 777 * the top bits outside of the range of any physical address size we 778 * support are clear as well. We also validate the physical itself. 779 */ 780 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 781 782 #define pud_none(pud) (!pud_val(pud)) 783 784 #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) 785 786 #define pgd_none(pgd) (!pgd_val(pgd)) 787 788 #define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK) 789 790 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 791 void set_pmd_at(struct mm_struct *mm, unsigned long addr, 792 pmd_t *pmdp, pmd_t pmd); 793 #else 794 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 795 pmd_t *pmdp, pmd_t pmd) 796 { 797 *pmdp = pmd; 798 } 799 #endif 800 801 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 802 { 803 unsigned long val = __pa((unsigned long) (ptep)); 804 805 pmd_val(*pmdp) = val; 806 } 807 808 #define pud_set(pudp, pmdp) \ 809 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 810 static inline unsigned long __pmd_page(pmd_t pmd) 811 { 812 pte_t pte = __pte(pmd_val(pmd)); 813 unsigned long pfn; 814 815 pfn = pte_pfn(pte); 816 817 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 818 } 819 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 820 #define pud_page_vaddr(pud) \ 821 ((unsigned long) __va(pud_val(pud))) 822 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 823 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 824 #define pud_present(pud) (pud_val(pud) != 0U) 825 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 826 #define pgd_page_vaddr(pgd) \ 827 ((unsigned long) __va(pgd_val(pgd))) 828 #define pgd_present(pgd) (pgd_val(pgd) != 0U) 829 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) 830 831 static inline unsigned long pud_large(pud_t pud) 832 { 833 pte_t pte = __pte(pud_val(pud)); 834 835 return pte_val(pte) & _PAGE_PMD_HUGE; 836 } 837 838 static inline unsigned long pud_pfn(pud_t pud) 839 { 840 pte_t pte = __pte(pud_val(pud)); 841 842 return pte_pfn(pte); 843 } 844 845 /* Same in both SUN4V and SUN4U. */ 846 #define pte_none(pte) (!pte_val(pte)) 847 848 #define pgd_set(pgdp, pudp) \ 849 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp)))) 850 851 /* to find an entry in a page-table-directory. */ 852 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 853 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 854 855 /* to find an entry in a kernel page-table-directory */ 856 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 857 858 /* Find an entry in the third-level page table.. */ 859 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 860 #define pud_offset(pgdp, address) \ 861 ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address)) 862 863 /* Find an entry in the second-level page table.. */ 864 #define pmd_offset(pudp, address) \ 865 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 866 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 867 868 /* Find an entry in the third-level page table.. */ 869 #define pte_index(dir, address) \ 870 ((pte_t *) __pmd_page(*(dir)) + \ 871 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 872 #define pte_offset_kernel pte_index 873 #define pte_offset_map pte_index 874 #define pte_unmap(pte) do { } while (0) 875 876 /* Actual page table PTE updates. */ 877 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 878 pte_t *ptep, pte_t orig, int fullmm); 879 880 static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 881 pte_t *ptep, pte_t orig, int fullmm) 882 { 883 /* It is more efficient to let flush_tlb_kernel_range() 884 * handle init_mm tlb flushes. 885 * 886 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 887 * and SUN4V pte layout, so this inline test is fine. 888 */ 889 if (likely(mm != &init_mm) && pte_accessible(mm, orig)) 890 tlb_batch_add(mm, vaddr, ptep, orig, fullmm); 891 } 892 893 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 894 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 895 unsigned long addr, 896 pmd_t *pmdp) 897 { 898 pmd_t pmd = *pmdp; 899 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 900 return pmd; 901 } 902 903 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 904 pte_t *ptep, pte_t pte, int fullmm) 905 { 906 pte_t orig = *ptep; 907 908 *ptep = pte; 909 maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm); 910 } 911 912 #define set_pte_at(mm,addr,ptep,pte) \ 913 __set_pte_at((mm), (addr), (ptep), (pte), 0) 914 915 #define pte_clear(mm,addr,ptep) \ 916 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 917 918 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 919 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 920 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 921 922 #ifdef DCACHE_ALIASING_POSSIBLE 923 #define __HAVE_ARCH_MOVE_PTE 924 #define move_pte(pte, prot, old_addr, new_addr) \ 925 ({ \ 926 pte_t newpte = (pte); \ 927 if (tlb_type != hypervisor && pte_present(pte)) { \ 928 unsigned long this_pfn = pte_pfn(pte); \ 929 \ 930 if (pfn_valid(this_pfn) && \ 931 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 932 flush_dcache_page_all(current->mm, \ 933 pfn_to_page(this_pfn)); \ 934 } \ 935 newpte; \ 936 }) 937 #endif 938 939 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 940 941 void paging_init(void); 942 unsigned long find_ecache_flush_span(unsigned long size); 943 944 struct seq_file; 945 void mmu_info(struct seq_file *); 946 947 struct vm_area_struct; 948 void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 949 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 950 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 951 pmd_t *pmd); 952 953 #define __HAVE_ARCH_PMDP_INVALIDATE 954 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 955 pmd_t *pmdp); 956 957 #define __HAVE_ARCH_PGTABLE_DEPOSIT 958 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 959 pgtable_t pgtable); 960 961 #define __HAVE_ARCH_PGTABLE_WITHDRAW 962 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 963 #endif 964 965 /* Encode and de-code a swap entry */ 966 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 967 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 968 #define __swp_entry(type, offset) \ 969 ( (swp_entry_t) \ 970 { \ 971 (((long)(type) << PAGE_SHIFT) | \ 972 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 973 } ) 974 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 975 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 976 977 int page_in_phys_avail(unsigned long paddr); 978 979 /* 980 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 981 * its high 4 bits. These macros/functions put it there or get it from there. 982 */ 983 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 984 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 985 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 986 987 int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 988 unsigned long, pgprot_t); 989 990 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 991 unsigned long from, unsigned long pfn, 992 unsigned long size, pgprot_t prot) 993 { 994 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 995 int space = GET_IOSPACE(pfn); 996 unsigned long phys_base; 997 998 phys_base = offset | (((unsigned long) space) << 32UL); 999 1000 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 1001 } 1002 #define io_remap_pfn_range io_remap_pfn_range 1003 1004 #include <asm/tlbflush.h> 1005 #include <asm-generic/pgtable.h> 1006 1007 /* We provide our own get_unmapped_area to cope with VA holes and 1008 * SHM area cache aliasing for userland. 1009 */ 1010 #define HAVE_ARCH_UNMAPPED_AREA 1011 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1012 1013 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 1014 * the largest alignment possible such that larget PTEs can be used. 1015 */ 1016 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 1017 unsigned long, unsigned long, 1018 unsigned long); 1019 #define HAVE_ARCH_FB_UNMAPPED_AREA 1020 1021 void pgtable_cache_init(void); 1022 void sun4v_register_fault_status(void); 1023 void sun4v_ktsb_register(void); 1024 void __init cheetah_ecache_flush_init(void); 1025 void sun4v_patch_tlb_handlers(void); 1026 1027 extern unsigned long cmdline_memory_size; 1028 1029 asmlinkage void do_sparc64_fault(struct pt_regs *regs); 1030 1031 #endif /* !(__ASSEMBLY__) */ 1032 1033 #endif /* !(_SPARC64_PGTABLE_H) */ 1034