1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pgtable.h: SpitFire page table operations. 4 * 5 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 6 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 7 */ 8 9 #ifndef _SPARC64_PGTABLE_H 10 #define _SPARC64_PGTABLE_H 11 12 /* This file contains the functions and defines necessary to modify and use 13 * the SpitFire page tables. 14 */ 15 16 #include <asm-generic/5level-fixup.h> 17 #include <linux/compiler.h> 18 #include <linux/const.h> 19 #include <asm/types.h> 20 #include <asm/spitfire.h> 21 #include <asm/asi.h> 22 #include <asm/adi.h> 23 #include <asm/page.h> 24 #include <asm/processor.h> 25 26 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 27 * The page copy blockops can use 0x6000000 to 0x8000000. 28 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. 29 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. 30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 31 * The vmalloc area spans 0x100000000 to 0x200000000. 32 * Since modules need to be in the lowest 32-bits of the address space, 33 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 34 * There is a single static kernel PMD which maps from 0x0 to address 35 * 0x400000000. 36 */ 37 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 38 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) 39 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) 40 #define MODULES_VADDR _AC(0x0000000010000000,UL) 41 #define MODULES_LEN _AC(0x00000000e0000000,UL) 42 #define MODULES_END _AC(0x00000000f0000000,UL) 43 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 44 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 45 #define VMALLOC_START _AC(0x0000000100000000,UL) 46 #define VMEMMAP_BASE VMALLOC_END 47 48 /* PMD_SHIFT determines the size of the area a second-level page 49 * table can map 50 */ 51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 53 #define PMD_MASK (~(PMD_SIZE-1)) 54 #define PMD_BITS (PAGE_SHIFT - 3) 55 56 /* PUD_SHIFT determines the size of the area a third-level page 57 * table can map 58 */ 59 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) 60 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) 61 #define PUD_MASK (~(PUD_SIZE-1)) 62 #define PUD_BITS (PAGE_SHIFT - 3) 63 64 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 65 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) 66 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 67 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 68 #define PGDIR_BITS (PAGE_SHIFT - 3) 69 70 #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) 71 #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support 72 #endif 73 74 #if (PGDIR_SHIFT + PGDIR_BITS) != 53 75 #error Page table parameters do not cover virtual address space properly. 76 #endif 77 78 #if (PMD_SHIFT != HPAGE_SHIFT) 79 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 80 #endif 81 82 #ifndef __ASSEMBLY__ 83 84 extern unsigned long VMALLOC_END; 85 86 #define vmemmap ((struct page *)VMEMMAP_BASE) 87 88 #include <linux/sched.h> 89 90 bool kern_addr_valid(unsigned long addr); 91 92 /* Entries per page directory level. */ 93 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 94 #define PTRS_PER_PMD (1UL << PMD_BITS) 95 #define PTRS_PER_PUD (1UL << PUD_BITS) 96 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 97 98 /* Kernel has a separate 44bit address space. */ 99 #define FIRST_USER_ADDRESS 0UL 100 101 #define pmd_ERROR(e) \ 102 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ 103 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) 104 #define pud_ERROR(e) \ 105 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ 106 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) 107 #define pgd_ERROR(e) \ 108 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ 109 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) 110 111 #endif /* !(__ASSEMBLY__) */ 112 113 /* PTE bits which are the same in SUN4U and SUN4V format. */ 114 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 115 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 116 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 117 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 118 #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE 119 120 /* SUN4U pte bits... */ 121 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 122 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 123 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 124 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 125 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 126 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 127 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 128 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 129 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 130 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 131 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 132 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 133 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 134 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 135 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 136 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 137 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 138 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 139 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 140 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 141 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 142 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 143 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 144 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 145 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 146 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 147 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 148 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 149 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 150 151 /* SUN4V pte bits... */ 152 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 153 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 154 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 155 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 156 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 157 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 158 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 159 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 160 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 161 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 162 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 163 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 164 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 165 /* Bit 9 is used to enable MCD corruption detection instead on M7 */ 166 #define _PAGE_MCD_4V _AC(0x0000000000000200,UL) /* Memory Corruption */ 167 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 168 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 169 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 170 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 171 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 172 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 173 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 174 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 175 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 176 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 177 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 178 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 179 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 180 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 181 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 182 183 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 184 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 185 186 #if REAL_HPAGE_SHIFT != 22 187 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 188 #endif 189 190 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 191 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 192 193 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 194 #define __P000 __pgprot(0) 195 #define __P001 __pgprot(0) 196 #define __P010 __pgprot(0) 197 #define __P011 __pgprot(0) 198 #define __P100 __pgprot(0) 199 #define __P101 __pgprot(0) 200 #define __P110 __pgprot(0) 201 #define __P111 __pgprot(0) 202 203 #define __S000 __pgprot(0) 204 #define __S001 __pgprot(0) 205 #define __S010 __pgprot(0) 206 #define __S011 __pgprot(0) 207 #define __S100 __pgprot(0) 208 #define __S101 __pgprot(0) 209 #define __S110 __pgprot(0) 210 #define __S111 __pgprot(0) 211 212 #ifndef __ASSEMBLY__ 213 214 pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 215 216 unsigned long pte_sz_bits(unsigned long size); 217 218 extern pgprot_t PAGE_KERNEL; 219 extern pgprot_t PAGE_KERNEL_LOCKED; 220 extern pgprot_t PAGE_COPY; 221 extern pgprot_t PAGE_SHARED; 222 223 /* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */ 224 extern unsigned long _PAGE_IE; 225 extern unsigned long _PAGE_E; 226 extern unsigned long _PAGE_CACHE; 227 228 extern unsigned long pg_iobits; 229 extern unsigned long _PAGE_ALL_SZ_BITS; 230 231 extern struct page *mem_map_zero; 232 #define ZERO_PAGE(vaddr) (mem_map_zero) 233 234 /* This macro must be updated when the size of struct page grows above 80 235 * or reduces below 64. 236 * The idea that compiler optimizes out switch() statement, and only 237 * leaves clrx instructions 238 */ 239 #define mm_zero_struct_page(pp) do { \ 240 unsigned long *_pp = (void *)(pp); \ 241 \ 242 /* Check that struct page is either 64, 72, or 80 bytes */ \ 243 BUILD_BUG_ON(sizeof(struct page) & 7); \ 244 BUILD_BUG_ON(sizeof(struct page) < 64); \ 245 BUILD_BUG_ON(sizeof(struct page) > 80); \ 246 \ 247 switch (sizeof(struct page)) { \ 248 case 80: \ 249 _pp[9] = 0; /* fallthrough */ \ 250 case 72: \ 251 _pp[8] = 0; /* fallthrough */ \ 252 default: \ 253 _pp[7] = 0; \ 254 _pp[6] = 0; \ 255 _pp[5] = 0; \ 256 _pp[4] = 0; \ 257 _pp[3] = 0; \ 258 _pp[2] = 0; \ 259 _pp[1] = 0; \ 260 _pp[0] = 0; \ 261 } \ 262 } while (0) 263 264 /* PFNs are real physical page numbers. However, mem_map only begins to record 265 * per-page information starting at pfn_base. This is to handle systems where 266 * the first physical page in the machine is at some huge physical address, 267 * such as 4GB. This is common on a partitioned E10000, for example. 268 */ 269 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 270 { 271 unsigned long paddr = pfn << PAGE_SHIFT; 272 273 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 274 return __pte(paddr | pgprot_val(prot)); 275 } 276 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 277 278 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 279 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 280 { 281 pte_t pte = pfn_pte(page_nr, pgprot); 282 283 return __pmd(pte_val(pte)); 284 } 285 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 286 #endif 287 288 /* This one can be done with two shifts. */ 289 static inline unsigned long pte_pfn(pte_t pte) 290 { 291 unsigned long ret; 292 293 __asm__ __volatile__( 294 "\n661: sllx %1, %2, %0\n" 295 " srlx %0, %3, %0\n" 296 " .section .sun4v_2insn_patch, \"ax\"\n" 297 " .word 661b\n" 298 " sllx %1, %4, %0\n" 299 " srlx %0, %5, %0\n" 300 " .previous\n" 301 : "=r" (ret) 302 : "r" (pte_val(pte)), 303 "i" (21), "i" (21 + PAGE_SHIFT), 304 "i" (8), "i" (8 + PAGE_SHIFT)); 305 306 return ret; 307 } 308 #define pte_page(x) pfn_to_page(pte_pfn(x)) 309 310 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 311 { 312 unsigned long mask, tmp; 313 314 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) 315 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) 316 * 317 * Even if we use negation tricks the result is still a 6 318 * instruction sequence, so don't try to play fancy and just 319 * do the most straightforward implementation. 320 * 321 * Note: We encode this into 3 sun4v 2-insn patch sequences. 322 */ 323 324 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 325 __asm__ __volatile__( 326 "\n661: sethi %%uhi(%2), %1\n" 327 " sethi %%hi(%2), %0\n" 328 "\n662: or %1, %%ulo(%2), %1\n" 329 " or %0, %%lo(%2), %0\n" 330 "\n663: sllx %1, 32, %1\n" 331 " or %0, %1, %0\n" 332 " .section .sun4v_2insn_patch, \"ax\"\n" 333 " .word 661b\n" 334 " sethi %%uhi(%3), %1\n" 335 " sethi %%hi(%3), %0\n" 336 " .word 662b\n" 337 " or %1, %%ulo(%3), %1\n" 338 " or %0, %%lo(%3), %0\n" 339 " .word 663b\n" 340 " sllx %1, 32, %1\n" 341 " or %0, %1, %0\n" 342 " .previous\n" 343 " .section .sun_m7_2insn_patch, \"ax\"\n" 344 " .word 661b\n" 345 " sethi %%uhi(%4), %1\n" 346 " sethi %%hi(%4), %0\n" 347 " .word 662b\n" 348 " or %1, %%ulo(%4), %1\n" 349 " or %0, %%lo(%4), %0\n" 350 " .word 663b\n" 351 " sllx %1, 32, %1\n" 352 " or %0, %1, %0\n" 353 " .previous\n" 354 : "=r" (mask), "=r" (tmp) 355 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 356 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | 357 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 358 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 359 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | 360 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V), 361 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 362 _PAGE_CP_4V | _PAGE_E_4V | 363 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 364 365 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 366 } 367 368 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 369 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 370 { 371 pte_t pte = __pte(pmd_val(pmd)); 372 373 pte = pte_modify(pte, newprot); 374 375 return __pmd(pte_val(pte)); 376 } 377 #endif 378 379 static inline pgprot_t pgprot_noncached(pgprot_t prot) 380 { 381 unsigned long val = pgprot_val(prot); 382 383 __asm__ __volatile__( 384 "\n661: andn %0, %2, %0\n" 385 " or %0, %3, %0\n" 386 " .section .sun4v_2insn_patch, \"ax\"\n" 387 " .word 661b\n" 388 " andn %0, %4, %0\n" 389 " or %0, %5, %0\n" 390 " .previous\n" 391 " .section .sun_m7_2insn_patch, \"ax\"\n" 392 " .word 661b\n" 393 " andn %0, %6, %0\n" 394 " or %0, %5, %0\n" 395 " .previous\n" 396 : "=r" (val) 397 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 398 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V), 399 "i" (_PAGE_CP_4V)); 400 401 return __pgprot(val); 402 } 403 /* Various pieces of code check for platform support by ifdef testing 404 * on "pgprot_noncached". That's broken and should be fixed, but for 405 * now... 406 */ 407 #define pgprot_noncached pgprot_noncached 408 409 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 410 extern pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, 411 struct page *page, int writable); 412 #define arch_make_huge_pte arch_make_huge_pte 413 static inline unsigned long __pte_default_huge_mask(void) 414 { 415 unsigned long mask; 416 417 __asm__ __volatile__( 418 "\n661: sethi %%uhi(%1), %0\n" 419 " sllx %0, 32, %0\n" 420 " .section .sun4v_2insn_patch, \"ax\"\n" 421 " .word 661b\n" 422 " mov %2, %0\n" 423 " nop\n" 424 " .previous\n" 425 : "=r" (mask) 426 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 427 428 return mask; 429 } 430 431 static inline pte_t pte_mkhuge(pte_t pte) 432 { 433 return __pte(pte_val(pte) | __pte_default_huge_mask()); 434 } 435 436 static inline bool is_default_hugetlb_pte(pte_t pte) 437 { 438 unsigned long mask = __pte_default_huge_mask(); 439 440 return (pte_val(pte) & mask) == mask; 441 } 442 443 static inline bool is_hugetlb_pmd(pmd_t pmd) 444 { 445 return !!(pmd_val(pmd) & _PAGE_PMD_HUGE); 446 } 447 448 static inline bool is_hugetlb_pud(pud_t pud) 449 { 450 return !!(pud_val(pud) & _PAGE_PUD_HUGE); 451 } 452 453 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 454 static inline pmd_t pmd_mkhuge(pmd_t pmd) 455 { 456 pte_t pte = __pte(pmd_val(pmd)); 457 458 pte = pte_mkhuge(pte); 459 pte_val(pte) |= _PAGE_PMD_HUGE; 460 461 return __pmd(pte_val(pte)); 462 } 463 #endif 464 #else 465 static inline bool is_hugetlb_pte(pte_t pte) 466 { 467 return false; 468 } 469 #endif 470 471 static inline pte_t pte_mkdirty(pte_t pte) 472 { 473 unsigned long val = pte_val(pte), tmp; 474 475 __asm__ __volatile__( 476 "\n661: or %0, %3, %0\n" 477 " nop\n" 478 "\n662: nop\n" 479 " nop\n" 480 " .section .sun4v_2insn_patch, \"ax\"\n" 481 " .word 661b\n" 482 " sethi %%uhi(%4), %1\n" 483 " sllx %1, 32, %1\n" 484 " .word 662b\n" 485 " or %1, %%lo(%4), %1\n" 486 " or %0, %1, %0\n" 487 " .previous\n" 488 : "=r" (val), "=r" (tmp) 489 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 490 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 491 492 return __pte(val); 493 } 494 495 static inline pte_t pte_mkclean(pte_t pte) 496 { 497 unsigned long val = pte_val(pte), tmp; 498 499 __asm__ __volatile__( 500 "\n661: andn %0, %3, %0\n" 501 " nop\n" 502 "\n662: nop\n" 503 " nop\n" 504 " .section .sun4v_2insn_patch, \"ax\"\n" 505 " .word 661b\n" 506 " sethi %%uhi(%4), %1\n" 507 " sllx %1, 32, %1\n" 508 " .word 662b\n" 509 " or %1, %%lo(%4), %1\n" 510 " andn %0, %1, %0\n" 511 " .previous\n" 512 : "=r" (val), "=r" (tmp) 513 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 514 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 515 516 return __pte(val); 517 } 518 519 static inline pte_t pte_mkwrite(pte_t pte) 520 { 521 unsigned long val = pte_val(pte), mask; 522 523 __asm__ __volatile__( 524 "\n661: mov %1, %0\n" 525 " nop\n" 526 " .section .sun4v_2insn_patch, \"ax\"\n" 527 " .word 661b\n" 528 " sethi %%uhi(%2), %0\n" 529 " sllx %0, 32, %0\n" 530 " .previous\n" 531 : "=r" (mask) 532 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 533 534 return __pte(val | mask); 535 } 536 537 static inline pte_t pte_wrprotect(pte_t pte) 538 { 539 unsigned long val = pte_val(pte), tmp; 540 541 __asm__ __volatile__( 542 "\n661: andn %0, %3, %0\n" 543 " nop\n" 544 "\n662: nop\n" 545 " nop\n" 546 " .section .sun4v_2insn_patch, \"ax\"\n" 547 " .word 661b\n" 548 " sethi %%uhi(%4), %1\n" 549 " sllx %1, 32, %1\n" 550 " .word 662b\n" 551 " or %1, %%lo(%4), %1\n" 552 " andn %0, %1, %0\n" 553 " .previous\n" 554 : "=r" (val), "=r" (tmp) 555 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 556 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 557 558 return __pte(val); 559 } 560 561 static inline pte_t pte_mkold(pte_t pte) 562 { 563 unsigned long mask; 564 565 __asm__ __volatile__( 566 "\n661: mov %1, %0\n" 567 " nop\n" 568 " .section .sun4v_2insn_patch, \"ax\"\n" 569 " .word 661b\n" 570 " sethi %%uhi(%2), %0\n" 571 " sllx %0, 32, %0\n" 572 " .previous\n" 573 : "=r" (mask) 574 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 575 576 mask |= _PAGE_R; 577 578 return __pte(pte_val(pte) & ~mask); 579 } 580 581 static inline pte_t pte_mkyoung(pte_t pte) 582 { 583 unsigned long mask; 584 585 __asm__ __volatile__( 586 "\n661: mov %1, %0\n" 587 " nop\n" 588 " .section .sun4v_2insn_patch, \"ax\"\n" 589 " .word 661b\n" 590 " sethi %%uhi(%2), %0\n" 591 " sllx %0, 32, %0\n" 592 " .previous\n" 593 : "=r" (mask) 594 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 595 596 mask |= _PAGE_R; 597 598 return __pte(pte_val(pte) | mask); 599 } 600 601 static inline pte_t pte_mkspecial(pte_t pte) 602 { 603 pte_val(pte) |= _PAGE_SPECIAL; 604 return pte; 605 } 606 607 static inline pte_t pte_mkmcd(pte_t pte) 608 { 609 pte_val(pte) |= _PAGE_MCD_4V; 610 return pte; 611 } 612 613 static inline pte_t pte_mknotmcd(pte_t pte) 614 { 615 pte_val(pte) &= ~_PAGE_MCD_4V; 616 return pte; 617 } 618 619 static inline unsigned long pte_young(pte_t pte) 620 { 621 unsigned long mask; 622 623 __asm__ __volatile__( 624 "\n661: mov %1, %0\n" 625 " nop\n" 626 " .section .sun4v_2insn_patch, \"ax\"\n" 627 " .word 661b\n" 628 " sethi %%uhi(%2), %0\n" 629 " sllx %0, 32, %0\n" 630 " .previous\n" 631 : "=r" (mask) 632 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 633 634 return (pte_val(pte) & mask); 635 } 636 637 static inline unsigned long pte_dirty(pte_t pte) 638 { 639 unsigned long mask; 640 641 __asm__ __volatile__( 642 "\n661: mov %1, %0\n" 643 " nop\n" 644 " .section .sun4v_2insn_patch, \"ax\"\n" 645 " .word 661b\n" 646 " sethi %%uhi(%2), %0\n" 647 " sllx %0, 32, %0\n" 648 " .previous\n" 649 : "=r" (mask) 650 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 651 652 return (pte_val(pte) & mask); 653 } 654 655 static inline unsigned long pte_write(pte_t pte) 656 { 657 unsigned long mask; 658 659 __asm__ __volatile__( 660 "\n661: mov %1, %0\n" 661 " nop\n" 662 " .section .sun4v_2insn_patch, \"ax\"\n" 663 " .word 661b\n" 664 " sethi %%uhi(%2), %0\n" 665 " sllx %0, 32, %0\n" 666 " .previous\n" 667 : "=r" (mask) 668 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 669 670 return (pte_val(pte) & mask); 671 } 672 673 static inline unsigned long pte_exec(pte_t pte) 674 { 675 unsigned long mask; 676 677 __asm__ __volatile__( 678 "\n661: sethi %%hi(%1), %0\n" 679 " .section .sun4v_1insn_patch, \"ax\"\n" 680 " .word 661b\n" 681 " mov %2, %0\n" 682 " .previous\n" 683 : "=r" (mask) 684 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 685 686 return (pte_val(pte) & mask); 687 } 688 689 static inline unsigned long pte_present(pte_t pte) 690 { 691 unsigned long val = pte_val(pte); 692 693 __asm__ __volatile__( 694 "\n661: and %0, %2, %0\n" 695 " .section .sun4v_1insn_patch, \"ax\"\n" 696 " .word 661b\n" 697 " and %0, %3, %0\n" 698 " .previous\n" 699 : "=r" (val) 700 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 701 702 return val; 703 } 704 705 #define pte_accessible pte_accessible 706 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 707 { 708 return pte_val(a) & _PAGE_VALID; 709 } 710 711 static inline unsigned long pte_special(pte_t pte) 712 { 713 return pte_val(pte) & _PAGE_SPECIAL; 714 } 715 716 static inline unsigned long pmd_large(pmd_t pmd) 717 { 718 pte_t pte = __pte(pmd_val(pmd)); 719 720 return pte_val(pte) & _PAGE_PMD_HUGE; 721 } 722 723 static inline unsigned long pmd_pfn(pmd_t pmd) 724 { 725 pte_t pte = __pte(pmd_val(pmd)); 726 727 return pte_pfn(pte); 728 } 729 730 #define pmd_write pmd_write 731 static inline unsigned long pmd_write(pmd_t pmd) 732 { 733 pte_t pte = __pte(pmd_val(pmd)); 734 735 return pte_write(pte); 736 } 737 738 #define pud_write(pud) pte_write(__pte(pud_val(pud))) 739 740 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 741 static inline unsigned long pmd_dirty(pmd_t pmd) 742 { 743 pte_t pte = __pte(pmd_val(pmd)); 744 745 return pte_dirty(pte); 746 } 747 748 static inline unsigned long pmd_young(pmd_t pmd) 749 { 750 pte_t pte = __pte(pmd_val(pmd)); 751 752 return pte_young(pte); 753 } 754 755 static inline unsigned long pmd_trans_huge(pmd_t pmd) 756 { 757 pte_t pte = __pte(pmd_val(pmd)); 758 759 return pte_val(pte) & _PAGE_PMD_HUGE; 760 } 761 762 static inline pmd_t pmd_mkold(pmd_t pmd) 763 { 764 pte_t pte = __pte(pmd_val(pmd)); 765 766 pte = pte_mkold(pte); 767 768 return __pmd(pte_val(pte)); 769 } 770 771 static inline pmd_t pmd_wrprotect(pmd_t pmd) 772 { 773 pte_t pte = __pte(pmd_val(pmd)); 774 775 pte = pte_wrprotect(pte); 776 777 return __pmd(pte_val(pte)); 778 } 779 780 static inline pmd_t pmd_mkdirty(pmd_t pmd) 781 { 782 pte_t pte = __pte(pmd_val(pmd)); 783 784 pte = pte_mkdirty(pte); 785 786 return __pmd(pte_val(pte)); 787 } 788 789 static inline pmd_t pmd_mkclean(pmd_t pmd) 790 { 791 pte_t pte = __pte(pmd_val(pmd)); 792 793 pte = pte_mkclean(pte); 794 795 return __pmd(pte_val(pte)); 796 } 797 798 static inline pmd_t pmd_mkyoung(pmd_t pmd) 799 { 800 pte_t pte = __pte(pmd_val(pmd)); 801 802 pte = pte_mkyoung(pte); 803 804 return __pmd(pte_val(pte)); 805 } 806 807 static inline pmd_t pmd_mkwrite(pmd_t pmd) 808 { 809 pte_t pte = __pte(pmd_val(pmd)); 810 811 pte = pte_mkwrite(pte); 812 813 return __pmd(pte_val(pte)); 814 } 815 816 static inline pgprot_t pmd_pgprot(pmd_t entry) 817 { 818 unsigned long val = pmd_val(entry); 819 820 return __pgprot(val); 821 } 822 #endif 823 824 static inline int pmd_present(pmd_t pmd) 825 { 826 return pmd_val(pmd) != 0UL; 827 } 828 829 #define pmd_none(pmd) (!pmd_val(pmd)) 830 831 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is 832 * very simple, it's just the physical address. PTE tables are of 833 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and 834 * the top bits outside of the range of any physical address size we 835 * support are clear as well. We also validate the physical itself. 836 */ 837 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 838 839 #define pud_none(pud) (!pud_val(pud)) 840 841 #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) 842 843 #define pgd_none(pgd) (!pgd_val(pgd)) 844 845 #define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK) 846 847 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 848 void set_pmd_at(struct mm_struct *mm, unsigned long addr, 849 pmd_t *pmdp, pmd_t pmd); 850 #else 851 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 852 pmd_t *pmdp, pmd_t pmd) 853 { 854 *pmdp = pmd; 855 } 856 #endif 857 858 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 859 { 860 unsigned long val = __pa((unsigned long) (ptep)); 861 862 pmd_val(*pmdp) = val; 863 } 864 865 #define pud_set(pudp, pmdp) \ 866 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 867 static inline unsigned long __pmd_page(pmd_t pmd) 868 { 869 pte_t pte = __pte(pmd_val(pmd)); 870 unsigned long pfn; 871 872 pfn = pte_pfn(pte); 873 874 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 875 } 876 877 static inline unsigned long pud_page_vaddr(pud_t pud) 878 { 879 pte_t pte = __pte(pud_val(pud)); 880 unsigned long pfn; 881 882 pfn = pte_pfn(pte); 883 884 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 885 } 886 887 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 888 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 889 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 890 #define pud_present(pud) (pud_val(pud) != 0U) 891 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 892 #define pgd_page_vaddr(pgd) \ 893 ((unsigned long) __va(pgd_val(pgd))) 894 #define pgd_present(pgd) (pgd_val(pgd) != 0U) 895 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) 896 897 static inline unsigned long pud_large(pud_t pud) 898 { 899 pte_t pte = __pte(pud_val(pud)); 900 901 return pte_val(pte) & _PAGE_PMD_HUGE; 902 } 903 904 static inline unsigned long pud_pfn(pud_t pud) 905 { 906 pte_t pte = __pte(pud_val(pud)); 907 908 return pte_pfn(pte); 909 } 910 911 /* Same in both SUN4V and SUN4U. */ 912 #define pte_none(pte) (!pte_val(pte)) 913 914 #define pgd_set(pgdp, pudp) \ 915 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp)))) 916 917 /* to find an entry in a page-table-directory. */ 918 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 919 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 920 921 /* to find an entry in a kernel page-table-directory */ 922 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 923 924 /* Find an entry in the third-level page table.. */ 925 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 926 #define pud_offset(pgdp, address) \ 927 ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address)) 928 929 /* Find an entry in the second-level page table.. */ 930 #define pmd_offset(pudp, address) \ 931 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 932 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 933 934 /* Find an entry in the third-level page table.. */ 935 #define pte_index(dir, address) \ 936 ((pte_t *) __pmd_page(*(dir)) + \ 937 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 938 #define pte_offset_kernel pte_index 939 #define pte_offset_map pte_index 940 #define pte_unmap(pte) do { } while (0) 941 942 /* We cannot include <linux/mm_types.h> at this point yet: */ 943 extern struct mm_struct init_mm; 944 945 /* Actual page table PTE updates. */ 946 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 947 pte_t *ptep, pte_t orig, int fullmm, 948 unsigned int hugepage_shift); 949 950 static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 951 pte_t *ptep, pte_t orig, int fullmm, 952 unsigned int hugepage_shift) 953 { 954 /* It is more efficient to let flush_tlb_kernel_range() 955 * handle init_mm tlb flushes. 956 * 957 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 958 * and SUN4V pte layout, so this inline test is fine. 959 */ 960 if (likely(mm != &init_mm) && pte_accessible(mm, orig)) 961 tlb_batch_add(mm, vaddr, ptep, orig, fullmm, hugepage_shift); 962 } 963 964 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 965 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 966 unsigned long addr, 967 pmd_t *pmdp) 968 { 969 pmd_t pmd = *pmdp; 970 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 971 return pmd; 972 } 973 974 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 975 pte_t *ptep, pte_t pte, int fullmm) 976 { 977 pte_t orig = *ptep; 978 979 *ptep = pte; 980 maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm, PAGE_SHIFT); 981 } 982 983 #define set_pte_at(mm,addr,ptep,pte) \ 984 __set_pte_at((mm), (addr), (ptep), (pte), 0) 985 986 #define pte_clear(mm,addr,ptep) \ 987 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 988 989 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 990 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 991 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 992 993 #ifdef DCACHE_ALIASING_POSSIBLE 994 #define __HAVE_ARCH_MOVE_PTE 995 #define move_pte(pte, prot, old_addr, new_addr) \ 996 ({ \ 997 pte_t newpte = (pte); \ 998 if (tlb_type != hypervisor && pte_present(pte)) { \ 999 unsigned long this_pfn = pte_pfn(pte); \ 1000 \ 1001 if (pfn_valid(this_pfn) && \ 1002 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 1003 flush_dcache_page_all(current->mm, \ 1004 pfn_to_page(this_pfn)); \ 1005 } \ 1006 newpte; \ 1007 }) 1008 #endif 1009 1010 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 1011 1012 void paging_init(void); 1013 unsigned long find_ecache_flush_span(unsigned long size); 1014 1015 struct seq_file; 1016 void mmu_info(struct seq_file *); 1017 1018 struct vm_area_struct; 1019 void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 1020 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1021 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1022 pmd_t *pmd); 1023 1024 #define __HAVE_ARCH_PMDP_INVALIDATE 1025 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1026 pmd_t *pmdp); 1027 1028 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1029 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1030 pgtable_t pgtable); 1031 1032 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1033 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1034 #endif 1035 1036 /* Encode and de-code a swap entry */ 1037 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 1038 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 1039 #define __swp_entry(type, offset) \ 1040 ( (swp_entry_t) \ 1041 { \ 1042 (((long)(type) << PAGE_SHIFT) | \ 1043 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 1044 } ) 1045 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1046 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1047 1048 int page_in_phys_avail(unsigned long paddr); 1049 1050 /* 1051 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 1052 * its high 4 bits. These macros/functions put it there or get it from there. 1053 */ 1054 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 1055 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 1056 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 1057 1058 int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 1059 unsigned long, pgprot_t); 1060 1061 void adi_restore_tags(struct mm_struct *mm, struct vm_area_struct *vma, 1062 unsigned long addr, pte_t pte); 1063 1064 int adi_save_tags(struct mm_struct *mm, struct vm_area_struct *vma, 1065 unsigned long addr, pte_t oldpte); 1066 1067 #define __HAVE_ARCH_DO_SWAP_PAGE 1068 static inline void arch_do_swap_page(struct mm_struct *mm, 1069 struct vm_area_struct *vma, 1070 unsigned long addr, 1071 pte_t pte, pte_t oldpte) 1072 { 1073 /* If this is a new page being mapped in, there can be no 1074 * ADI tags stored away for this page. Skip looking for 1075 * stored tags 1076 */ 1077 if (pte_none(oldpte)) 1078 return; 1079 1080 if (adi_state.enabled && (pte_val(pte) & _PAGE_MCD_4V)) 1081 adi_restore_tags(mm, vma, addr, pte); 1082 } 1083 1084 #define __HAVE_ARCH_UNMAP_ONE 1085 static inline int arch_unmap_one(struct mm_struct *mm, 1086 struct vm_area_struct *vma, 1087 unsigned long addr, pte_t oldpte) 1088 { 1089 if (adi_state.enabled && (pte_val(oldpte) & _PAGE_MCD_4V)) 1090 return adi_save_tags(mm, vma, addr, oldpte); 1091 return 0; 1092 } 1093 1094 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 1095 unsigned long from, unsigned long pfn, 1096 unsigned long size, pgprot_t prot) 1097 { 1098 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 1099 int space = GET_IOSPACE(pfn); 1100 unsigned long phys_base; 1101 1102 phys_base = offset | (((unsigned long) space) << 32UL); 1103 1104 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 1105 } 1106 #define io_remap_pfn_range io_remap_pfn_range 1107 1108 #include <asm/tlbflush.h> 1109 #include <asm-generic/pgtable.h> 1110 1111 /* We provide our own get_unmapped_area to cope with VA holes and 1112 * SHM area cache aliasing for userland. 1113 */ 1114 #define HAVE_ARCH_UNMAPPED_AREA 1115 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1116 1117 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 1118 * the largest alignment possible such that larget PTEs can be used. 1119 */ 1120 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 1121 unsigned long, unsigned long, 1122 unsigned long); 1123 #define HAVE_ARCH_FB_UNMAPPED_AREA 1124 1125 void pgtable_cache_init(void); 1126 void sun4v_register_fault_status(void); 1127 void sun4v_ktsb_register(void); 1128 void __init cheetah_ecache_flush_init(void); 1129 void sun4v_patch_tlb_handlers(void); 1130 1131 extern unsigned long cmdline_memory_size; 1132 1133 asmlinkage void do_sparc64_fault(struct pt_regs *regs); 1134 1135 #endif /* !(__ASSEMBLY__) */ 1136 1137 #endif /* !(_SPARC64_PGTABLE_H) */ 1138