1 /* 2 * pgtable.h: SpitFire page table operations. 3 * 4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #ifndef _SPARC64_PGTABLE_H 9 #define _SPARC64_PGTABLE_H 10 11 /* This file contains the functions and defines necessary to modify and use 12 * the SpitFire page tables. 13 */ 14 15 #include <linux/compiler.h> 16 #include <linux/const.h> 17 #include <asm/types.h> 18 #include <asm/spitfire.h> 19 #include <asm/asi.h> 20 #include <asm/page.h> 21 #include <asm/processor.h> 22 23 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 24 * The page copy blockops can use 0x6000000 to 0x8000000. 25 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. 26 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. 27 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 28 * The vmalloc area spans 0x100000000 to 0x200000000. 29 * Since modules need to be in the lowest 32-bits of the address space, 30 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 31 * There is a single static kernel PMD which maps from 0x0 to address 32 * 0x400000000. 33 */ 34 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 35 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) 36 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) 37 #define MODULES_VADDR _AC(0x0000000010000000,UL) 38 #define MODULES_LEN _AC(0x00000000e0000000,UL) 39 #define MODULES_END _AC(0x00000000f0000000,UL) 40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 42 #define VMALLOC_START _AC(0x0000000100000000,UL) 43 #define VMEMMAP_BASE VMALLOC_END 44 45 /* PMD_SHIFT determines the size of the area a second-level page 46 * table can map 47 */ 48 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 49 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 50 #define PMD_MASK (~(PMD_SIZE-1)) 51 #define PMD_BITS (PAGE_SHIFT - 3) 52 53 /* PUD_SHIFT determines the size of the area a third-level page 54 * table can map 55 */ 56 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) 57 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) 58 #define PUD_MASK (~(PUD_SIZE-1)) 59 #define PUD_BITS (PAGE_SHIFT - 3) 60 61 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 62 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) 63 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 64 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 65 #define PGDIR_BITS (PAGE_SHIFT - 3) 66 67 #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) 68 #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support 69 #endif 70 71 #if (PGDIR_SHIFT + PGDIR_BITS) != 53 72 #error Page table parameters do not cover virtual address space properly. 73 #endif 74 75 #if (PMD_SHIFT != HPAGE_SHIFT) 76 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 77 #endif 78 79 #ifndef __ASSEMBLY__ 80 81 extern unsigned long VMALLOC_END; 82 83 #define vmemmap ((struct page *)VMEMMAP_BASE) 84 85 #include <linux/sched.h> 86 87 bool kern_addr_valid(unsigned long addr); 88 89 /* Entries per page directory level. */ 90 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 91 #define PTRS_PER_PMD (1UL << PMD_BITS) 92 #define PTRS_PER_PUD (1UL << PUD_BITS) 93 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 94 95 /* Kernel has a separate 44bit address space. */ 96 #define FIRST_USER_ADDRESS 0 97 98 #define pmd_ERROR(e) \ 99 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ 100 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) 101 #define pud_ERROR(e) \ 102 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ 103 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) 104 #define pgd_ERROR(e) \ 105 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ 106 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) 107 108 #endif /* !(__ASSEMBLY__) */ 109 110 /* PTE bits which are the same in SUN4U and SUN4V format. */ 111 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 112 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 113 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 114 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 115 #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE 116 117 /* Advertise support for _PAGE_SPECIAL */ 118 #define __HAVE_ARCH_PTE_SPECIAL 119 120 /* SUN4U pte bits... */ 121 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 122 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 123 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 124 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 125 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 126 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 127 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 128 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 129 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 130 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 131 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 132 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 133 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 134 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 135 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 136 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 137 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 138 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 139 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 140 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */ 141 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 142 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 143 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 144 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 145 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 146 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 147 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 148 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 149 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 150 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 151 152 /* SUN4V pte bits... */ 153 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 154 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 155 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 156 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 157 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 158 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 159 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 160 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 161 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 162 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 163 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 164 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 165 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 166 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 167 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 168 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 169 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 170 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */ 171 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 172 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 173 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 174 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 175 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 176 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 177 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 178 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 179 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 180 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 181 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 182 183 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 184 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 185 186 #if REAL_HPAGE_SHIFT != 22 187 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 188 #endif 189 190 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 191 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 192 193 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 194 #define __P000 __pgprot(0) 195 #define __P001 __pgprot(0) 196 #define __P010 __pgprot(0) 197 #define __P011 __pgprot(0) 198 #define __P100 __pgprot(0) 199 #define __P101 __pgprot(0) 200 #define __P110 __pgprot(0) 201 #define __P111 __pgprot(0) 202 203 #define __S000 __pgprot(0) 204 #define __S001 __pgprot(0) 205 #define __S010 __pgprot(0) 206 #define __S011 __pgprot(0) 207 #define __S100 __pgprot(0) 208 #define __S101 __pgprot(0) 209 #define __S110 __pgprot(0) 210 #define __S111 __pgprot(0) 211 212 #ifndef __ASSEMBLY__ 213 214 pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 215 216 unsigned long pte_sz_bits(unsigned long size); 217 218 extern pgprot_t PAGE_KERNEL; 219 extern pgprot_t PAGE_KERNEL_LOCKED; 220 extern pgprot_t PAGE_COPY; 221 extern pgprot_t PAGE_SHARED; 222 223 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */ 224 extern unsigned long _PAGE_IE; 225 extern unsigned long _PAGE_E; 226 extern unsigned long _PAGE_CACHE; 227 228 extern unsigned long pg_iobits; 229 extern unsigned long _PAGE_ALL_SZ_BITS; 230 231 extern struct page *mem_map_zero; 232 #define ZERO_PAGE(vaddr) (mem_map_zero) 233 234 /* PFNs are real physical page numbers. However, mem_map only begins to record 235 * per-page information starting at pfn_base. This is to handle systems where 236 * the first physical page in the machine is at some huge physical address, 237 * such as 4GB. This is common on a partitioned E10000, for example. 238 */ 239 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 240 { 241 unsigned long paddr = pfn << PAGE_SHIFT; 242 243 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 244 return __pte(paddr | pgprot_val(prot)); 245 } 246 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 247 248 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 249 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 250 { 251 pte_t pte = pfn_pte(page_nr, pgprot); 252 253 return __pmd(pte_val(pte)); 254 } 255 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 256 #endif 257 258 /* This one can be done with two shifts. */ 259 static inline unsigned long pte_pfn(pte_t pte) 260 { 261 unsigned long ret; 262 263 __asm__ __volatile__( 264 "\n661: sllx %1, %2, %0\n" 265 " srlx %0, %3, %0\n" 266 " .section .sun4v_2insn_patch, \"ax\"\n" 267 " .word 661b\n" 268 " sllx %1, %4, %0\n" 269 " srlx %0, %5, %0\n" 270 " .previous\n" 271 : "=r" (ret) 272 : "r" (pte_val(pte)), 273 "i" (21), "i" (21 + PAGE_SHIFT), 274 "i" (8), "i" (8 + PAGE_SHIFT)); 275 276 return ret; 277 } 278 #define pte_page(x) pfn_to_page(pte_pfn(x)) 279 280 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 281 { 282 unsigned long mask, tmp; 283 284 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) 285 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) 286 * 287 * Even if we use negation tricks the result is still a 6 288 * instruction sequence, so don't try to play fancy and just 289 * do the most straightforward implementation. 290 * 291 * Note: We encode this into 3 sun4v 2-insn patch sequences. 292 */ 293 294 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 295 __asm__ __volatile__( 296 "\n661: sethi %%uhi(%2), %1\n" 297 " sethi %%hi(%2), %0\n" 298 "\n662: or %1, %%ulo(%2), %1\n" 299 " or %0, %%lo(%2), %0\n" 300 "\n663: sllx %1, 32, %1\n" 301 " or %0, %1, %0\n" 302 " .section .sun4v_2insn_patch, \"ax\"\n" 303 " .word 661b\n" 304 " sethi %%uhi(%3), %1\n" 305 " sethi %%hi(%3), %0\n" 306 " .word 662b\n" 307 " or %1, %%ulo(%3), %1\n" 308 " or %0, %%lo(%3), %0\n" 309 " .word 663b\n" 310 " sllx %1, 32, %1\n" 311 " or %0, %1, %0\n" 312 " .previous\n" 313 : "=r" (mask), "=r" (tmp) 314 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 315 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | 316 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 317 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 318 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | 319 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 320 321 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 322 } 323 324 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 325 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 326 { 327 pte_t pte = __pte(pmd_val(pmd)); 328 329 pte = pte_modify(pte, newprot); 330 331 return __pmd(pte_val(pte)); 332 } 333 #endif 334 335 static inline pte_t pgoff_to_pte(unsigned long off) 336 { 337 off <<= PAGE_SHIFT; 338 339 __asm__ __volatile__( 340 "\n661: or %0, %2, %0\n" 341 " .section .sun4v_1insn_patch, \"ax\"\n" 342 " .word 661b\n" 343 " or %0, %3, %0\n" 344 " .previous\n" 345 : "=r" (off) 346 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 347 348 return __pte(off); 349 } 350 351 static inline pgprot_t pgprot_noncached(pgprot_t prot) 352 { 353 unsigned long val = pgprot_val(prot); 354 355 __asm__ __volatile__( 356 "\n661: andn %0, %2, %0\n" 357 " or %0, %3, %0\n" 358 " .section .sun4v_2insn_patch, \"ax\"\n" 359 " .word 661b\n" 360 " andn %0, %4, %0\n" 361 " or %0, %5, %0\n" 362 " .previous\n" 363 : "=r" (val) 364 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 365 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V)); 366 367 return __pgprot(val); 368 } 369 /* Various pieces of code check for platform support by ifdef testing 370 * on "pgprot_noncached". That's broken and should be fixed, but for 371 * now... 372 */ 373 #define pgprot_noncached pgprot_noncached 374 375 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 376 static inline pte_t pte_mkhuge(pte_t pte) 377 { 378 unsigned long mask; 379 380 __asm__ __volatile__( 381 "\n661: sethi %%uhi(%1), %0\n" 382 " sllx %0, 32, %0\n" 383 " .section .sun4v_2insn_patch, \"ax\"\n" 384 " .word 661b\n" 385 " mov %2, %0\n" 386 " nop\n" 387 " .previous\n" 388 : "=r" (mask) 389 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 390 391 return __pte(pte_val(pte) | mask); 392 } 393 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 394 static inline pmd_t pmd_mkhuge(pmd_t pmd) 395 { 396 pte_t pte = __pte(pmd_val(pmd)); 397 398 pte = pte_mkhuge(pte); 399 pte_val(pte) |= _PAGE_PMD_HUGE; 400 401 return __pmd(pte_val(pte)); 402 } 403 #endif 404 #endif 405 406 static inline pte_t pte_mkdirty(pte_t pte) 407 { 408 unsigned long val = pte_val(pte), tmp; 409 410 __asm__ __volatile__( 411 "\n661: or %0, %3, %0\n" 412 " nop\n" 413 "\n662: nop\n" 414 " nop\n" 415 " .section .sun4v_2insn_patch, \"ax\"\n" 416 " .word 661b\n" 417 " sethi %%uhi(%4), %1\n" 418 " sllx %1, 32, %1\n" 419 " .word 662b\n" 420 " or %1, %%lo(%4), %1\n" 421 " or %0, %1, %0\n" 422 " .previous\n" 423 : "=r" (val), "=r" (tmp) 424 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 425 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 426 427 return __pte(val); 428 } 429 430 static inline pte_t pte_mkclean(pte_t pte) 431 { 432 unsigned long val = pte_val(pte), tmp; 433 434 __asm__ __volatile__( 435 "\n661: andn %0, %3, %0\n" 436 " nop\n" 437 "\n662: nop\n" 438 " nop\n" 439 " .section .sun4v_2insn_patch, \"ax\"\n" 440 " .word 661b\n" 441 " sethi %%uhi(%4), %1\n" 442 " sllx %1, 32, %1\n" 443 " .word 662b\n" 444 " or %1, %%lo(%4), %1\n" 445 " andn %0, %1, %0\n" 446 " .previous\n" 447 : "=r" (val), "=r" (tmp) 448 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 449 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 450 451 return __pte(val); 452 } 453 454 static inline pte_t pte_mkwrite(pte_t pte) 455 { 456 unsigned long val = pte_val(pte), mask; 457 458 __asm__ __volatile__( 459 "\n661: mov %1, %0\n" 460 " nop\n" 461 " .section .sun4v_2insn_patch, \"ax\"\n" 462 " .word 661b\n" 463 " sethi %%uhi(%2), %0\n" 464 " sllx %0, 32, %0\n" 465 " .previous\n" 466 : "=r" (mask) 467 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 468 469 return __pte(val | mask); 470 } 471 472 static inline pte_t pte_wrprotect(pte_t pte) 473 { 474 unsigned long val = pte_val(pte), tmp; 475 476 __asm__ __volatile__( 477 "\n661: andn %0, %3, %0\n" 478 " nop\n" 479 "\n662: nop\n" 480 " nop\n" 481 " .section .sun4v_2insn_patch, \"ax\"\n" 482 " .word 661b\n" 483 " sethi %%uhi(%4), %1\n" 484 " sllx %1, 32, %1\n" 485 " .word 662b\n" 486 " or %1, %%lo(%4), %1\n" 487 " andn %0, %1, %0\n" 488 " .previous\n" 489 : "=r" (val), "=r" (tmp) 490 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 491 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 492 493 return __pte(val); 494 } 495 496 static inline pte_t pte_mkold(pte_t pte) 497 { 498 unsigned long mask; 499 500 __asm__ __volatile__( 501 "\n661: mov %1, %0\n" 502 " nop\n" 503 " .section .sun4v_2insn_patch, \"ax\"\n" 504 " .word 661b\n" 505 " sethi %%uhi(%2), %0\n" 506 " sllx %0, 32, %0\n" 507 " .previous\n" 508 : "=r" (mask) 509 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 510 511 mask |= _PAGE_R; 512 513 return __pte(pte_val(pte) & ~mask); 514 } 515 516 static inline pte_t pte_mkyoung(pte_t pte) 517 { 518 unsigned long mask; 519 520 __asm__ __volatile__( 521 "\n661: mov %1, %0\n" 522 " nop\n" 523 " .section .sun4v_2insn_patch, \"ax\"\n" 524 " .word 661b\n" 525 " sethi %%uhi(%2), %0\n" 526 " sllx %0, 32, %0\n" 527 " .previous\n" 528 : "=r" (mask) 529 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 530 531 mask |= _PAGE_R; 532 533 return __pte(pte_val(pte) | mask); 534 } 535 536 static inline pte_t pte_mkspecial(pte_t pte) 537 { 538 pte_val(pte) |= _PAGE_SPECIAL; 539 return pte; 540 } 541 542 static inline unsigned long pte_young(pte_t pte) 543 { 544 unsigned long mask; 545 546 __asm__ __volatile__( 547 "\n661: mov %1, %0\n" 548 " nop\n" 549 " .section .sun4v_2insn_patch, \"ax\"\n" 550 " .word 661b\n" 551 " sethi %%uhi(%2), %0\n" 552 " sllx %0, 32, %0\n" 553 " .previous\n" 554 : "=r" (mask) 555 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 556 557 return (pte_val(pte) & mask); 558 } 559 560 static inline unsigned long pte_dirty(pte_t pte) 561 { 562 unsigned long mask; 563 564 __asm__ __volatile__( 565 "\n661: mov %1, %0\n" 566 " nop\n" 567 " .section .sun4v_2insn_patch, \"ax\"\n" 568 " .word 661b\n" 569 " sethi %%uhi(%2), %0\n" 570 " sllx %0, 32, %0\n" 571 " .previous\n" 572 : "=r" (mask) 573 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 574 575 return (pte_val(pte) & mask); 576 } 577 578 static inline unsigned long pte_write(pte_t pte) 579 { 580 unsigned long mask; 581 582 __asm__ __volatile__( 583 "\n661: mov %1, %0\n" 584 " nop\n" 585 " .section .sun4v_2insn_patch, \"ax\"\n" 586 " .word 661b\n" 587 " sethi %%uhi(%2), %0\n" 588 " sllx %0, 32, %0\n" 589 " .previous\n" 590 : "=r" (mask) 591 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 592 593 return (pte_val(pte) & mask); 594 } 595 596 static inline unsigned long pte_exec(pte_t pte) 597 { 598 unsigned long mask; 599 600 __asm__ __volatile__( 601 "\n661: sethi %%hi(%1), %0\n" 602 " .section .sun4v_1insn_patch, \"ax\"\n" 603 " .word 661b\n" 604 " mov %2, %0\n" 605 " .previous\n" 606 : "=r" (mask) 607 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 608 609 return (pte_val(pte) & mask); 610 } 611 612 static inline unsigned long pte_file(pte_t pte) 613 { 614 unsigned long val = pte_val(pte); 615 616 __asm__ __volatile__( 617 "\n661: and %0, %2, %0\n" 618 " .section .sun4v_1insn_patch, \"ax\"\n" 619 " .word 661b\n" 620 " and %0, %3, %0\n" 621 " .previous\n" 622 : "=r" (val) 623 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 624 625 return val; 626 } 627 628 static inline unsigned long pte_present(pte_t pte) 629 { 630 unsigned long val = pte_val(pte); 631 632 __asm__ __volatile__( 633 "\n661: and %0, %2, %0\n" 634 " .section .sun4v_1insn_patch, \"ax\"\n" 635 " .word 661b\n" 636 " and %0, %3, %0\n" 637 " .previous\n" 638 : "=r" (val) 639 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 640 641 return val; 642 } 643 644 #define pte_accessible pte_accessible 645 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 646 { 647 return pte_val(a) & _PAGE_VALID; 648 } 649 650 static inline unsigned long pte_special(pte_t pte) 651 { 652 return pte_val(pte) & _PAGE_SPECIAL; 653 } 654 655 static inline unsigned long pmd_large(pmd_t pmd) 656 { 657 pte_t pte = __pte(pmd_val(pmd)); 658 659 return pte_val(pte) & _PAGE_PMD_HUGE; 660 } 661 662 static inline unsigned long pmd_pfn(pmd_t pmd) 663 { 664 pte_t pte = __pte(pmd_val(pmd)); 665 666 return pte_pfn(pte); 667 } 668 669 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 670 static inline unsigned long pmd_dirty(pmd_t pmd) 671 { 672 pte_t pte = __pte(pmd_val(pmd)); 673 674 return pte_dirty(pte); 675 } 676 677 static inline unsigned long pmd_young(pmd_t pmd) 678 { 679 pte_t pte = __pte(pmd_val(pmd)); 680 681 return pte_young(pte); 682 } 683 684 static inline unsigned long pmd_write(pmd_t pmd) 685 { 686 pte_t pte = __pte(pmd_val(pmd)); 687 688 return pte_write(pte); 689 } 690 691 static inline unsigned long pmd_trans_huge(pmd_t pmd) 692 { 693 pte_t pte = __pte(pmd_val(pmd)); 694 695 return pte_val(pte) & _PAGE_PMD_HUGE; 696 } 697 698 static inline unsigned long pmd_trans_splitting(pmd_t pmd) 699 { 700 pte_t pte = __pte(pmd_val(pmd)); 701 702 return pmd_trans_huge(pmd) && pte_special(pte); 703 } 704 705 #define has_transparent_hugepage() 1 706 707 static inline pmd_t pmd_mkold(pmd_t pmd) 708 { 709 pte_t pte = __pte(pmd_val(pmd)); 710 711 pte = pte_mkold(pte); 712 713 return __pmd(pte_val(pte)); 714 } 715 716 static inline pmd_t pmd_wrprotect(pmd_t pmd) 717 { 718 pte_t pte = __pte(pmd_val(pmd)); 719 720 pte = pte_wrprotect(pte); 721 722 return __pmd(pte_val(pte)); 723 } 724 725 static inline pmd_t pmd_mkdirty(pmd_t pmd) 726 { 727 pte_t pte = __pte(pmd_val(pmd)); 728 729 pte = pte_mkdirty(pte); 730 731 return __pmd(pte_val(pte)); 732 } 733 734 static inline pmd_t pmd_mkyoung(pmd_t pmd) 735 { 736 pte_t pte = __pte(pmd_val(pmd)); 737 738 pte = pte_mkyoung(pte); 739 740 return __pmd(pte_val(pte)); 741 } 742 743 static inline pmd_t pmd_mkwrite(pmd_t pmd) 744 { 745 pte_t pte = __pte(pmd_val(pmd)); 746 747 pte = pte_mkwrite(pte); 748 749 return __pmd(pte_val(pte)); 750 } 751 752 static inline pmd_t pmd_mksplitting(pmd_t pmd) 753 { 754 pte_t pte = __pte(pmd_val(pmd)); 755 756 pte = pte_mkspecial(pte); 757 758 return __pmd(pte_val(pte)); 759 } 760 761 static inline pgprot_t pmd_pgprot(pmd_t entry) 762 { 763 unsigned long val = pmd_val(entry); 764 765 return __pgprot(val); 766 } 767 #endif 768 769 static inline int pmd_present(pmd_t pmd) 770 { 771 return pmd_val(pmd) != 0UL; 772 } 773 774 #define pmd_none(pmd) (!pmd_val(pmd)) 775 776 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is 777 * very simple, it's just the physical address. PTE tables are of 778 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and 779 * the top bits outside of the range of any physical address size we 780 * support are clear as well. We also validate the physical itself. 781 */ 782 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 783 784 #define pud_none(pud) (!pud_val(pud)) 785 786 #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) 787 788 #define pgd_none(pgd) (!pgd_val(pgd)) 789 790 #define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK) 791 792 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 793 void set_pmd_at(struct mm_struct *mm, unsigned long addr, 794 pmd_t *pmdp, pmd_t pmd); 795 #else 796 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 797 pmd_t *pmdp, pmd_t pmd) 798 { 799 *pmdp = pmd; 800 } 801 #endif 802 803 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 804 { 805 unsigned long val = __pa((unsigned long) (ptep)); 806 807 pmd_val(*pmdp) = val; 808 } 809 810 #define pud_set(pudp, pmdp) \ 811 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 812 static inline unsigned long __pmd_page(pmd_t pmd) 813 { 814 pte_t pte = __pte(pmd_val(pmd)); 815 unsigned long pfn; 816 817 pfn = pte_pfn(pte); 818 819 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 820 } 821 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 822 #define pud_page_vaddr(pud) \ 823 ((unsigned long) __va(pud_val(pud))) 824 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 825 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 826 #define pud_present(pud) (pud_val(pud) != 0U) 827 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 828 #define pgd_page_vaddr(pgd) \ 829 ((unsigned long) __va(pgd_val(pgd))) 830 #define pgd_present(pgd) (pgd_val(pgd) != 0U) 831 #define pgd_clear(pgdp) (pgd_val(*(pgd)) = 0UL) 832 833 static inline unsigned long pud_large(pud_t pud) 834 { 835 pte_t pte = __pte(pud_val(pud)); 836 837 return pte_val(pte) & _PAGE_PMD_HUGE; 838 } 839 840 static inline unsigned long pud_pfn(pud_t pud) 841 { 842 pte_t pte = __pte(pud_val(pud)); 843 844 return pte_pfn(pte); 845 } 846 847 /* Same in both SUN4V and SUN4U. */ 848 #define pte_none(pte) (!pte_val(pte)) 849 850 #define pgd_set(pgdp, pudp) \ 851 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp)))) 852 853 /* to find an entry in a page-table-directory. */ 854 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 855 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 856 857 /* to find an entry in a kernel page-table-directory */ 858 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 859 860 /* Find an entry in the third-level page table.. */ 861 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 862 #define pud_offset(pgdp, address) \ 863 ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address)) 864 865 /* Find an entry in the second-level page table.. */ 866 #define pmd_offset(pudp, address) \ 867 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 868 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 869 870 /* Find an entry in the third-level page table.. */ 871 #define pte_index(dir, address) \ 872 ((pte_t *) __pmd_page(*(dir)) + \ 873 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 874 #define pte_offset_kernel pte_index 875 #define pte_offset_map pte_index 876 #define pte_unmap(pte) do { } while (0) 877 878 /* Actual page table PTE updates. */ 879 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 880 pte_t *ptep, pte_t orig, int fullmm); 881 882 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 883 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 884 unsigned long addr, 885 pmd_t *pmdp) 886 { 887 pmd_t pmd = *pmdp; 888 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 889 return pmd; 890 } 891 892 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 893 pte_t *ptep, pte_t pte, int fullmm) 894 { 895 pte_t orig = *ptep; 896 897 *ptep = pte; 898 899 /* It is more efficient to let flush_tlb_kernel_range() 900 * handle init_mm tlb flushes. 901 * 902 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 903 * and SUN4V pte layout, so this inline test is fine. 904 */ 905 if (likely(mm != &init_mm) && pte_accessible(mm, orig)) 906 tlb_batch_add(mm, addr, ptep, orig, fullmm); 907 } 908 909 #define set_pte_at(mm,addr,ptep,pte) \ 910 __set_pte_at((mm), (addr), (ptep), (pte), 0) 911 912 #define pte_clear(mm,addr,ptep) \ 913 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 914 915 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 916 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 917 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 918 919 #ifdef DCACHE_ALIASING_POSSIBLE 920 #define __HAVE_ARCH_MOVE_PTE 921 #define move_pte(pte, prot, old_addr, new_addr) \ 922 ({ \ 923 pte_t newpte = (pte); \ 924 if (tlb_type != hypervisor && pte_present(pte)) { \ 925 unsigned long this_pfn = pte_pfn(pte); \ 926 \ 927 if (pfn_valid(this_pfn) && \ 928 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 929 flush_dcache_page_all(current->mm, \ 930 pfn_to_page(this_pfn)); \ 931 } \ 932 newpte; \ 933 }) 934 #endif 935 936 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 937 938 void paging_init(void); 939 unsigned long find_ecache_flush_span(unsigned long size); 940 941 struct seq_file; 942 void mmu_info(struct seq_file *); 943 944 struct vm_area_struct; 945 void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 946 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 947 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 948 pmd_t *pmd); 949 950 #define __HAVE_ARCH_PMDP_INVALIDATE 951 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 952 pmd_t *pmdp); 953 954 #define __HAVE_ARCH_PGTABLE_DEPOSIT 955 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 956 pgtable_t pgtable); 957 958 #define __HAVE_ARCH_PGTABLE_WITHDRAW 959 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 960 #endif 961 962 /* Encode and de-code a swap entry */ 963 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 964 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 965 #define __swp_entry(type, offset) \ 966 ( (swp_entry_t) \ 967 { \ 968 (((long)(type) << PAGE_SHIFT) | \ 969 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 970 } ) 971 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 972 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 973 974 /* File offset in PTE support. */ 975 unsigned long pte_file(pte_t); 976 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) 977 pte_t pgoff_to_pte(unsigned long); 978 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) 979 980 int page_in_phys_avail(unsigned long paddr); 981 982 /* 983 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 984 * its high 4 bits. These macros/functions put it there or get it from there. 985 */ 986 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 987 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 988 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 989 990 int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 991 unsigned long, pgprot_t); 992 993 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 994 unsigned long from, unsigned long pfn, 995 unsigned long size, pgprot_t prot) 996 { 997 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 998 int space = GET_IOSPACE(pfn); 999 unsigned long phys_base; 1000 1001 phys_base = offset | (((unsigned long) space) << 32UL); 1002 1003 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 1004 } 1005 #define io_remap_pfn_range io_remap_pfn_range 1006 1007 #include <asm/tlbflush.h> 1008 #include <asm-generic/pgtable.h> 1009 1010 /* We provide our own get_unmapped_area to cope with VA holes and 1011 * SHM area cache aliasing for userland. 1012 */ 1013 #define HAVE_ARCH_UNMAPPED_AREA 1014 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1015 1016 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 1017 * the largest alignment possible such that larget PTEs can be used. 1018 */ 1019 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 1020 unsigned long, unsigned long, 1021 unsigned long); 1022 #define HAVE_ARCH_FB_UNMAPPED_AREA 1023 1024 void pgtable_cache_init(void); 1025 void sun4v_register_fault_status(void); 1026 void sun4v_ktsb_register(void); 1027 void __init cheetah_ecache_flush_init(void); 1028 void sun4v_patch_tlb_handlers(void); 1029 1030 extern unsigned long cmdline_memory_size; 1031 1032 asmlinkage void do_sparc64_fault(struct pt_regs *regs); 1033 1034 #endif /* !(__ASSEMBLY__) */ 1035 1036 #endif /* !(_SPARC64_PGTABLE_H) */ 1037