1 /* 2 * pgtable.h: SpitFire page table operations. 3 * 4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #ifndef _SPARC64_PGTABLE_H 9 #define _SPARC64_PGTABLE_H 10 11 /* This file contains the functions and defines necessary to modify and use 12 * the SpitFire page tables. 13 */ 14 15 #include <asm-generic/5level-fixup.h> 16 #include <linux/compiler.h> 17 #include <linux/const.h> 18 #include <asm/types.h> 19 #include <asm/spitfire.h> 20 #include <asm/asi.h> 21 #include <asm/page.h> 22 #include <asm/processor.h> 23 24 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 25 * The page copy blockops can use 0x6000000 to 0x8000000. 26 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. 27 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. 28 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 29 * The vmalloc area spans 0x100000000 to 0x200000000. 30 * Since modules need to be in the lowest 32-bits of the address space, 31 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 32 * There is a single static kernel PMD which maps from 0x0 to address 33 * 0x400000000. 34 */ 35 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 36 #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) 37 #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) 38 #define MODULES_VADDR _AC(0x0000000010000000,UL) 39 #define MODULES_LEN _AC(0x00000000e0000000,UL) 40 #define MODULES_END _AC(0x00000000f0000000,UL) 41 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 42 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 43 #define VMALLOC_START _AC(0x0000000100000000,UL) 44 #define VMEMMAP_BASE VMALLOC_END 45 46 /* PMD_SHIFT determines the size of the area a second-level page 47 * table can map 48 */ 49 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 50 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 51 #define PMD_MASK (~(PMD_SIZE-1)) 52 #define PMD_BITS (PAGE_SHIFT - 3) 53 54 /* PUD_SHIFT determines the size of the area a third-level page 55 * table can map 56 */ 57 #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) 58 #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) 59 #define PUD_MASK (~(PUD_SIZE-1)) 60 #define PUD_BITS (PAGE_SHIFT - 3) 61 62 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 63 #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) 64 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 65 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 66 #define PGDIR_BITS (PAGE_SHIFT - 3) 67 68 #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) 69 #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support 70 #endif 71 72 #if (PGDIR_SHIFT + PGDIR_BITS) != 53 73 #error Page table parameters do not cover virtual address space properly. 74 #endif 75 76 #if (PMD_SHIFT != HPAGE_SHIFT) 77 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 78 #endif 79 80 #ifndef __ASSEMBLY__ 81 82 extern unsigned long VMALLOC_END; 83 84 #define vmemmap ((struct page *)VMEMMAP_BASE) 85 86 #include <linux/sched.h> 87 88 bool kern_addr_valid(unsigned long addr); 89 90 /* Entries per page directory level. */ 91 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 92 #define PTRS_PER_PMD (1UL << PMD_BITS) 93 #define PTRS_PER_PUD (1UL << PUD_BITS) 94 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 95 96 /* Kernel has a separate 44bit address space. */ 97 #define FIRST_USER_ADDRESS 0UL 98 99 #define pmd_ERROR(e) \ 100 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ 101 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) 102 #define pud_ERROR(e) \ 103 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ 104 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) 105 #define pgd_ERROR(e) \ 106 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ 107 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) 108 109 #endif /* !(__ASSEMBLY__) */ 110 111 /* PTE bits which are the same in SUN4U and SUN4V format. */ 112 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 113 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 114 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 115 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 116 #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE 117 118 /* Advertise support for _PAGE_SPECIAL */ 119 #define __HAVE_ARCH_PTE_SPECIAL 120 121 /* SUN4U pte bits... */ 122 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 123 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 124 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 125 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 126 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 127 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 128 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 129 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 130 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 131 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 132 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 133 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 134 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 135 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 136 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 137 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 138 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 139 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 140 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 141 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 142 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 143 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 144 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 145 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 146 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 147 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 148 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 149 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 150 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 151 152 /* SUN4V pte bits... */ 153 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 154 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 155 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 156 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 157 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 158 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 159 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 160 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 161 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 162 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 163 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 164 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 165 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 166 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 167 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 168 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 169 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 170 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 171 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 172 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 173 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 174 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 175 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 176 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 177 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 178 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 179 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 180 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 181 182 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 183 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 184 185 #if REAL_HPAGE_SHIFT != 22 186 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 187 #endif 188 189 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 190 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 191 192 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 193 #define __P000 __pgprot(0) 194 #define __P001 __pgprot(0) 195 #define __P010 __pgprot(0) 196 #define __P011 __pgprot(0) 197 #define __P100 __pgprot(0) 198 #define __P101 __pgprot(0) 199 #define __P110 __pgprot(0) 200 #define __P111 __pgprot(0) 201 202 #define __S000 __pgprot(0) 203 #define __S001 __pgprot(0) 204 #define __S010 __pgprot(0) 205 #define __S011 __pgprot(0) 206 #define __S100 __pgprot(0) 207 #define __S101 __pgprot(0) 208 #define __S110 __pgprot(0) 209 #define __S111 __pgprot(0) 210 211 #ifndef __ASSEMBLY__ 212 213 pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 214 215 unsigned long pte_sz_bits(unsigned long size); 216 217 extern pgprot_t PAGE_KERNEL; 218 extern pgprot_t PAGE_KERNEL_LOCKED; 219 extern pgprot_t PAGE_COPY; 220 extern pgprot_t PAGE_SHARED; 221 222 /* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */ 223 extern unsigned long _PAGE_IE; 224 extern unsigned long _PAGE_E; 225 extern unsigned long _PAGE_CACHE; 226 227 extern unsigned long pg_iobits; 228 extern unsigned long _PAGE_ALL_SZ_BITS; 229 230 extern struct page *mem_map_zero; 231 #define ZERO_PAGE(vaddr) (mem_map_zero) 232 233 /* PFNs are real physical page numbers. However, mem_map only begins to record 234 * per-page information starting at pfn_base. This is to handle systems where 235 * the first physical page in the machine is at some huge physical address, 236 * such as 4GB. This is common on a partitioned E10000, for example. 237 */ 238 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 239 { 240 unsigned long paddr = pfn << PAGE_SHIFT; 241 242 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 243 return __pte(paddr | pgprot_val(prot)); 244 } 245 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 246 247 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 248 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 249 { 250 pte_t pte = pfn_pte(page_nr, pgprot); 251 252 return __pmd(pte_val(pte)); 253 } 254 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 255 #endif 256 257 /* This one can be done with two shifts. */ 258 static inline unsigned long pte_pfn(pte_t pte) 259 { 260 unsigned long ret; 261 262 __asm__ __volatile__( 263 "\n661: sllx %1, %2, %0\n" 264 " srlx %0, %3, %0\n" 265 " .section .sun4v_2insn_patch, \"ax\"\n" 266 " .word 661b\n" 267 " sllx %1, %4, %0\n" 268 " srlx %0, %5, %0\n" 269 " .previous\n" 270 : "=r" (ret) 271 : "r" (pte_val(pte)), 272 "i" (21), "i" (21 + PAGE_SHIFT), 273 "i" (8), "i" (8 + PAGE_SHIFT)); 274 275 return ret; 276 } 277 #define pte_page(x) pfn_to_page(pte_pfn(x)) 278 279 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 280 { 281 unsigned long mask, tmp; 282 283 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) 284 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) 285 * 286 * Even if we use negation tricks the result is still a 6 287 * instruction sequence, so don't try to play fancy and just 288 * do the most straightforward implementation. 289 * 290 * Note: We encode this into 3 sun4v 2-insn patch sequences. 291 */ 292 293 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 294 __asm__ __volatile__( 295 "\n661: sethi %%uhi(%2), %1\n" 296 " sethi %%hi(%2), %0\n" 297 "\n662: or %1, %%ulo(%2), %1\n" 298 " or %0, %%lo(%2), %0\n" 299 "\n663: sllx %1, 32, %1\n" 300 " or %0, %1, %0\n" 301 " .section .sun4v_2insn_patch, \"ax\"\n" 302 " .word 661b\n" 303 " sethi %%uhi(%3), %1\n" 304 " sethi %%hi(%3), %0\n" 305 " .word 662b\n" 306 " or %1, %%ulo(%3), %1\n" 307 " or %0, %%lo(%3), %0\n" 308 " .word 663b\n" 309 " sllx %1, 32, %1\n" 310 " or %0, %1, %0\n" 311 " .previous\n" 312 " .section .sun_m7_2insn_patch, \"ax\"\n" 313 " .word 661b\n" 314 " sethi %%uhi(%4), %1\n" 315 " sethi %%hi(%4), %0\n" 316 " .word 662b\n" 317 " or %1, %%ulo(%4), %1\n" 318 " or %0, %%lo(%4), %0\n" 319 " .word 663b\n" 320 " sllx %1, 32, %1\n" 321 " or %0, %1, %0\n" 322 " .previous\n" 323 : "=r" (mask), "=r" (tmp) 324 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 325 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | 326 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 327 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 328 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | 329 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V), 330 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 331 _PAGE_CP_4V | _PAGE_E_4V | 332 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 333 334 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 335 } 336 337 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 338 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 339 { 340 pte_t pte = __pte(pmd_val(pmd)); 341 342 pte = pte_modify(pte, newprot); 343 344 return __pmd(pte_val(pte)); 345 } 346 #endif 347 348 static inline pgprot_t pgprot_noncached(pgprot_t prot) 349 { 350 unsigned long val = pgprot_val(prot); 351 352 __asm__ __volatile__( 353 "\n661: andn %0, %2, %0\n" 354 " or %0, %3, %0\n" 355 " .section .sun4v_2insn_patch, \"ax\"\n" 356 " .word 661b\n" 357 " andn %0, %4, %0\n" 358 " or %0, %5, %0\n" 359 " .previous\n" 360 " .section .sun_m7_2insn_patch, \"ax\"\n" 361 " .word 661b\n" 362 " andn %0, %6, %0\n" 363 " or %0, %5, %0\n" 364 " .previous\n" 365 : "=r" (val) 366 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 367 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V), 368 "i" (_PAGE_CP_4V)); 369 370 return __pgprot(val); 371 } 372 /* Various pieces of code check for platform support by ifdef testing 373 * on "pgprot_noncached". That's broken and should be fixed, but for 374 * now... 375 */ 376 #define pgprot_noncached pgprot_noncached 377 378 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 379 extern pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, 380 struct page *page, int writable); 381 #define arch_make_huge_pte arch_make_huge_pte 382 static inline unsigned long __pte_default_huge_mask(void) 383 { 384 unsigned long mask; 385 386 __asm__ __volatile__( 387 "\n661: sethi %%uhi(%1), %0\n" 388 " sllx %0, 32, %0\n" 389 " .section .sun4v_2insn_patch, \"ax\"\n" 390 " .word 661b\n" 391 " mov %2, %0\n" 392 " nop\n" 393 " .previous\n" 394 : "=r" (mask) 395 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 396 397 return mask; 398 } 399 400 static inline pte_t pte_mkhuge(pte_t pte) 401 { 402 return __pte(pte_val(pte) | __pte_default_huge_mask()); 403 } 404 405 static inline bool is_default_hugetlb_pte(pte_t pte) 406 { 407 unsigned long mask = __pte_default_huge_mask(); 408 409 return (pte_val(pte) & mask) == mask; 410 } 411 412 static inline bool is_hugetlb_pmd(pmd_t pmd) 413 { 414 return !!(pmd_val(pmd) & _PAGE_PMD_HUGE); 415 } 416 417 static inline bool is_hugetlb_pud(pud_t pud) 418 { 419 return !!(pud_val(pud) & _PAGE_PUD_HUGE); 420 } 421 422 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 423 static inline pmd_t pmd_mkhuge(pmd_t pmd) 424 { 425 pte_t pte = __pte(pmd_val(pmd)); 426 427 pte = pte_mkhuge(pte); 428 pte_val(pte) |= _PAGE_PMD_HUGE; 429 430 return __pmd(pte_val(pte)); 431 } 432 #endif 433 #else 434 static inline bool is_hugetlb_pte(pte_t pte) 435 { 436 return false; 437 } 438 #endif 439 440 static inline pte_t pte_mkdirty(pte_t pte) 441 { 442 unsigned long val = pte_val(pte), tmp; 443 444 __asm__ __volatile__( 445 "\n661: or %0, %3, %0\n" 446 " nop\n" 447 "\n662: nop\n" 448 " nop\n" 449 " .section .sun4v_2insn_patch, \"ax\"\n" 450 " .word 661b\n" 451 " sethi %%uhi(%4), %1\n" 452 " sllx %1, 32, %1\n" 453 " .word 662b\n" 454 " or %1, %%lo(%4), %1\n" 455 " or %0, %1, %0\n" 456 " .previous\n" 457 : "=r" (val), "=r" (tmp) 458 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 459 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 460 461 return __pte(val); 462 } 463 464 static inline pte_t pte_mkclean(pte_t pte) 465 { 466 unsigned long val = pte_val(pte), tmp; 467 468 __asm__ __volatile__( 469 "\n661: andn %0, %3, %0\n" 470 " nop\n" 471 "\n662: nop\n" 472 " nop\n" 473 " .section .sun4v_2insn_patch, \"ax\"\n" 474 " .word 661b\n" 475 " sethi %%uhi(%4), %1\n" 476 " sllx %1, 32, %1\n" 477 " .word 662b\n" 478 " or %1, %%lo(%4), %1\n" 479 " andn %0, %1, %0\n" 480 " .previous\n" 481 : "=r" (val), "=r" (tmp) 482 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 483 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 484 485 return __pte(val); 486 } 487 488 static inline pte_t pte_mkwrite(pte_t pte) 489 { 490 unsigned long val = pte_val(pte), mask; 491 492 __asm__ __volatile__( 493 "\n661: mov %1, %0\n" 494 " nop\n" 495 " .section .sun4v_2insn_patch, \"ax\"\n" 496 " .word 661b\n" 497 " sethi %%uhi(%2), %0\n" 498 " sllx %0, 32, %0\n" 499 " .previous\n" 500 : "=r" (mask) 501 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 502 503 return __pte(val | mask); 504 } 505 506 static inline pte_t pte_wrprotect(pte_t pte) 507 { 508 unsigned long val = pte_val(pte), tmp; 509 510 __asm__ __volatile__( 511 "\n661: andn %0, %3, %0\n" 512 " nop\n" 513 "\n662: nop\n" 514 " nop\n" 515 " .section .sun4v_2insn_patch, \"ax\"\n" 516 " .word 661b\n" 517 " sethi %%uhi(%4), %1\n" 518 " sllx %1, 32, %1\n" 519 " .word 662b\n" 520 " or %1, %%lo(%4), %1\n" 521 " andn %0, %1, %0\n" 522 " .previous\n" 523 : "=r" (val), "=r" (tmp) 524 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 525 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 526 527 return __pte(val); 528 } 529 530 static inline pte_t pte_mkold(pte_t pte) 531 { 532 unsigned long mask; 533 534 __asm__ __volatile__( 535 "\n661: mov %1, %0\n" 536 " nop\n" 537 " .section .sun4v_2insn_patch, \"ax\"\n" 538 " .word 661b\n" 539 " sethi %%uhi(%2), %0\n" 540 " sllx %0, 32, %0\n" 541 " .previous\n" 542 : "=r" (mask) 543 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 544 545 mask |= _PAGE_R; 546 547 return __pte(pte_val(pte) & ~mask); 548 } 549 550 static inline pte_t pte_mkyoung(pte_t pte) 551 { 552 unsigned long mask; 553 554 __asm__ __volatile__( 555 "\n661: mov %1, %0\n" 556 " nop\n" 557 " .section .sun4v_2insn_patch, \"ax\"\n" 558 " .word 661b\n" 559 " sethi %%uhi(%2), %0\n" 560 " sllx %0, 32, %0\n" 561 " .previous\n" 562 : "=r" (mask) 563 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 564 565 mask |= _PAGE_R; 566 567 return __pte(pte_val(pte) | mask); 568 } 569 570 static inline pte_t pte_mkspecial(pte_t pte) 571 { 572 pte_val(pte) |= _PAGE_SPECIAL; 573 return pte; 574 } 575 576 static inline unsigned long pte_young(pte_t pte) 577 { 578 unsigned long mask; 579 580 __asm__ __volatile__( 581 "\n661: mov %1, %0\n" 582 " nop\n" 583 " .section .sun4v_2insn_patch, \"ax\"\n" 584 " .word 661b\n" 585 " sethi %%uhi(%2), %0\n" 586 " sllx %0, 32, %0\n" 587 " .previous\n" 588 : "=r" (mask) 589 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 590 591 return (pte_val(pte) & mask); 592 } 593 594 static inline unsigned long pte_dirty(pte_t pte) 595 { 596 unsigned long mask; 597 598 __asm__ __volatile__( 599 "\n661: mov %1, %0\n" 600 " nop\n" 601 " .section .sun4v_2insn_patch, \"ax\"\n" 602 " .word 661b\n" 603 " sethi %%uhi(%2), %0\n" 604 " sllx %0, 32, %0\n" 605 " .previous\n" 606 : "=r" (mask) 607 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 608 609 return (pte_val(pte) & mask); 610 } 611 612 static inline unsigned long pte_write(pte_t pte) 613 { 614 unsigned long mask; 615 616 __asm__ __volatile__( 617 "\n661: mov %1, %0\n" 618 " nop\n" 619 " .section .sun4v_2insn_patch, \"ax\"\n" 620 " .word 661b\n" 621 " sethi %%uhi(%2), %0\n" 622 " sllx %0, 32, %0\n" 623 " .previous\n" 624 : "=r" (mask) 625 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 626 627 return (pte_val(pte) & mask); 628 } 629 630 static inline unsigned long pte_exec(pte_t pte) 631 { 632 unsigned long mask; 633 634 __asm__ __volatile__( 635 "\n661: sethi %%hi(%1), %0\n" 636 " .section .sun4v_1insn_patch, \"ax\"\n" 637 " .word 661b\n" 638 " mov %2, %0\n" 639 " .previous\n" 640 : "=r" (mask) 641 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 642 643 return (pte_val(pte) & mask); 644 } 645 646 static inline unsigned long pte_present(pte_t pte) 647 { 648 unsigned long val = pte_val(pte); 649 650 __asm__ __volatile__( 651 "\n661: and %0, %2, %0\n" 652 " .section .sun4v_1insn_patch, \"ax\"\n" 653 " .word 661b\n" 654 " and %0, %3, %0\n" 655 " .previous\n" 656 : "=r" (val) 657 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 658 659 return val; 660 } 661 662 #define pte_accessible pte_accessible 663 static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) 664 { 665 return pte_val(a) & _PAGE_VALID; 666 } 667 668 static inline unsigned long pte_special(pte_t pte) 669 { 670 return pte_val(pte) & _PAGE_SPECIAL; 671 } 672 673 static inline unsigned long pmd_large(pmd_t pmd) 674 { 675 pte_t pte = __pte(pmd_val(pmd)); 676 677 return pte_val(pte) & _PAGE_PMD_HUGE; 678 } 679 680 static inline unsigned long pmd_pfn(pmd_t pmd) 681 { 682 pte_t pte = __pte(pmd_val(pmd)); 683 684 return pte_pfn(pte); 685 } 686 687 #define __HAVE_ARCH_PMD_WRITE 688 static inline unsigned long pmd_write(pmd_t pmd) 689 { 690 pte_t pte = __pte(pmd_val(pmd)); 691 692 return pte_write(pte); 693 } 694 695 #define pud_write(pud) pte_write(__pte(pud_val(pud))) 696 697 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 698 static inline unsigned long pmd_dirty(pmd_t pmd) 699 { 700 pte_t pte = __pte(pmd_val(pmd)); 701 702 return pte_dirty(pte); 703 } 704 705 static inline unsigned long pmd_young(pmd_t pmd) 706 { 707 pte_t pte = __pte(pmd_val(pmd)); 708 709 return pte_young(pte); 710 } 711 712 static inline unsigned long pmd_trans_huge(pmd_t pmd) 713 { 714 pte_t pte = __pte(pmd_val(pmd)); 715 716 return pte_val(pte) & _PAGE_PMD_HUGE; 717 } 718 719 static inline pmd_t pmd_mkold(pmd_t pmd) 720 { 721 pte_t pte = __pte(pmd_val(pmd)); 722 723 pte = pte_mkold(pte); 724 725 return __pmd(pte_val(pte)); 726 } 727 728 static inline pmd_t pmd_wrprotect(pmd_t pmd) 729 { 730 pte_t pte = __pte(pmd_val(pmd)); 731 732 pte = pte_wrprotect(pte); 733 734 return __pmd(pte_val(pte)); 735 } 736 737 static inline pmd_t pmd_mkdirty(pmd_t pmd) 738 { 739 pte_t pte = __pte(pmd_val(pmd)); 740 741 pte = pte_mkdirty(pte); 742 743 return __pmd(pte_val(pte)); 744 } 745 746 static inline pmd_t pmd_mkclean(pmd_t pmd) 747 { 748 pte_t pte = __pte(pmd_val(pmd)); 749 750 pte = pte_mkclean(pte); 751 752 return __pmd(pte_val(pte)); 753 } 754 755 static inline pmd_t pmd_mkyoung(pmd_t pmd) 756 { 757 pte_t pte = __pte(pmd_val(pmd)); 758 759 pte = pte_mkyoung(pte); 760 761 return __pmd(pte_val(pte)); 762 } 763 764 static inline pmd_t pmd_mkwrite(pmd_t pmd) 765 { 766 pte_t pte = __pte(pmd_val(pmd)); 767 768 pte = pte_mkwrite(pte); 769 770 return __pmd(pte_val(pte)); 771 } 772 773 static inline pgprot_t pmd_pgprot(pmd_t entry) 774 { 775 unsigned long val = pmd_val(entry); 776 777 return __pgprot(val); 778 } 779 #endif 780 781 static inline int pmd_present(pmd_t pmd) 782 { 783 return pmd_val(pmd) != 0UL; 784 } 785 786 #define pmd_none(pmd) (!pmd_val(pmd)) 787 788 /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is 789 * very simple, it's just the physical address. PTE tables are of 790 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and 791 * the top bits outside of the range of any physical address size we 792 * support are clear as well. We also validate the physical itself. 793 */ 794 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 795 796 #define pud_none(pud) (!pud_val(pud)) 797 798 #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) 799 800 #define pgd_none(pgd) (!pgd_val(pgd)) 801 802 #define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK) 803 804 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 805 void set_pmd_at(struct mm_struct *mm, unsigned long addr, 806 pmd_t *pmdp, pmd_t pmd); 807 #else 808 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 809 pmd_t *pmdp, pmd_t pmd) 810 { 811 *pmdp = pmd; 812 } 813 #endif 814 815 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 816 { 817 unsigned long val = __pa((unsigned long) (ptep)); 818 819 pmd_val(*pmdp) = val; 820 } 821 822 #define pud_set(pudp, pmdp) \ 823 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 824 static inline unsigned long __pmd_page(pmd_t pmd) 825 { 826 pte_t pte = __pte(pmd_val(pmd)); 827 unsigned long pfn; 828 829 pfn = pte_pfn(pte); 830 831 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 832 } 833 834 static inline unsigned long pud_page_vaddr(pud_t pud) 835 { 836 pte_t pte = __pte(pud_val(pud)); 837 unsigned long pfn; 838 839 pfn = pte_pfn(pte); 840 841 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 842 } 843 844 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 845 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 846 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 847 #define pud_present(pud) (pud_val(pud) != 0U) 848 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 849 #define pgd_page_vaddr(pgd) \ 850 ((unsigned long) __va(pgd_val(pgd))) 851 #define pgd_present(pgd) (pgd_val(pgd) != 0U) 852 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) 853 854 static inline unsigned long pud_large(pud_t pud) 855 { 856 pte_t pte = __pte(pud_val(pud)); 857 858 return pte_val(pte) & _PAGE_PMD_HUGE; 859 } 860 861 static inline unsigned long pud_pfn(pud_t pud) 862 { 863 pte_t pte = __pte(pud_val(pud)); 864 865 return pte_pfn(pte); 866 } 867 868 /* Same in both SUN4V and SUN4U. */ 869 #define pte_none(pte) (!pte_val(pte)) 870 871 #define pgd_set(pgdp, pudp) \ 872 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp)))) 873 874 /* to find an entry in a page-table-directory. */ 875 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 876 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 877 878 /* to find an entry in a kernel page-table-directory */ 879 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 880 881 /* Find an entry in the third-level page table.. */ 882 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 883 #define pud_offset(pgdp, address) \ 884 ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address)) 885 886 /* Find an entry in the second-level page table.. */ 887 #define pmd_offset(pudp, address) \ 888 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 889 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 890 891 /* Find an entry in the third-level page table.. */ 892 #define pte_index(dir, address) \ 893 ((pte_t *) __pmd_page(*(dir)) + \ 894 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 895 #define pte_offset_kernel pte_index 896 #define pte_offset_map pte_index 897 #define pte_unmap(pte) do { } while (0) 898 899 /* We cannot include <linux/mm_types.h> at this point yet: */ 900 extern struct mm_struct init_mm; 901 902 /* Actual page table PTE updates. */ 903 void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 904 pte_t *ptep, pte_t orig, int fullmm, 905 unsigned int hugepage_shift); 906 907 static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 908 pte_t *ptep, pte_t orig, int fullmm, 909 unsigned int hugepage_shift) 910 { 911 /* It is more efficient to let flush_tlb_kernel_range() 912 * handle init_mm tlb flushes. 913 * 914 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 915 * and SUN4V pte layout, so this inline test is fine. 916 */ 917 if (likely(mm != &init_mm) && pte_accessible(mm, orig)) 918 tlb_batch_add(mm, vaddr, ptep, orig, fullmm, hugepage_shift); 919 } 920 921 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 922 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 923 unsigned long addr, 924 pmd_t *pmdp) 925 { 926 pmd_t pmd = *pmdp; 927 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 928 return pmd; 929 } 930 931 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 932 pte_t *ptep, pte_t pte, int fullmm) 933 { 934 pte_t orig = *ptep; 935 936 *ptep = pte; 937 maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm, PAGE_SHIFT); 938 } 939 940 #define set_pte_at(mm,addr,ptep,pte) \ 941 __set_pte_at((mm), (addr), (ptep), (pte), 0) 942 943 #define pte_clear(mm,addr,ptep) \ 944 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 945 946 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 947 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 948 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 949 950 #ifdef DCACHE_ALIASING_POSSIBLE 951 #define __HAVE_ARCH_MOVE_PTE 952 #define move_pte(pte, prot, old_addr, new_addr) \ 953 ({ \ 954 pte_t newpte = (pte); \ 955 if (tlb_type != hypervisor && pte_present(pte)) { \ 956 unsigned long this_pfn = pte_pfn(pte); \ 957 \ 958 if (pfn_valid(this_pfn) && \ 959 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 960 flush_dcache_page_all(current->mm, \ 961 pfn_to_page(this_pfn)); \ 962 } \ 963 newpte; \ 964 }) 965 #endif 966 967 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 968 969 void paging_init(void); 970 unsigned long find_ecache_flush_span(unsigned long size); 971 972 struct seq_file; 973 void mmu_info(struct seq_file *); 974 975 struct vm_area_struct; 976 void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 977 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 978 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 979 pmd_t *pmd); 980 981 #define __HAVE_ARCH_PMDP_INVALIDATE 982 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 983 pmd_t *pmdp); 984 985 #define __HAVE_ARCH_PGTABLE_DEPOSIT 986 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 987 pgtable_t pgtable); 988 989 #define __HAVE_ARCH_PGTABLE_WITHDRAW 990 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 991 #endif 992 993 /* Encode and de-code a swap entry */ 994 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 995 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 996 #define __swp_entry(type, offset) \ 997 ( (swp_entry_t) \ 998 { \ 999 (((long)(type) << PAGE_SHIFT) | \ 1000 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 1001 } ) 1002 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1003 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1004 1005 int page_in_phys_avail(unsigned long paddr); 1006 1007 /* 1008 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 1009 * its high 4 bits. These macros/functions put it there or get it from there. 1010 */ 1011 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 1012 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 1013 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 1014 1015 int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 1016 unsigned long, pgprot_t); 1017 1018 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 1019 unsigned long from, unsigned long pfn, 1020 unsigned long size, pgprot_t prot) 1021 { 1022 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 1023 int space = GET_IOSPACE(pfn); 1024 unsigned long phys_base; 1025 1026 phys_base = offset | (((unsigned long) space) << 32UL); 1027 1028 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 1029 } 1030 #define io_remap_pfn_range io_remap_pfn_range 1031 1032 #include <asm/tlbflush.h> 1033 #include <asm-generic/pgtable.h> 1034 1035 /* We provide our own get_unmapped_area to cope with VA holes and 1036 * SHM area cache aliasing for userland. 1037 */ 1038 #define HAVE_ARCH_UNMAPPED_AREA 1039 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1040 1041 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 1042 * the largest alignment possible such that larget PTEs can be used. 1043 */ 1044 unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 1045 unsigned long, unsigned long, 1046 unsigned long); 1047 #define HAVE_ARCH_FB_UNMAPPED_AREA 1048 1049 void pgtable_cache_init(void); 1050 void sun4v_register_fault_status(void); 1051 void sun4v_ktsb_register(void); 1052 void __init cheetah_ecache_flush_init(void); 1053 void sun4v_patch_tlb_handlers(void); 1054 1055 extern unsigned long cmdline_memory_size; 1056 1057 asmlinkage void do_sparc64_fault(struct pt_regs *regs); 1058 1059 #endif /* !(__ASSEMBLY__) */ 1060 1061 #endif /* !(_SPARC64_PGTABLE_H) */ 1062