1 /* 2 * pgtable.h: SpitFire page table operations. 3 * 4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #ifndef _SPARC64_PGTABLE_H 9 #define _SPARC64_PGTABLE_H 10 11 /* This file contains the functions and defines necessary to modify and use 12 * the SpitFire page tables. 13 */ 14 15 #include <linux/compiler.h> 16 #include <linux/const.h> 17 #include <asm/types.h> 18 #include <asm/spitfire.h> 19 #include <asm/asi.h> 20 #include <asm/page.h> 21 #include <asm/processor.h> 22 23 #include <asm-generic/pgtable-nopud.h> 24 25 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 26 * The page copy blockops can use 0x6000000 to 0x8000000. 27 * The TSB is mapped in the 0x8000000 to 0xa000000 range. 28 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 29 * The vmalloc area spans 0x100000000 to 0x200000000. 30 * Since modules need to be in the lowest 32-bits of the address space, 31 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 32 * There is a single static kernel PMD which maps from 0x0 to address 33 * 0x400000000. 34 */ 35 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 36 #define TSBMAP_BASE _AC(0x0000000008000000,UL) 37 #define MODULES_VADDR _AC(0x0000000010000000,UL) 38 #define MODULES_LEN _AC(0x00000000e0000000,UL) 39 #define MODULES_END _AC(0x00000000f0000000,UL) 40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 42 #define VMALLOC_START _AC(0x0000000100000000,UL) 43 #define VMALLOC_END _AC(0x0000010000000000,UL) 44 #define VMEMMAP_BASE _AC(0x0000010000000000,UL) 45 46 #define vmemmap ((struct page *)VMEMMAP_BASE) 47 48 /* XXX All of this needs to be rethought so we can take advantage 49 * XXX cheetah's full 64-bit virtual address space, ie. no more hole 50 * XXX in the middle like on spitfire. -DaveM 51 */ 52 /* 53 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset 54 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte# 55 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page 56 * table is a single page long). The next higher PMD_BITS determine pmd# 57 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2) 58 * since the pmd entries are 4 bytes, and each pmd page is a single page 59 * long). Finally, the higher few bits determine pgde#. 60 */ 61 62 /* PMD_SHIFT determines the size of the area a second-level page 63 * table can map 64 */ 65 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 66 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 67 #define PMD_MASK (~(PMD_SIZE-1)) 68 #define PMD_BITS (PAGE_SHIFT - 2) 69 70 /* PGDIR_SHIFT determines what a third-level page table entry can map */ 71 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS) 72 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 73 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 74 #define PGDIR_BITS (PAGE_SHIFT - 2) 75 76 #ifndef __ASSEMBLY__ 77 78 #include <linux/sched.h> 79 80 /* Entries per page directory level. */ 81 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 82 #define PTRS_PER_PMD (1UL << PMD_BITS) 83 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 84 85 /* Kernel has a separate 44bit address space. */ 86 #define FIRST_USER_ADDRESS 0 87 88 #define pte_ERROR(e) __builtin_trap() 89 #define pmd_ERROR(e) __builtin_trap() 90 #define pgd_ERROR(e) __builtin_trap() 91 92 #endif /* !(__ASSEMBLY__) */ 93 94 /* PTE bits which are the same in SUN4U and SUN4V format. */ 95 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 96 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 97 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 98 99 /* Advertise support for _PAGE_SPECIAL */ 100 #define __HAVE_ARCH_PTE_SPECIAL 101 102 /* SUN4U pte bits... */ 103 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 104 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 105 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 106 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 107 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 108 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 109 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 110 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 111 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 112 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 113 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 114 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 115 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 116 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 117 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 118 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 119 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 120 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 121 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */ 122 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 123 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 124 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 125 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 126 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 127 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 128 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 129 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 130 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 131 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 132 133 /* SUN4V pte bits... */ 134 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 135 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 136 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 137 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 138 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 139 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 140 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 141 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 142 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 143 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 144 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 145 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 146 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 147 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 148 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 149 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 150 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */ 151 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 152 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 153 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 154 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 155 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 156 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 157 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 158 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 159 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 160 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 161 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 162 163 #if PAGE_SHIFT == 13 164 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 165 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 166 #elif PAGE_SHIFT == 16 167 #define _PAGE_SZBITS_4U _PAGE_SZ64K_4U 168 #define _PAGE_SZBITS_4V _PAGE_SZ64K_4V 169 #else 170 #error Wrong PAGE_SHIFT specified 171 #endif 172 173 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) 174 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 175 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 176 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) 177 #define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U 178 #define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V 179 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) 180 #define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U 181 #define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V 182 #endif 183 184 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 185 #define __P000 __pgprot(0) 186 #define __P001 __pgprot(0) 187 #define __P010 __pgprot(0) 188 #define __P011 __pgprot(0) 189 #define __P100 __pgprot(0) 190 #define __P101 __pgprot(0) 191 #define __P110 __pgprot(0) 192 #define __P111 __pgprot(0) 193 194 #define __S000 __pgprot(0) 195 #define __S001 __pgprot(0) 196 #define __S010 __pgprot(0) 197 #define __S011 __pgprot(0) 198 #define __S100 __pgprot(0) 199 #define __S101 __pgprot(0) 200 #define __S110 __pgprot(0) 201 #define __S111 __pgprot(0) 202 203 #ifndef __ASSEMBLY__ 204 205 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 206 207 extern unsigned long pte_sz_bits(unsigned long size); 208 209 extern pgprot_t PAGE_KERNEL; 210 extern pgprot_t PAGE_KERNEL_LOCKED; 211 extern pgprot_t PAGE_COPY; 212 extern pgprot_t PAGE_SHARED; 213 214 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */ 215 extern unsigned long _PAGE_IE; 216 extern unsigned long _PAGE_E; 217 extern unsigned long _PAGE_CACHE; 218 219 extern unsigned long pg_iobits; 220 extern unsigned long _PAGE_ALL_SZ_BITS; 221 extern unsigned long _PAGE_SZBITS; 222 223 extern struct page *mem_map_zero; 224 #define ZERO_PAGE(vaddr) (mem_map_zero) 225 226 /* PFNs are real physical page numbers. However, mem_map only begins to record 227 * per-page information starting at pfn_base. This is to handle systems where 228 * the first physical page in the machine is at some huge physical address, 229 * such as 4GB. This is common on a partitioned E10000, for example. 230 */ 231 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 232 { 233 unsigned long paddr = pfn << PAGE_SHIFT; 234 unsigned long sz_bits; 235 236 sz_bits = 0UL; 237 if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) { 238 __asm__ __volatile__( 239 "\n661: sethi %%uhi(%1), %0\n" 240 " sllx %0, 32, %0\n" 241 " .section .sun4v_2insn_patch, \"ax\"\n" 242 " .word 661b\n" 243 " mov %2, %0\n" 244 " nop\n" 245 " .previous\n" 246 : "=r" (sz_bits) 247 : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V)); 248 } 249 return __pte(paddr | sz_bits | pgprot_val(prot)); 250 } 251 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 252 253 /* This one can be done with two shifts. */ 254 static inline unsigned long pte_pfn(pte_t pte) 255 { 256 unsigned long ret; 257 258 __asm__ __volatile__( 259 "\n661: sllx %1, %2, %0\n" 260 " srlx %0, %3, %0\n" 261 " .section .sun4v_2insn_patch, \"ax\"\n" 262 " .word 661b\n" 263 " sllx %1, %4, %0\n" 264 " srlx %0, %5, %0\n" 265 " .previous\n" 266 : "=r" (ret) 267 : "r" (pte_val(pte)), 268 "i" (21), "i" (21 + PAGE_SHIFT), 269 "i" (8), "i" (8 + PAGE_SHIFT)); 270 271 return ret; 272 } 273 #define pte_page(x) pfn_to_page(pte_pfn(x)) 274 275 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 276 { 277 unsigned long mask, tmp; 278 279 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347) 280 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8) 281 * 282 * Even if we use negation tricks the result is still a 6 283 * instruction sequence, so don't try to play fancy and just 284 * do the most straightforward implementation. 285 * 286 * Note: We encode this into 3 sun4v 2-insn patch sequences. 287 */ 288 289 __asm__ __volatile__( 290 "\n661: sethi %%uhi(%2), %1\n" 291 " sethi %%hi(%2), %0\n" 292 "\n662: or %1, %%ulo(%2), %1\n" 293 " or %0, %%lo(%2), %0\n" 294 "\n663: sllx %1, 32, %1\n" 295 " or %0, %1, %0\n" 296 " .section .sun4v_2insn_patch, \"ax\"\n" 297 " .word 661b\n" 298 " sethi %%uhi(%3), %1\n" 299 " sethi %%hi(%3), %0\n" 300 " .word 662b\n" 301 " or %1, %%ulo(%3), %1\n" 302 " or %0, %%lo(%3), %0\n" 303 " .word 663b\n" 304 " sllx %1, 32, %1\n" 305 " or %0, %1, %0\n" 306 " .previous\n" 307 : "=r" (mask), "=r" (tmp) 308 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 309 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U | 310 _PAGE_SZBITS_4U | _PAGE_SPECIAL), 311 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 312 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V | 313 _PAGE_SZBITS_4V | _PAGE_SPECIAL)); 314 315 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 316 } 317 318 static inline pte_t pgoff_to_pte(unsigned long off) 319 { 320 off <<= PAGE_SHIFT; 321 322 __asm__ __volatile__( 323 "\n661: or %0, %2, %0\n" 324 " .section .sun4v_1insn_patch, \"ax\"\n" 325 " .word 661b\n" 326 " or %0, %3, %0\n" 327 " .previous\n" 328 : "=r" (off) 329 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 330 331 return __pte(off); 332 } 333 334 static inline pgprot_t pgprot_noncached(pgprot_t prot) 335 { 336 unsigned long val = pgprot_val(prot); 337 338 __asm__ __volatile__( 339 "\n661: andn %0, %2, %0\n" 340 " or %0, %3, %0\n" 341 " .section .sun4v_2insn_patch, \"ax\"\n" 342 " .word 661b\n" 343 " andn %0, %4, %0\n" 344 " or %0, %5, %0\n" 345 " .previous\n" 346 : "=r" (val) 347 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 348 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V)); 349 350 return __pgprot(val); 351 } 352 /* Various pieces of code check for platform support by ifdef testing 353 * on "pgprot_noncached". That's broken and should be fixed, but for 354 * now... 355 */ 356 #define pgprot_noncached pgprot_noncached 357 358 #ifdef CONFIG_HUGETLB_PAGE 359 static inline pte_t pte_mkhuge(pte_t pte) 360 { 361 unsigned long mask; 362 363 __asm__ __volatile__( 364 "\n661: sethi %%uhi(%1), %0\n" 365 " sllx %0, 32, %0\n" 366 " .section .sun4v_2insn_patch, \"ax\"\n" 367 " .word 661b\n" 368 " mov %2, %0\n" 369 " nop\n" 370 " .previous\n" 371 : "=r" (mask) 372 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 373 374 return __pte(pte_val(pte) | mask); 375 } 376 #endif 377 378 static inline pte_t pte_mkdirty(pte_t pte) 379 { 380 unsigned long val = pte_val(pte), tmp; 381 382 __asm__ __volatile__( 383 "\n661: or %0, %3, %0\n" 384 " nop\n" 385 "\n662: nop\n" 386 " nop\n" 387 " .section .sun4v_2insn_patch, \"ax\"\n" 388 " .word 661b\n" 389 " sethi %%uhi(%4), %1\n" 390 " sllx %1, 32, %1\n" 391 " .word 662b\n" 392 " or %1, %%lo(%4), %1\n" 393 " or %0, %1, %0\n" 394 " .previous\n" 395 : "=r" (val), "=r" (tmp) 396 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 397 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 398 399 return __pte(val); 400 } 401 402 static inline pte_t pte_mkclean(pte_t pte) 403 { 404 unsigned long val = pte_val(pte), tmp; 405 406 __asm__ __volatile__( 407 "\n661: andn %0, %3, %0\n" 408 " nop\n" 409 "\n662: nop\n" 410 " nop\n" 411 " .section .sun4v_2insn_patch, \"ax\"\n" 412 " .word 661b\n" 413 " sethi %%uhi(%4), %1\n" 414 " sllx %1, 32, %1\n" 415 " .word 662b\n" 416 " or %1, %%lo(%4), %1\n" 417 " andn %0, %1, %0\n" 418 " .previous\n" 419 : "=r" (val), "=r" (tmp) 420 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 421 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 422 423 return __pte(val); 424 } 425 426 static inline pte_t pte_mkwrite(pte_t pte) 427 { 428 unsigned long val = pte_val(pte), mask; 429 430 __asm__ __volatile__( 431 "\n661: mov %1, %0\n" 432 " nop\n" 433 " .section .sun4v_2insn_patch, \"ax\"\n" 434 " .word 661b\n" 435 " sethi %%uhi(%2), %0\n" 436 " sllx %0, 32, %0\n" 437 " .previous\n" 438 : "=r" (mask) 439 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 440 441 return __pte(val | mask); 442 } 443 444 static inline pte_t pte_wrprotect(pte_t pte) 445 { 446 unsigned long val = pte_val(pte), tmp; 447 448 __asm__ __volatile__( 449 "\n661: andn %0, %3, %0\n" 450 " nop\n" 451 "\n662: nop\n" 452 " nop\n" 453 " .section .sun4v_2insn_patch, \"ax\"\n" 454 " .word 661b\n" 455 " sethi %%uhi(%4), %1\n" 456 " sllx %1, 32, %1\n" 457 " .word 662b\n" 458 " or %1, %%lo(%4), %1\n" 459 " andn %0, %1, %0\n" 460 " .previous\n" 461 : "=r" (val), "=r" (tmp) 462 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 463 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 464 465 return __pte(val); 466 } 467 468 static inline pte_t pte_mkold(pte_t pte) 469 { 470 unsigned long mask; 471 472 __asm__ __volatile__( 473 "\n661: mov %1, %0\n" 474 " nop\n" 475 " .section .sun4v_2insn_patch, \"ax\"\n" 476 " .word 661b\n" 477 " sethi %%uhi(%2), %0\n" 478 " sllx %0, 32, %0\n" 479 " .previous\n" 480 : "=r" (mask) 481 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 482 483 mask |= _PAGE_R; 484 485 return __pte(pte_val(pte) & ~mask); 486 } 487 488 static inline pte_t pte_mkyoung(pte_t pte) 489 { 490 unsigned long mask; 491 492 __asm__ __volatile__( 493 "\n661: mov %1, %0\n" 494 " nop\n" 495 " .section .sun4v_2insn_patch, \"ax\"\n" 496 " .word 661b\n" 497 " sethi %%uhi(%2), %0\n" 498 " sllx %0, 32, %0\n" 499 " .previous\n" 500 : "=r" (mask) 501 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 502 503 mask |= _PAGE_R; 504 505 return __pte(pte_val(pte) | mask); 506 } 507 508 static inline pte_t pte_mkspecial(pte_t pte) 509 { 510 pte_val(pte) |= _PAGE_SPECIAL; 511 return pte; 512 } 513 514 static inline unsigned long pte_young(pte_t pte) 515 { 516 unsigned long mask; 517 518 __asm__ __volatile__( 519 "\n661: mov %1, %0\n" 520 " nop\n" 521 " .section .sun4v_2insn_patch, \"ax\"\n" 522 " .word 661b\n" 523 " sethi %%uhi(%2), %0\n" 524 " sllx %0, 32, %0\n" 525 " .previous\n" 526 : "=r" (mask) 527 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 528 529 return (pte_val(pte) & mask); 530 } 531 532 static inline unsigned long pte_dirty(pte_t pte) 533 { 534 unsigned long mask; 535 536 __asm__ __volatile__( 537 "\n661: mov %1, %0\n" 538 " nop\n" 539 " .section .sun4v_2insn_patch, \"ax\"\n" 540 " .word 661b\n" 541 " sethi %%uhi(%2), %0\n" 542 " sllx %0, 32, %0\n" 543 " .previous\n" 544 : "=r" (mask) 545 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 546 547 return (pte_val(pte) & mask); 548 } 549 550 static inline unsigned long pte_write(pte_t pte) 551 { 552 unsigned long mask; 553 554 __asm__ __volatile__( 555 "\n661: mov %1, %0\n" 556 " nop\n" 557 " .section .sun4v_2insn_patch, \"ax\"\n" 558 " .word 661b\n" 559 " sethi %%uhi(%2), %0\n" 560 " sllx %0, 32, %0\n" 561 " .previous\n" 562 : "=r" (mask) 563 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 564 565 return (pte_val(pte) & mask); 566 } 567 568 static inline unsigned long pte_exec(pte_t pte) 569 { 570 unsigned long mask; 571 572 __asm__ __volatile__( 573 "\n661: sethi %%hi(%1), %0\n" 574 " .section .sun4v_1insn_patch, \"ax\"\n" 575 " .word 661b\n" 576 " mov %2, %0\n" 577 " .previous\n" 578 : "=r" (mask) 579 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 580 581 return (pte_val(pte) & mask); 582 } 583 584 static inline unsigned long pte_file(pte_t pte) 585 { 586 unsigned long val = pte_val(pte); 587 588 __asm__ __volatile__( 589 "\n661: and %0, %2, %0\n" 590 " .section .sun4v_1insn_patch, \"ax\"\n" 591 " .word 661b\n" 592 " and %0, %3, %0\n" 593 " .previous\n" 594 : "=r" (val) 595 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 596 597 return val; 598 } 599 600 static inline unsigned long pte_present(pte_t pte) 601 { 602 unsigned long val = pte_val(pte); 603 604 __asm__ __volatile__( 605 "\n661: and %0, %2, %0\n" 606 " .section .sun4v_1insn_patch, \"ax\"\n" 607 " .word 661b\n" 608 " and %0, %3, %0\n" 609 " .previous\n" 610 : "=r" (val) 611 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 612 613 return val; 614 } 615 616 static inline unsigned long pte_special(pte_t pte) 617 { 618 return pte_val(pte) & _PAGE_SPECIAL; 619 } 620 621 #define pmd_set(pmdp, ptep) \ 622 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL)) 623 #define pud_set(pudp, pmdp) \ 624 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL)) 625 #define __pmd_page(pmd) \ 626 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL))) 627 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 628 #define pud_page_vaddr(pud) \ 629 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL))) 630 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 631 #define pmd_none(pmd) (!pmd_val(pmd)) 632 #define pmd_bad(pmd) (0) 633 #define pmd_present(pmd) (pmd_val(pmd) != 0U) 634 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U) 635 #define pud_none(pud) (!pud_val(pud)) 636 #define pud_bad(pud) (0) 637 #define pud_present(pud) (pud_val(pud) != 0U) 638 #define pud_clear(pudp) (pud_val(*(pudp)) = 0U) 639 640 /* Same in both SUN4V and SUN4U. */ 641 #define pte_none(pte) (!pte_val(pte)) 642 643 /* to find an entry in a page-table-directory. */ 644 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 645 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 646 647 /* to find an entry in a kernel page-table-directory */ 648 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 649 650 /* Find an entry in the second-level page table.. */ 651 #define pmd_offset(pudp, address) \ 652 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 653 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 654 655 /* Find an entry in the third-level page table.. */ 656 #define pte_index(dir, address) \ 657 ((pte_t *) __pmd_page(*(dir)) + \ 658 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 659 #define pte_offset_kernel pte_index 660 #define pte_offset_map pte_index 661 #define pte_unmap(pte) do { } while (0) 662 663 /* Actual page table PTE updates. */ 664 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 665 pte_t *ptep, pte_t orig, int fullmm); 666 667 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 668 pte_t *ptep, pte_t pte, int fullmm) 669 { 670 pte_t orig = *ptep; 671 672 *ptep = pte; 673 674 /* It is more efficient to let flush_tlb_kernel_range() 675 * handle init_mm tlb flushes. 676 * 677 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 678 * and SUN4V pte layout, so this inline test is fine. 679 */ 680 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID)) 681 tlb_batch_add(mm, addr, ptep, orig, fullmm); 682 } 683 684 #define set_pte_at(mm,addr,ptep,pte) \ 685 __set_pte_at((mm), (addr), (ptep), (pte), 0) 686 687 #define pte_clear(mm,addr,ptep) \ 688 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 689 690 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 691 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 692 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 693 694 #ifdef DCACHE_ALIASING_POSSIBLE 695 #define __HAVE_ARCH_MOVE_PTE 696 #define move_pte(pte, prot, old_addr, new_addr) \ 697 ({ \ 698 pte_t newpte = (pte); \ 699 if (tlb_type != hypervisor && pte_present(pte)) { \ 700 unsigned long this_pfn = pte_pfn(pte); \ 701 \ 702 if (pfn_valid(this_pfn) && \ 703 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 704 flush_dcache_page_all(current->mm, \ 705 pfn_to_page(this_pfn)); \ 706 } \ 707 newpte; \ 708 }) 709 #endif 710 711 extern pgd_t swapper_pg_dir[2048]; 712 extern pmd_t swapper_low_pmd_dir[2048]; 713 714 extern void paging_init(void); 715 extern unsigned long find_ecache_flush_span(unsigned long size); 716 717 struct seq_file; 718 extern void mmu_info(struct seq_file *); 719 720 /* These do nothing with the way I have things setup. */ 721 #define mmu_lockarea(vaddr, len) (vaddr) 722 #define mmu_unlockarea(vaddr, len) do { } while(0) 723 724 struct vm_area_struct; 725 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 726 727 /* Encode and de-code a swap entry */ 728 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 729 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 730 #define __swp_entry(type, offset) \ 731 ( (swp_entry_t) \ 732 { \ 733 (((long)(type) << PAGE_SHIFT) | \ 734 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 735 } ) 736 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 737 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 738 739 /* File offset in PTE support. */ 740 extern unsigned long pte_file(pte_t); 741 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) 742 extern pte_t pgoff_to_pte(unsigned long); 743 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) 744 745 extern unsigned long sparc64_valid_addr_bitmap[]; 746 747 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 748 static inline bool kern_addr_valid(unsigned long addr) 749 { 750 unsigned long paddr = __pa(addr); 751 752 if ((paddr >> 41UL) != 0UL) 753 return false; 754 return test_bit(paddr >> 22, sparc64_valid_addr_bitmap); 755 } 756 757 extern int page_in_phys_avail(unsigned long paddr); 758 759 /* 760 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 761 * its high 4 bits. These macros/functions put it there or get it from there. 762 */ 763 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 764 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 765 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 766 767 extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 768 unsigned long, pgprot_t); 769 770 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 771 unsigned long from, unsigned long pfn, 772 unsigned long size, pgprot_t prot) 773 { 774 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 775 int space = GET_IOSPACE(pfn); 776 unsigned long phys_base; 777 778 phys_base = offset | (((unsigned long) space) << 32UL); 779 780 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 781 } 782 783 #include <asm-generic/pgtable.h> 784 785 /* We provide our own get_unmapped_area to cope with VA holes and 786 * SHM area cache aliasing for userland. 787 */ 788 #define HAVE_ARCH_UNMAPPED_AREA 789 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 790 791 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 792 * the largest alignment possible such that larget PTEs can be used. 793 */ 794 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 795 unsigned long, unsigned long, 796 unsigned long); 797 #define HAVE_ARCH_FB_UNMAPPED_AREA 798 799 extern void pgtable_cache_init(void); 800 extern void sun4v_register_fault_status(void); 801 extern void sun4v_ktsb_register(void); 802 extern void __init cheetah_ecache_flush_init(void); 803 extern void sun4v_patch_tlb_handlers(void); 804 805 extern unsigned long cmdline_memory_size; 806 807 extern asmlinkage void do_sparc64_fault(struct pt_regs *regs); 808 809 #endif /* !(__ASSEMBLY__) */ 810 811 #endif /* !(_SPARC64_PGTABLE_H) */ 812