1 /* 2 * pgtable.h: SpitFire page table operations. 3 * 4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 6 */ 7 8 #ifndef _SPARC64_PGTABLE_H 9 #define _SPARC64_PGTABLE_H 10 11 /* This file contains the functions and defines necessary to modify and use 12 * the SpitFire page tables. 13 */ 14 15 #include <linux/compiler.h> 16 #include <linux/const.h> 17 #include <asm/types.h> 18 #include <asm/spitfire.h> 19 #include <asm/asi.h> 20 #include <asm/page.h> 21 #include <asm/processor.h> 22 23 #include <asm-generic/pgtable-nopud.h> 24 25 /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). 26 * The page copy blockops can use 0x6000000 to 0x8000000. 27 * The TSB is mapped in the 0x8000000 to 0xa000000 range. 28 * The PROM resides in an area spanning 0xf0000000 to 0x100000000. 29 * The vmalloc area spans 0x100000000 to 0x200000000. 30 * Since modules need to be in the lowest 32-bits of the address space, 31 * we place them right before the OBP area from 0x10000000 to 0xf0000000. 32 * There is a single static kernel PMD which maps from 0x0 to address 33 * 0x400000000. 34 */ 35 #define TLBTEMP_BASE _AC(0x0000000006000000,UL) 36 #define TSBMAP_BASE _AC(0x0000000008000000,UL) 37 #define MODULES_VADDR _AC(0x0000000010000000,UL) 38 #define MODULES_LEN _AC(0x00000000e0000000,UL) 39 #define MODULES_END _AC(0x00000000f0000000,UL) 40 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) 41 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) 42 #define VMALLOC_START _AC(0x0000000100000000,UL) 43 #define VMALLOC_END _AC(0x0000010000000000,UL) 44 #define VMEMMAP_BASE _AC(0x0000010000000000,UL) 45 46 #define vmemmap ((struct page *)VMEMMAP_BASE) 47 48 /* PMD_SHIFT determines the size of the area a second-level page 49 * table can map 50 */ 51 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) 52 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) 53 #define PMD_MASK (~(PMD_SIZE-1)) 54 #define PMD_BITS (PAGE_SHIFT - 3) 55 56 /* PGDIR_SHIFT determines what a third-level page table entry can map */ 57 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS) 58 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) 59 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 60 #define PGDIR_BITS (PAGE_SHIFT - 3) 61 62 #if (PGDIR_SHIFT + PGDIR_BITS) != 43 63 #error Page table parameters do not cover virtual address space properly. 64 #endif 65 66 #if (PMD_SHIFT != HPAGE_SHIFT) 67 #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. 68 #endif 69 70 #ifndef __ASSEMBLY__ 71 72 #include <linux/sched.h> 73 74 /* Entries per page directory level. */ 75 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) 76 #define PTRS_PER_PMD (1UL << PMD_BITS) 77 #define PTRS_PER_PGD (1UL << PGDIR_BITS) 78 79 /* Kernel has a separate 44bit address space. */ 80 #define FIRST_USER_ADDRESS 0 81 82 #define pte_ERROR(e) __builtin_trap() 83 #define pmd_ERROR(e) __builtin_trap() 84 #define pgd_ERROR(e) __builtin_trap() 85 86 #endif /* !(__ASSEMBLY__) */ 87 88 /* PTE bits which are the same in SUN4U and SUN4V format. */ 89 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ 90 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ 91 #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ 92 #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ 93 94 /* Advertise support for _PAGE_SPECIAL */ 95 #define __HAVE_ARCH_PTE_SPECIAL 96 97 /* SUN4U pte bits... */ 98 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ 99 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ 100 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ 101 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ 102 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ 103 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ 104 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ 105 #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ 106 #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ 107 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ 108 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ 109 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ 110 #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ 111 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ 112 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ 113 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ 114 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ 115 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ 116 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ 117 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */ 118 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ 119 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ 120 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ 121 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ 122 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ 123 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ 124 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ 125 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ 126 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ 127 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ 128 129 /* SUN4V pte bits... */ 130 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ 131 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ 132 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ 133 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ 134 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ 135 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ 136 #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ 137 #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ 138 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ 139 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ 140 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ 141 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ 142 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ 143 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ 144 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ 145 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ 146 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ 147 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */ 148 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ 149 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ 150 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ 151 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ 152 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ 153 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ 154 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ 155 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ 156 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ 157 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ 158 #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ 159 160 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U 161 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V 162 163 #if REAL_HPAGE_SHIFT != 22 164 #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up 165 #endif 166 167 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U 168 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V 169 170 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ 171 #define __P000 __pgprot(0) 172 #define __P001 __pgprot(0) 173 #define __P010 __pgprot(0) 174 #define __P011 __pgprot(0) 175 #define __P100 __pgprot(0) 176 #define __P101 __pgprot(0) 177 #define __P110 __pgprot(0) 178 #define __P111 __pgprot(0) 179 180 #define __S000 __pgprot(0) 181 #define __S001 __pgprot(0) 182 #define __S010 __pgprot(0) 183 #define __S011 __pgprot(0) 184 #define __S100 __pgprot(0) 185 #define __S101 __pgprot(0) 186 #define __S110 __pgprot(0) 187 #define __S111 __pgprot(0) 188 189 #ifndef __ASSEMBLY__ 190 191 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); 192 193 extern unsigned long pte_sz_bits(unsigned long size); 194 195 extern pgprot_t PAGE_KERNEL; 196 extern pgprot_t PAGE_KERNEL_LOCKED; 197 extern pgprot_t PAGE_COPY; 198 extern pgprot_t PAGE_SHARED; 199 200 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */ 201 extern unsigned long _PAGE_IE; 202 extern unsigned long _PAGE_E; 203 extern unsigned long _PAGE_CACHE; 204 205 extern unsigned long pg_iobits; 206 extern unsigned long _PAGE_ALL_SZ_BITS; 207 208 extern struct page *mem_map_zero; 209 #define ZERO_PAGE(vaddr) (mem_map_zero) 210 211 /* PFNs are real physical page numbers. However, mem_map only begins to record 212 * per-page information starting at pfn_base. This is to handle systems where 213 * the first physical page in the machine is at some huge physical address, 214 * such as 4GB. This is common on a partitioned E10000, for example. 215 */ 216 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 217 { 218 unsigned long paddr = pfn << PAGE_SHIFT; 219 220 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 221 return __pte(paddr | pgprot_val(prot)); 222 } 223 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 224 225 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 226 static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 227 { 228 pte_t pte = pfn_pte(page_nr, pgprot); 229 230 return __pmd(pte_val(pte)); 231 } 232 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 233 #endif 234 235 /* This one can be done with two shifts. */ 236 static inline unsigned long pte_pfn(pte_t pte) 237 { 238 unsigned long ret; 239 240 __asm__ __volatile__( 241 "\n661: sllx %1, %2, %0\n" 242 " srlx %0, %3, %0\n" 243 " .section .sun4v_2insn_patch, \"ax\"\n" 244 " .word 661b\n" 245 " sllx %1, %4, %0\n" 246 " srlx %0, %5, %0\n" 247 " .previous\n" 248 : "=r" (ret) 249 : "r" (pte_val(pte)), 250 "i" (21), "i" (21 + PAGE_SHIFT), 251 "i" (8), "i" (8 + PAGE_SHIFT)); 252 253 return ret; 254 } 255 #define pte_page(x) pfn_to_page(pte_pfn(x)) 256 257 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 258 { 259 unsigned long mask, tmp; 260 261 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347) 262 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8) 263 * 264 * Even if we use negation tricks the result is still a 6 265 * instruction sequence, so don't try to play fancy and just 266 * do the most straightforward implementation. 267 * 268 * Note: We encode this into 3 sun4v 2-insn patch sequences. 269 */ 270 271 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); 272 __asm__ __volatile__( 273 "\n661: sethi %%uhi(%2), %1\n" 274 " sethi %%hi(%2), %0\n" 275 "\n662: or %1, %%ulo(%2), %1\n" 276 " or %0, %%lo(%2), %0\n" 277 "\n663: sllx %1, 32, %1\n" 278 " or %0, %1, %0\n" 279 " .section .sun4v_2insn_patch, \"ax\"\n" 280 " .word 661b\n" 281 " sethi %%uhi(%3), %1\n" 282 " sethi %%hi(%3), %0\n" 283 " .word 662b\n" 284 " or %1, %%ulo(%3), %1\n" 285 " or %0, %%lo(%3), %0\n" 286 " .word 663b\n" 287 " sllx %1, 32, %1\n" 288 " or %0, %1, %0\n" 289 " .previous\n" 290 : "=r" (mask), "=r" (tmp) 291 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | 292 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | _PAGE_PRESENT_4U | 293 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), 294 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | 295 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | _PAGE_PRESENT_4V | 296 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); 297 298 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); 299 } 300 301 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 302 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 303 { 304 pte_t pte = __pte(pmd_val(pmd)); 305 306 pte = pte_modify(pte, newprot); 307 308 return __pmd(pte_val(pte)); 309 } 310 #endif 311 312 static inline pte_t pgoff_to_pte(unsigned long off) 313 { 314 off <<= PAGE_SHIFT; 315 316 __asm__ __volatile__( 317 "\n661: or %0, %2, %0\n" 318 " .section .sun4v_1insn_patch, \"ax\"\n" 319 " .word 661b\n" 320 " or %0, %3, %0\n" 321 " .previous\n" 322 : "=r" (off) 323 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 324 325 return __pte(off); 326 } 327 328 static inline pgprot_t pgprot_noncached(pgprot_t prot) 329 { 330 unsigned long val = pgprot_val(prot); 331 332 __asm__ __volatile__( 333 "\n661: andn %0, %2, %0\n" 334 " or %0, %3, %0\n" 335 " .section .sun4v_2insn_patch, \"ax\"\n" 336 " .word 661b\n" 337 " andn %0, %4, %0\n" 338 " or %0, %5, %0\n" 339 " .previous\n" 340 : "=r" (val) 341 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), 342 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V)); 343 344 return __pgprot(val); 345 } 346 /* Various pieces of code check for platform support by ifdef testing 347 * on "pgprot_noncached". That's broken and should be fixed, but for 348 * now... 349 */ 350 #define pgprot_noncached pgprot_noncached 351 352 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) 353 static inline pte_t pte_mkhuge(pte_t pte) 354 { 355 unsigned long mask; 356 357 __asm__ __volatile__( 358 "\n661: sethi %%uhi(%1), %0\n" 359 " sllx %0, 32, %0\n" 360 " .section .sun4v_2insn_patch, \"ax\"\n" 361 " .word 661b\n" 362 " mov %2, %0\n" 363 " nop\n" 364 " .previous\n" 365 : "=r" (mask) 366 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); 367 368 return __pte(pte_val(pte) | mask); 369 } 370 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 371 static inline pmd_t pmd_mkhuge(pmd_t pmd) 372 { 373 pte_t pte = __pte(pmd_val(pmd)); 374 375 pte = pte_mkhuge(pte); 376 pte_val(pte) |= _PAGE_PMD_HUGE; 377 378 return __pmd(pte_val(pte)); 379 } 380 #endif 381 #endif 382 383 static inline pte_t pte_mkdirty(pte_t pte) 384 { 385 unsigned long val = pte_val(pte), tmp; 386 387 __asm__ __volatile__( 388 "\n661: or %0, %3, %0\n" 389 " nop\n" 390 "\n662: nop\n" 391 " nop\n" 392 " .section .sun4v_2insn_patch, \"ax\"\n" 393 " .word 661b\n" 394 " sethi %%uhi(%4), %1\n" 395 " sllx %1, 32, %1\n" 396 " .word 662b\n" 397 " or %1, %%lo(%4), %1\n" 398 " or %0, %1, %0\n" 399 " .previous\n" 400 : "=r" (val), "=r" (tmp) 401 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 402 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 403 404 return __pte(val); 405 } 406 407 static inline pte_t pte_mkclean(pte_t pte) 408 { 409 unsigned long val = pte_val(pte), tmp; 410 411 __asm__ __volatile__( 412 "\n661: andn %0, %3, %0\n" 413 " nop\n" 414 "\n662: nop\n" 415 " nop\n" 416 " .section .sun4v_2insn_patch, \"ax\"\n" 417 " .word 661b\n" 418 " sethi %%uhi(%4), %1\n" 419 " sllx %1, 32, %1\n" 420 " .word 662b\n" 421 " or %1, %%lo(%4), %1\n" 422 " andn %0, %1, %0\n" 423 " .previous\n" 424 : "=r" (val), "=r" (tmp) 425 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), 426 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); 427 428 return __pte(val); 429 } 430 431 static inline pte_t pte_mkwrite(pte_t pte) 432 { 433 unsigned long val = pte_val(pte), mask; 434 435 __asm__ __volatile__( 436 "\n661: mov %1, %0\n" 437 " nop\n" 438 " .section .sun4v_2insn_patch, \"ax\"\n" 439 " .word 661b\n" 440 " sethi %%uhi(%2), %0\n" 441 " sllx %0, 32, %0\n" 442 " .previous\n" 443 : "=r" (mask) 444 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 445 446 return __pte(val | mask); 447 } 448 449 static inline pte_t pte_wrprotect(pte_t pte) 450 { 451 unsigned long val = pte_val(pte), tmp; 452 453 __asm__ __volatile__( 454 "\n661: andn %0, %3, %0\n" 455 " nop\n" 456 "\n662: nop\n" 457 " nop\n" 458 " .section .sun4v_2insn_patch, \"ax\"\n" 459 " .word 661b\n" 460 " sethi %%uhi(%4), %1\n" 461 " sllx %1, 32, %1\n" 462 " .word 662b\n" 463 " or %1, %%lo(%4), %1\n" 464 " andn %0, %1, %0\n" 465 " .previous\n" 466 : "=r" (val), "=r" (tmp) 467 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), 468 "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); 469 470 return __pte(val); 471 } 472 473 static inline pte_t pte_mkold(pte_t pte) 474 { 475 unsigned long mask; 476 477 __asm__ __volatile__( 478 "\n661: mov %1, %0\n" 479 " nop\n" 480 " .section .sun4v_2insn_patch, \"ax\"\n" 481 " .word 661b\n" 482 " sethi %%uhi(%2), %0\n" 483 " sllx %0, 32, %0\n" 484 " .previous\n" 485 : "=r" (mask) 486 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 487 488 mask |= _PAGE_R; 489 490 return __pte(pte_val(pte) & ~mask); 491 } 492 493 static inline pte_t pte_mkyoung(pte_t pte) 494 { 495 unsigned long mask; 496 497 __asm__ __volatile__( 498 "\n661: mov %1, %0\n" 499 " nop\n" 500 " .section .sun4v_2insn_patch, \"ax\"\n" 501 " .word 661b\n" 502 " sethi %%uhi(%2), %0\n" 503 " sllx %0, 32, %0\n" 504 " .previous\n" 505 : "=r" (mask) 506 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 507 508 mask |= _PAGE_R; 509 510 return __pte(pte_val(pte) | mask); 511 } 512 513 static inline pte_t pte_mkspecial(pte_t pte) 514 { 515 pte_val(pte) |= _PAGE_SPECIAL; 516 return pte; 517 } 518 519 static inline unsigned long pte_young(pte_t pte) 520 { 521 unsigned long mask; 522 523 __asm__ __volatile__( 524 "\n661: mov %1, %0\n" 525 " nop\n" 526 " .section .sun4v_2insn_patch, \"ax\"\n" 527 " .word 661b\n" 528 " sethi %%uhi(%2), %0\n" 529 " sllx %0, 32, %0\n" 530 " .previous\n" 531 : "=r" (mask) 532 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); 533 534 return (pte_val(pte) & mask); 535 } 536 537 static inline unsigned long pte_dirty(pte_t pte) 538 { 539 unsigned long mask; 540 541 __asm__ __volatile__( 542 "\n661: mov %1, %0\n" 543 " nop\n" 544 " .section .sun4v_2insn_patch, \"ax\"\n" 545 " .word 661b\n" 546 " sethi %%uhi(%2), %0\n" 547 " sllx %0, 32, %0\n" 548 " .previous\n" 549 : "=r" (mask) 550 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); 551 552 return (pte_val(pte) & mask); 553 } 554 555 static inline unsigned long pte_write(pte_t pte) 556 { 557 unsigned long mask; 558 559 __asm__ __volatile__( 560 "\n661: mov %1, %0\n" 561 " nop\n" 562 " .section .sun4v_2insn_patch, \"ax\"\n" 563 " .word 661b\n" 564 " sethi %%uhi(%2), %0\n" 565 " sllx %0, 32, %0\n" 566 " .previous\n" 567 : "=r" (mask) 568 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); 569 570 return (pte_val(pte) & mask); 571 } 572 573 static inline unsigned long pte_exec(pte_t pte) 574 { 575 unsigned long mask; 576 577 __asm__ __volatile__( 578 "\n661: sethi %%hi(%1), %0\n" 579 " .section .sun4v_1insn_patch, \"ax\"\n" 580 " .word 661b\n" 581 " mov %2, %0\n" 582 " .previous\n" 583 : "=r" (mask) 584 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); 585 586 return (pte_val(pte) & mask); 587 } 588 589 static inline unsigned long pte_file(pte_t pte) 590 { 591 unsigned long val = pte_val(pte); 592 593 __asm__ __volatile__( 594 "\n661: and %0, %2, %0\n" 595 " .section .sun4v_1insn_patch, \"ax\"\n" 596 " .word 661b\n" 597 " and %0, %3, %0\n" 598 " .previous\n" 599 : "=r" (val) 600 : "0" (val), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V)); 601 602 return val; 603 } 604 605 static inline unsigned long pte_present(pte_t pte) 606 { 607 unsigned long val = pte_val(pte); 608 609 __asm__ __volatile__( 610 "\n661: and %0, %2, %0\n" 611 " .section .sun4v_1insn_patch, \"ax\"\n" 612 " .word 661b\n" 613 " and %0, %3, %0\n" 614 " .previous\n" 615 : "=r" (val) 616 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); 617 618 return val; 619 } 620 621 #define pte_accessible pte_accessible 622 static inline unsigned long pte_accessible(pte_t a) 623 { 624 return pte_val(a) & _PAGE_VALID; 625 } 626 627 static inline unsigned long pte_special(pte_t pte) 628 { 629 return pte_val(pte) & _PAGE_SPECIAL; 630 } 631 632 static inline unsigned long pmd_large(pmd_t pmd) 633 { 634 pte_t pte = __pte(pmd_val(pmd)); 635 636 return (pte_val(pte) & _PAGE_PMD_HUGE) && pte_present(pte); 637 } 638 639 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 640 static inline unsigned long pmd_young(pmd_t pmd) 641 { 642 pte_t pte = __pte(pmd_val(pmd)); 643 644 return pte_young(pte); 645 } 646 647 static inline unsigned long pmd_write(pmd_t pmd) 648 { 649 pte_t pte = __pte(pmd_val(pmd)); 650 651 return pte_write(pte); 652 } 653 654 static inline unsigned long pmd_pfn(pmd_t pmd) 655 { 656 pte_t pte = __pte(pmd_val(pmd)); 657 658 return pte_pfn(pte); 659 } 660 661 static inline unsigned long pmd_trans_huge(pmd_t pmd) 662 { 663 pte_t pte = __pte(pmd_val(pmd)); 664 665 return pte_val(pte) & _PAGE_PMD_HUGE; 666 } 667 668 static inline unsigned long pmd_trans_splitting(pmd_t pmd) 669 { 670 pte_t pte = __pte(pmd_val(pmd)); 671 672 return pmd_trans_huge(pmd) && pte_special(pte); 673 } 674 675 #define has_transparent_hugepage() 1 676 677 static inline pmd_t pmd_mkold(pmd_t pmd) 678 { 679 pte_t pte = __pte(pmd_val(pmd)); 680 681 pte = pte_mkold(pte); 682 683 return __pmd(pte_val(pte)); 684 } 685 686 static inline pmd_t pmd_wrprotect(pmd_t pmd) 687 { 688 pte_t pte = __pte(pmd_val(pmd)); 689 690 pte = pte_wrprotect(pte); 691 692 return __pmd(pte_val(pte)); 693 } 694 695 static inline pmd_t pmd_mkdirty(pmd_t pmd) 696 { 697 pte_t pte = __pte(pmd_val(pmd)); 698 699 pte = pte_mkdirty(pte); 700 701 return __pmd(pte_val(pte)); 702 } 703 704 static inline pmd_t pmd_mkyoung(pmd_t pmd) 705 { 706 pte_t pte = __pte(pmd_val(pmd)); 707 708 pte = pte_mkyoung(pte); 709 710 return __pmd(pte_val(pte)); 711 } 712 713 static inline pmd_t pmd_mkwrite(pmd_t pmd) 714 { 715 pte_t pte = __pte(pmd_val(pmd)); 716 717 pte = pte_mkwrite(pte); 718 719 return __pmd(pte_val(pte)); 720 } 721 722 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 723 { 724 unsigned long mask; 725 726 if (tlb_type == hypervisor) 727 mask = _PAGE_PRESENT_4V; 728 else 729 mask = _PAGE_PRESENT_4U; 730 731 pmd_val(pmd) &= ~mask; 732 733 return pmd; 734 } 735 736 static inline pmd_t pmd_mksplitting(pmd_t pmd) 737 { 738 pte_t pte = __pte(pmd_val(pmd)); 739 740 pte = pte_mkspecial(pte); 741 742 return __pmd(pte_val(pte)); 743 } 744 745 static inline pgprot_t pmd_pgprot(pmd_t entry) 746 { 747 unsigned long val = pmd_val(entry); 748 749 return __pgprot(val); 750 } 751 #endif 752 753 static inline int pmd_present(pmd_t pmd) 754 { 755 return pmd_val(pmd) != 0UL; 756 } 757 758 #define pmd_none(pmd) (!pmd_val(pmd)) 759 760 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 761 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 762 pmd_t *pmdp, pmd_t pmd); 763 #else 764 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 765 pmd_t *pmdp, pmd_t pmd) 766 { 767 *pmdp = pmd; 768 } 769 #endif 770 771 static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 772 { 773 unsigned long val = __pa((unsigned long) (ptep)); 774 775 pmd_val(*pmdp) = val; 776 } 777 778 #define pud_set(pudp, pmdp) \ 779 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) 780 static inline unsigned long __pmd_page(pmd_t pmd) 781 { 782 pte_t pte = __pte(pmd_val(pmd)); 783 unsigned long pfn; 784 785 pfn = pte_pfn(pte); 786 787 return ((unsigned long) __va(pfn << PAGE_SHIFT)); 788 } 789 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 790 #define pud_page_vaddr(pud) \ 791 ((unsigned long) __va(pud_val(pud))) 792 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 793 #define pmd_bad(pmd) (0) 794 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) 795 #define pud_none(pud) (!pud_val(pud)) 796 #define pud_bad(pud) (0) 797 #define pud_present(pud) (pud_val(pud) != 0U) 798 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) 799 800 /* Same in both SUN4V and SUN4U. */ 801 #define pte_none(pte) (!pte_val(pte)) 802 803 /* to find an entry in a page-table-directory. */ 804 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 805 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 806 807 /* to find an entry in a kernel page-table-directory */ 808 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 809 810 /* Find an entry in the second-level page table.. */ 811 #define pmd_offset(pudp, address) \ 812 ((pmd_t *) pud_page_vaddr(*(pudp)) + \ 813 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) 814 815 /* Find an entry in the third-level page table.. */ 816 #define pte_index(dir, address) \ 817 ((pte_t *) __pmd_page(*(dir)) + \ 818 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 819 #define pte_offset_kernel pte_index 820 #define pte_offset_map pte_index 821 #define pte_unmap(pte) do { } while (0) 822 823 /* Actual page table PTE updates. */ 824 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, 825 pte_t *ptep, pte_t orig, int fullmm); 826 827 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 828 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 829 unsigned long addr, 830 pmd_t *pmdp) 831 { 832 pmd_t pmd = *pmdp; 833 set_pmd_at(mm, addr, pmdp, __pmd(0UL)); 834 return pmd; 835 } 836 837 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 838 pte_t *ptep, pte_t pte, int fullmm) 839 { 840 pte_t orig = *ptep; 841 842 *ptep = pte; 843 844 /* It is more efficient to let flush_tlb_kernel_range() 845 * handle init_mm tlb flushes. 846 * 847 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U 848 * and SUN4V pte layout, so this inline test is fine. 849 */ 850 if (likely(mm != &init_mm) && pte_accessible(orig)) 851 tlb_batch_add(mm, addr, ptep, orig, fullmm); 852 } 853 854 #define set_pte_at(mm,addr,ptep,pte) \ 855 __set_pte_at((mm), (addr), (ptep), (pte), 0) 856 857 #define pte_clear(mm,addr,ptep) \ 858 set_pte_at((mm), (addr), (ptep), __pte(0UL)) 859 860 #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 861 #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ 862 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) 863 864 #ifdef DCACHE_ALIASING_POSSIBLE 865 #define __HAVE_ARCH_MOVE_PTE 866 #define move_pte(pte, prot, old_addr, new_addr) \ 867 ({ \ 868 pte_t newpte = (pte); \ 869 if (tlb_type != hypervisor && pte_present(pte)) { \ 870 unsigned long this_pfn = pte_pfn(pte); \ 871 \ 872 if (pfn_valid(this_pfn) && \ 873 (((old_addr) ^ (new_addr)) & (1 << 13))) \ 874 flush_dcache_page_all(current->mm, \ 875 pfn_to_page(this_pfn)); \ 876 } \ 877 newpte; \ 878 }) 879 #endif 880 881 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 882 extern pmd_t swapper_low_pmd_dir[PTRS_PER_PMD]; 883 884 extern void paging_init(void); 885 extern unsigned long find_ecache_flush_span(unsigned long size); 886 887 struct seq_file; 888 extern void mmu_info(struct seq_file *); 889 890 struct vm_area_struct; 891 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 892 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 893 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 894 pmd_t *pmd); 895 896 #define __HAVE_ARCH_PGTABLE_DEPOSIT 897 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 898 pgtable_t pgtable); 899 900 #define __HAVE_ARCH_PGTABLE_WITHDRAW 901 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 902 #endif 903 904 /* Encode and de-code a swap entry */ 905 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) 906 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) 907 #define __swp_entry(type, offset) \ 908 ( (swp_entry_t) \ 909 { \ 910 (((long)(type) << PAGE_SHIFT) | \ 911 ((long)(offset) << (PAGE_SHIFT + 8UL))) \ 912 } ) 913 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 914 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 915 916 /* File offset in PTE support. */ 917 extern unsigned long pte_file(pte_t); 918 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT) 919 extern pte_t pgoff_to_pte(unsigned long); 920 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL) 921 922 extern unsigned long sparc64_valid_addr_bitmap[]; 923 924 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 925 static inline bool kern_addr_valid(unsigned long addr) 926 { 927 unsigned long paddr = __pa(addr); 928 929 if ((paddr >> 41UL) != 0UL) 930 return false; 931 return test_bit(paddr >> 22, sparc64_valid_addr_bitmap); 932 } 933 934 extern int page_in_phys_avail(unsigned long paddr); 935 936 /* 937 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in 938 * its high 4 bits. These macros/functions put it there or get it from there. 939 */ 940 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) 941 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) 942 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) 943 944 extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, 945 unsigned long, pgprot_t); 946 947 static inline int io_remap_pfn_range(struct vm_area_struct *vma, 948 unsigned long from, unsigned long pfn, 949 unsigned long size, pgprot_t prot) 950 { 951 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; 952 int space = GET_IOSPACE(pfn); 953 unsigned long phys_base; 954 955 phys_base = offset | (((unsigned long) space) << 32UL); 956 957 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); 958 } 959 #define io_remap_pfn_range io_remap_pfn_range 960 961 #include <asm/tlbflush.h> 962 #include <asm-generic/pgtable.h> 963 964 /* We provide our own get_unmapped_area to cope with VA holes and 965 * SHM area cache aliasing for userland. 966 */ 967 #define HAVE_ARCH_UNMAPPED_AREA 968 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 969 970 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use 971 * the largest alignment possible such that larget PTEs can be used. 972 */ 973 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, 974 unsigned long, unsigned long, 975 unsigned long); 976 #define HAVE_ARCH_FB_UNMAPPED_AREA 977 978 extern void pgtable_cache_init(void); 979 extern void sun4v_register_fault_status(void); 980 extern void sun4v_ktsb_register(void); 981 extern void __init cheetah_ecache_flush_init(void); 982 extern void sun4v_patch_tlb_handlers(void); 983 984 extern unsigned long cmdline_memory_size; 985 986 extern asmlinkage void do_sparc64_fault(struct pt_regs *regs); 987 988 #endif /* !(__ASSEMBLY__) */ 989 990 #endif /* !(_SPARC64_PGTABLE_H) */ 991