xref: /openbmc/linux/arch/sparc/include/asm/ns87303.h (revision b2441318)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /* ns87303.h: Configuration Register Description for the
3a439fe51SSam Ravnborg  *            National Semiconductor PC87303 (SuperIO).
4a439fe51SSam Ravnborg  *
5a439fe51SSam Ravnborg  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
6a439fe51SSam Ravnborg  */
7a439fe51SSam Ravnborg 
8a439fe51SSam Ravnborg #ifndef _SPARC_NS87303_H
9a439fe51SSam Ravnborg #define _SPARC_NS87303_H 1
10a439fe51SSam Ravnborg 
11a439fe51SSam Ravnborg /*
12a439fe51SSam Ravnborg  * Control Register Index Values
13a439fe51SSam Ravnborg  */
14a439fe51SSam Ravnborg #define FER	0x00
15a439fe51SSam Ravnborg #define FAR	0x01
16a439fe51SSam Ravnborg #define PTR	0x02
17a439fe51SSam Ravnborg #define FCR	0x03
18a439fe51SSam Ravnborg #define PCR	0x04
19a439fe51SSam Ravnborg #define KRR	0x05
20a439fe51SSam Ravnborg #define PMC	0x06
21a439fe51SSam Ravnborg #define TUP	0x07
22a439fe51SSam Ravnborg #define SID	0x08
23a439fe51SSam Ravnborg #define ASC	0x09
24a439fe51SSam Ravnborg #define CS0CF0	0x0a
25a439fe51SSam Ravnborg #define CS0CF1	0x0b
26a439fe51SSam Ravnborg #define CS1CF0	0x0c
27a439fe51SSam Ravnborg #define CS1CF1	0x0d
28a439fe51SSam Ravnborg 
29a439fe51SSam Ravnborg /* Function Enable Register (FER) bits */
30a439fe51SSam Ravnborg #define FER_EDM		0x10	/* Encoded Drive and Motor pin information   */
31a439fe51SSam Ravnborg 
32a439fe51SSam Ravnborg /* Function Address Register (FAR) bits */
33a439fe51SSam Ravnborg #define FAR_LPT_MASK	0x03
34a439fe51SSam Ravnborg #define FAR_LPTB	0x00
35a439fe51SSam Ravnborg #define FAR_LPTA	0x01
36a439fe51SSam Ravnborg #define FAR_LPTC	0x02
37a439fe51SSam Ravnborg 
38a439fe51SSam Ravnborg /* Power and Test Register (PTR) bits */
39a439fe51SSam Ravnborg #define PTR_LPTB_IRQ7	0x08
40a439fe51SSam Ravnborg #define PTR_LEVEL_IRQ	0x80	/* When not ECP/EPP: Use level IRQ           */
4125985edcSLucas De Marchi #define PTR_LPT_REG_DIR	0x80	/* When ECP/EPP: LPT CTR controls direction */
42a439fe51SSam Ravnborg 				/*               of the parallel port	     */
43a439fe51SSam Ravnborg 
44a439fe51SSam Ravnborg /* Function Control Register (FCR) bits */
45a439fe51SSam Ravnborg #define FCR_LDE		0x10	/* Logical Drive Exchange                    */
46a439fe51SSam Ravnborg #define FCR_ZWS_ENA	0x20	/* Enable short host read/write in ECP/EPP   */
47a439fe51SSam Ravnborg 
48a439fe51SSam Ravnborg /* Printer Control Register (PCR) bits */
49a439fe51SSam Ravnborg #define PCR_EPP_ENABLE	0x01
50a439fe51SSam Ravnborg #define PCR_EPP_IEEE	0x02	/* Enable EPP Version 1.9 (IEEE 1284)        */
51a439fe51SSam Ravnborg #define PCR_ECP_ENABLE	0x04
52a439fe51SSam Ravnborg #define PCR_ECP_CLK_ENA	0x08	/* If 0 ECP Clock is stopped on Power down   */
53a439fe51SSam Ravnborg #define PCR_IRQ_POLAR	0x20	/* If 0 IRQ is level high or negative pulse, */
54a439fe51SSam Ravnborg 				/* if 1 polarity is inverted                 */
55a439fe51SSam Ravnborg #define PCR_IRQ_ODRAIN	0x40	/* If 1, IRQ is open drain                   */
56a439fe51SSam Ravnborg 
57a439fe51SSam Ravnborg /* Tape UARTs and Parallel Port Config Register (TUP) bits */
58a439fe51SSam Ravnborg #define TUP_EPP_TIMO	0x02	/* Enable EPP timeout IRQ                    */
59a439fe51SSam Ravnborg 
60a439fe51SSam Ravnborg /* Advanced SuperIO Config Register (ASC) bits */
61a439fe51SSam Ravnborg #define ASC_LPT_IRQ7	0x01	/* Always use IRQ7 for LPT                  */
62a439fe51SSam Ravnborg #define ASC_DRV2_SEL	0x02	/* Logical Drive Exchange controlled by TDR  */
63a439fe51SSam Ravnborg 
64a439fe51SSam Ravnborg #define FER_RESERVED	0x00
65a439fe51SSam Ravnborg #define FAR_RESERVED	0x00
66a439fe51SSam Ravnborg #define PTR_RESERVED	0x73
67a439fe51SSam Ravnborg #define FCR_RESERVED	0xc4
68a439fe51SSam Ravnborg #define PCR_RESERVED	0x10
69a439fe51SSam Ravnborg #define KRR_RESERVED	0x00
70a439fe51SSam Ravnborg #define PMC_RESERVED	0x98
71a439fe51SSam Ravnborg #define TUP_RESERVED	0xfb
72a439fe51SSam Ravnborg #define SIP_RESERVED	0x00
73a439fe51SSam Ravnborg #define ASC_RESERVED	0x18
74a439fe51SSam Ravnborg #define CS0CF0_RESERVED	0x00
75a439fe51SSam Ravnborg #define CS0CF1_RESERVED	0x08
76a439fe51SSam Ravnborg #define CS1CF0_RESERVED	0x00
77a439fe51SSam Ravnborg #define CS1CF1_RESERVED	0x08
78a439fe51SSam Ravnborg 
79a439fe51SSam Ravnborg #ifdef __KERNEL__
80a439fe51SSam Ravnborg 
81a439fe51SSam Ravnborg #include <linux/spinlock.h>
82a439fe51SSam Ravnborg 
83a439fe51SSam Ravnborg #include <asm/io.h>
84a439fe51SSam Ravnborg 
85a439fe51SSam Ravnborg extern spinlock_t ns87303_lock;
86a439fe51SSam Ravnborg 
ns87303_modify(unsigned long port,unsigned int index,unsigned char clr,unsigned char set)87a439fe51SSam Ravnborg static inline int ns87303_modify(unsigned long port, unsigned int index,
88a439fe51SSam Ravnborg 				     unsigned char clr, unsigned char set)
89a439fe51SSam Ravnborg {
90a439fe51SSam Ravnborg 	static unsigned char reserved[] = {
91a439fe51SSam Ravnborg 		FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
92a439fe51SSam Ravnborg 		PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
93a439fe51SSam Ravnborg 		SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
94a439fe51SSam Ravnborg 		CS1CF0_RESERVED, CS1CF1_RESERVED
95a439fe51SSam Ravnborg 	};
96a439fe51SSam Ravnborg 	unsigned long flags;
97a439fe51SSam Ravnborg 	unsigned char value;
98a439fe51SSam Ravnborg 
99a439fe51SSam Ravnborg 	if (index > 0x0d)
100a439fe51SSam Ravnborg 		return -EINVAL;
101a439fe51SSam Ravnborg 
102a439fe51SSam Ravnborg 	spin_lock_irqsave(&ns87303_lock, flags);
103a439fe51SSam Ravnborg 
104a439fe51SSam Ravnborg 	outb(index, port);
105a439fe51SSam Ravnborg 	value = inb(port + 1);
106a439fe51SSam Ravnborg 	value &= ~(reserved[index] | clr);
107a439fe51SSam Ravnborg 	value |= set;
108a439fe51SSam Ravnborg 	outb(value, port + 1);
109a439fe51SSam Ravnborg 	outb(value, port + 1);
110a439fe51SSam Ravnborg 
111a439fe51SSam Ravnborg 	spin_unlock_irqrestore(&ns87303_lock, flags);
112a439fe51SSam Ravnborg 
113a439fe51SSam Ravnborg 	return 0;
114a439fe51SSam Ravnborg }
115a439fe51SSam Ravnborg 
116a439fe51SSam Ravnborg #endif /* __KERNEL__ */
117a439fe51SSam Ravnborg 
118a439fe51SSam Ravnborg #endif /* !(_SPARC_NS87303_H) */
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