1 /* io-unit.h: Definitions for the sun4d IO-UNIT. 2 * 3 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 4 */ 5 #ifndef _SPARC_IO_UNIT_H 6 #define _SPARC_IO_UNIT_H 7 8 #include <linux/spinlock.h> 9 #include <asm/page.h> 10 #include <asm/pgtable.h> 11 12 /* The io-unit handles all virtual to physical address translations 13 * that occur between the SBUS and physical memory. Access by 14 * the cpu to IO registers and similar go over the xdbus so are 15 * translated by the on chip SRMMU. The io-unit and the srmmu do 16 * not need to have the same translations at all, in fact most 17 * of the time the translations they handle are a disjunct set. 18 * Basically the io-unit handles all dvma sbus activity. 19 */ 20 21 /* AIEEE, unlike the nice sun4m, these monsters have 22 fixed DMA range 64M */ 23 24 #define IOUNIT_DMA_BASE 0xfc000000 /* TOP - 64M */ 25 #define IOUNIT_DMA_SIZE 0x04000000 /* 64M */ 26 /* We use last 1M for sparc_dvma_malloc */ 27 #define IOUNIT_DVMA_SIZE 0x00100000 /* 1M */ 28 29 /* The format of an iopte in the external page tables */ 30 #define IOUPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ 31 #define IOUPTE_CACHE 0x00000080 /* Cached (in Viking/MXCC) */ 32 /* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d. 33 * XXX Actually, all you should need to do is find out where the registers 34 * XXX are and copy over the sparc64 implementation I wrote. There may be 35 * XXX some horrible hwbugs though, so be careful. -DaveM 36 */ 37 #define IOUPTE_STREAM 0x00000040 /* Translation can use streaming cache */ 38 #define IOUPTE_INTRA 0x00000008 /* SBUS direct slot->slot transfer */ 39 #define IOUPTE_WRITE 0x00000004 /* Writeable */ 40 #define IOUPTE_VALID 0x00000002 /* IOPTE is valid */ 41 #define IOUPTE_PARITY 0x00000001 /* Parity is checked during DVMA */ 42 43 struct iounit_struct { 44 unsigned long bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)]; 45 spinlock_t lock; 46 iopte_t *page_table; 47 unsigned long rotor[3]; 48 unsigned long limit[4]; 49 }; 50 51 #define IOUNIT_BMAP1_START 0x00000000 52 #define IOUNIT_BMAP1_END (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1)) 53 #define IOUNIT_BMAP2_START IOUNIT_BMAP1_END 54 #define IOUNIT_BMAP2_END IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2)) 55 #define IOUNIT_BMAPM_START IOUNIT_BMAP2_END 56 #define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT) 57 58 #endif /* !(_SPARC_IO_UNIT_H) */ 59