1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg /* io-unit.h: Definitions for the sun4d IO-UNIT. 3a439fe51SSam Ravnborg * 4a439fe51SSam Ravnborg * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 5a439fe51SSam Ravnborg */ 6a439fe51SSam Ravnborg #ifndef _SPARC_IO_UNIT_H 7a439fe51SSam Ravnborg #define _SPARC_IO_UNIT_H 8a439fe51SSam Ravnborg 9a439fe51SSam Ravnborg #include <linux/spinlock.h> 10ca5999fdSMike Rapoport #include <linux/pgtable.h> 1165fddcfcSMike Rapoport #include <asm/page.h> 12a439fe51SSam Ravnborg 13a439fe51SSam Ravnborg /* The io-unit handles all virtual to physical address translations 14a439fe51SSam Ravnborg * that occur between the SBUS and physical memory. Access by 15a439fe51SSam Ravnborg * the cpu to IO registers and similar go over the xdbus so are 16a439fe51SSam Ravnborg * translated by the on chip SRMMU. The io-unit and the srmmu do 17a439fe51SSam Ravnborg * not need to have the same translations at all, in fact most 18a439fe51SSam Ravnborg * of the time the translations they handle are a disjunct set. 19a439fe51SSam Ravnborg * Basically the io-unit handles all dvma sbus activity. 20a439fe51SSam Ravnborg */ 21a439fe51SSam Ravnborg 22a439fe51SSam Ravnborg /* AIEEE, unlike the nice sun4m, these monsters have 23a439fe51SSam Ravnborg fixed DMA range 64M */ 24a439fe51SSam Ravnborg 25a439fe51SSam Ravnborg #define IOUNIT_DMA_BASE 0xfc000000 /* TOP - 64M */ 26a439fe51SSam Ravnborg #define IOUNIT_DMA_SIZE 0x04000000 /* 64M */ 27a439fe51SSam Ravnborg /* We use last 1M for sparc_dvma_malloc */ 28a439fe51SSam Ravnborg #define IOUNIT_DVMA_SIZE 0x00100000 /* 1M */ 29a439fe51SSam Ravnborg 30a439fe51SSam Ravnborg /* The format of an iopte in the external page tables */ 31a439fe51SSam Ravnborg #define IOUPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ 32a439fe51SSam Ravnborg #define IOUPTE_CACHE 0x00000080 /* Cached (in Viking/MXCC) */ 33a439fe51SSam Ravnborg /* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d. 34a439fe51SSam Ravnborg * XXX Actually, all you should need to do is find out where the registers 35a439fe51SSam Ravnborg * XXX are and copy over the sparc64 implementation I wrote. There may be 36a439fe51SSam Ravnborg * XXX some horrible hwbugs though, so be careful. -DaveM 37a439fe51SSam Ravnborg */ 38a439fe51SSam Ravnborg #define IOUPTE_STREAM 0x00000040 /* Translation can use streaming cache */ 39a439fe51SSam Ravnborg #define IOUPTE_INTRA 0x00000008 /* SBUS direct slot->slot transfer */ 40a439fe51SSam Ravnborg #define IOUPTE_WRITE 0x00000004 /* Writeable */ 41a439fe51SSam Ravnborg #define IOUPTE_VALID 0x00000002 /* IOPTE is valid */ 42a439fe51SSam Ravnborg #define IOUPTE_PARITY 0x00000001 /* Parity is checked during DVMA */ 43a439fe51SSam Ravnborg 44a439fe51SSam Ravnborg struct iounit_struct { 45a439fe51SSam Ravnborg unsigned long bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)]; 46a439fe51SSam Ravnborg spinlock_t lock; 471918660bSSam Ravnborg iopte_t __iomem *page_table; 48a439fe51SSam Ravnborg unsigned long rotor[3]; 49a439fe51SSam Ravnborg unsigned long limit[4]; 50a439fe51SSam Ravnborg }; 51a439fe51SSam Ravnborg 52a439fe51SSam Ravnborg #define IOUNIT_BMAP1_START 0x00000000 53a439fe51SSam Ravnborg #define IOUNIT_BMAP1_END (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1)) 54a439fe51SSam Ravnborg #define IOUNIT_BMAP2_START IOUNIT_BMAP1_END 55a439fe51SSam Ravnborg #define IOUNIT_BMAP2_END IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2)) 56a439fe51SSam Ravnborg #define IOUNIT_BMAPM_START IOUNIT_BMAP2_END 57a439fe51SSam Ravnborg #define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT) 58a439fe51SSam Ravnborg 59a439fe51SSam Ravnborg #endif /* !(_SPARC_IO_UNIT_H) */ 60