1 #ifndef _SPARC64_HYPERVISOR_H 2 #define _SPARC64_HYPERVISOR_H 3 4 /* Sun4v hypervisor interfaces and defines. 5 * 6 * Hypervisor calls are made via traps to software traps number 0x80 7 * and above. Registers %o0 to %o5 serve as argument, status, and 8 * return value registers. 9 * 10 * There are two kinds of these traps. First there are the normal 11 * "fast traps" which use software trap 0x80 and encode the function 12 * to invoke by number in register %o5. Argument and return value 13 * handling is as follows: 14 * 15 * ----------------------------------------------- 16 * | %o5 | function number | undefined | 17 * | %o0 | argument 0 | return status | 18 * | %o1 | argument 1 | return value 1 | 19 * | %o2 | argument 2 | return value 2 | 20 * | %o3 | argument 3 | return value 3 | 21 * | %o4 | argument 4 | return value 4 | 22 * ----------------------------------------------- 23 * 24 * The second type are "hyper-fast traps" which encode the function 25 * number in the software trap number itself. So these use trap 26 * numbers > 0x80. The register usage for hyper-fast traps is as 27 * follows: 28 * 29 * ----------------------------------------------- 30 * | %o0 | argument 0 | return status | 31 * | %o1 | argument 1 | return value 1 | 32 * | %o2 | argument 2 | return value 2 | 33 * | %o3 | argument 3 | return value 3 | 34 * | %o4 | argument 4 | return value 4 | 35 * ----------------------------------------------- 36 * 37 * Registers providing explicit arguments to the hypervisor calls 38 * are volatile across the call. Upon return their values are 39 * undefined unless explicitly specified as containing a particular 40 * return value by the specific call. The return status is always 41 * returned in register %o0, zero indicates a successful execution of 42 * the hypervisor call and other values indicate an error status as 43 * defined below. So, for example, if a hyper-fast trap takes 44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across 45 * the call and %o3, %o4, and %o5 would be preserved. 46 * 47 * If the hypervisor trap is invalid, or the fast trap function number 48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits 49 * of the argument and return values are significant. 50 */ 51 52 /* Trap numbers. */ 53 #define HV_FAST_TRAP 0x80 54 #define HV_MMU_MAP_ADDR_TRAP 0x83 55 #define HV_MMU_UNMAP_ADDR_TRAP 0x84 56 #define HV_TTRACE_ADDENTRY_TRAP 0x85 57 #define HV_CORE_TRAP 0xff 58 59 /* Error codes. */ 60 #define HV_EOK 0 /* Successful return */ 61 #define HV_ENOCPU 1 /* Invalid CPU id */ 62 #define HV_ENORADDR 2 /* Invalid real address */ 63 #define HV_ENOINTR 3 /* Invalid interrupt id */ 64 #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */ 65 #define HV_EBADTSB 5 /* Invalid TSB description */ 66 #define HV_EINVAL 6 /* Invalid argument */ 67 #define HV_EBADTRAP 7 /* Invalid function number */ 68 #define HV_EBADALIGN 8 /* Invalid address alignment */ 69 #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */ 70 #define HV_ENOACCESS 10 /* No access to resource */ 71 #define HV_EIO 11 /* I/O error */ 72 #define HV_ECPUERROR 12 /* CPU in error state */ 73 #define HV_ENOTSUPPORTED 13 /* Function not supported */ 74 #define HV_ENOMAP 14 /* No mapping found */ 75 #define HV_ETOOMANY 15 /* Too many items specified */ 76 #define HV_ECHANNEL 16 /* Invalid LDC channel */ 77 #define HV_EBUSY 17 /* Resource busy */ 78 79 /* mach_exit() 80 * TRAP: HV_FAST_TRAP 81 * FUNCTION: HV_FAST_MACH_EXIT 82 * ARG0: exit code 83 * ERRORS: This service does not return. 84 * 85 * Stop all CPUs in the virtual domain and place them into the stopped 86 * state. The 64-bit exit code may be passed to a service entity as 87 * the domain's exit status. On systems without a service entity, the 88 * domain will undergo a reset, and the boot firmware will be 89 * reloaded. 90 * 91 * This function will never return to the guest that invokes it. 92 * 93 * Note: By convention an exit code of zero denotes a successful exit by 94 * the guest code. A non-zero exit code denotes a guest specific 95 * error indication. 96 * 97 */ 98 #define HV_FAST_MACH_EXIT 0x00 99 100 #ifndef __ASSEMBLY__ 101 void sun4v_mach_exit(unsigned long exit_code); 102 #endif 103 104 /* Domain services. */ 105 106 /* mach_desc() 107 * TRAP: HV_FAST_TRAP 108 * FUNCTION: HV_FAST_MACH_DESC 109 * ARG0: buffer 110 * ARG1: length 111 * RET0: status 112 * RET1: length 113 * ERRORS: HV_EBADALIGN Buffer is badly aligned 114 * HV_ENORADDR Buffer is to an illegal real address. 115 * HV_EINVAL Buffer length is too small for complete 116 * machine description. 117 * 118 * Copy the most current machine description into the buffer indicated 119 * by the real address in ARG0. The buffer provided must be 16 byte 120 * aligned. Upon success or HV_EINVAL, this service returns the 121 * actual size of the machine description in the RET1 return value. 122 * 123 * Note: A method of determining the appropriate buffer size for the 124 * machine description is to first call this service with a buffer 125 * length of 0 bytes. 126 */ 127 #define HV_FAST_MACH_DESC 0x01 128 129 #ifndef __ASSEMBLY__ 130 unsigned long sun4v_mach_desc(unsigned long buffer_pa, 131 unsigned long buf_len, 132 unsigned long *real_buf_len); 133 #endif 134 135 /* mach_sir() 136 * TRAP: HV_FAST_TRAP 137 * FUNCTION: HV_FAST_MACH_SIR 138 * ERRORS: This service does not return. 139 * 140 * Perform a software initiated reset of the virtual machine domain. 141 * All CPUs are captured as soon as possible, all hardware devices are 142 * returned to the entry default state, and the domain is restarted at 143 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one 144 * of the CPUs. The single CPU restarted is selected as determined by 145 * platform specific policy. Memory is preserved across this 146 * operation. 147 */ 148 #define HV_FAST_MACH_SIR 0x02 149 150 #ifndef __ASSEMBLY__ 151 void sun4v_mach_sir(void); 152 #endif 153 154 /* mach_set_watchdog() 155 * TRAP: HV_FAST_TRAP 156 * FUNCTION: HV_FAST_MACH_SET_WATCHDOG 157 * ARG0: timeout in milliseconds 158 * RET0: status 159 * RET1: time remaining in milliseconds 160 * 161 * A guest uses this API to set a watchdog timer. Once the gues has set 162 * the timer, it must call the timer service again either to disable or 163 * postpone the expiration. If the timer expires before being reset or 164 * disabled, then the hypervisor take a platform specific action leading 165 * to guest termination within a bounded time period. The platform action 166 * may include recovery actions such as reporting the expiration to a 167 * Service Processor, and/or automatically restarting the gues. 168 * 169 * The 'timeout' parameter is specified in milliseconds, however the 170 * implementated granularity is given by the 'watchdog-resolution' 171 * property in the 'platform' node of the guest's machine description. 172 * The largest allowed timeout value is specified by the 173 * 'watchdog-max-timeout' property of the 'platform' node. 174 * 175 * If the 'timeout' argument is not zero, the watchdog timer is set to 176 * expire after a minimum of 'timeout' milliseconds. 177 * 178 * If the 'timeout' argument is zero, the watchdog timer is disabled. 179 * 180 * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout' 181 * property, the hypervisor leaves the watchdog timer state unchanged, 182 * and returns a status of EINVAL. 183 * 184 * The 'time remaining' return value is valid regardless of whether the 185 * return status is EOK or EINVAL. A non-zero return value indicates the 186 * number of milliseconds that were remaining until the timer was to expire. 187 * If less than one millisecond remains, the return value is '1'. If the 188 * watchdog timer was disabled at the time of the call, the return value is 189 * zero. 190 * 191 * If the hypervisor cannot support the exact timeout value requested, but 192 * can support a larger timeout value, the hypervisor may round the actual 193 * timeout to a value larger than the requested timeout, consequently the 194 * 'time remaining' return value may be larger than the previously requested 195 * timeout value. 196 * 197 * Any guest OS debugger should be aware that the watchdog service may be in 198 * use. Consequently, it is recommended that the watchdog service is 199 * disabled upon debugger entry (e.g. reaching a breakpoint), and then 200 * re-enabled upon returning to normal execution. The API has been designed 201 * with this in mind, and the 'time remaining' result of the disable call may 202 * be used directly as the timeout argument of the re-enable call. 203 */ 204 #define HV_FAST_MACH_SET_WATCHDOG 0x05 205 206 #ifndef __ASSEMBLY__ 207 unsigned long sun4v_mach_set_watchdog(unsigned long timeout, 208 unsigned long *orig_timeout); 209 #endif 210 211 /* CPU services. 212 * 213 * CPUs represent devices that can execute software threads. A single 214 * chip that contains multiple cores or strands is represented as 215 * multiple CPUs with unique CPU identifiers. CPUs are exported to 216 * OBP via the machine description (and to the OS via the OBP device 217 * tree). CPUs are always in one of three states: stopped, running, 218 * or error. 219 * 220 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a 221 * CPU within a logical domain. Operations that are to be performed 222 * on multiple CPUs specify them via a CPU list. A CPU list is an 223 * array in real memory, of which each 16-bit word is a CPU ID. CPU 224 * lists are passed through the API as two arguments. The first is 225 * the number of entries (16-bit words) in the CPU list, and the 226 * second is the (real address) pointer to the CPU ID list. 227 */ 228 229 /* cpu_start() 230 * TRAP: HV_FAST_TRAP 231 * FUNCTION: HV_FAST_CPU_START 232 * ARG0: CPU ID 233 * ARG1: PC 234 * ARG2: RTBA 235 * ARG3: target ARG0 236 * RET0: status 237 * ERRORS: ENOCPU Invalid CPU ID 238 * EINVAL Target CPU ID is not in the stopped state 239 * ENORADDR Invalid PC or RTBA real address 240 * EBADALIGN Unaligned PC or unaligned RTBA 241 * EWOULDBLOCK Starting resources are not available 242 * 243 * Start CPU with given CPU ID with PC in %pc and with a real trap 244 * base address value of RTBA. The indicated CPU must be in the 245 * stopped state. The supplied RTBA must be aligned on a 256 byte 246 * boundary. On successful completion, the specified CPU will be in 247 * the running state and will be supplied with "target ARG0" in %o0 248 * and RTBA in %tba. 249 */ 250 #define HV_FAST_CPU_START 0x10 251 252 #ifndef __ASSEMBLY__ 253 unsigned long sun4v_cpu_start(unsigned long cpuid, 254 unsigned long pc, 255 unsigned long rtba, 256 unsigned long arg0); 257 #endif 258 259 /* cpu_stop() 260 * TRAP: HV_FAST_TRAP 261 * FUNCTION: HV_FAST_CPU_STOP 262 * ARG0: CPU ID 263 * RET0: status 264 * ERRORS: ENOCPU Invalid CPU ID 265 * EINVAL Target CPU ID is the current cpu 266 * EINVAL Target CPU ID is not in the running state 267 * EWOULDBLOCK Stopping resources are not available 268 * ENOTSUPPORTED Not supported on this platform 269 * 270 * The specified CPU is stopped. The indicated CPU must be in the 271 * running state. On completion, it will be in the stopped state. It 272 * is not legal to stop the current CPU. 273 * 274 * Note: As this service cannot be used to stop the current cpu, this service 275 * may not be used to stop the last running CPU in a domain. To stop 276 * and exit a running domain, a guest must use the mach_exit() service. 277 */ 278 #define HV_FAST_CPU_STOP 0x11 279 280 #ifndef __ASSEMBLY__ 281 unsigned long sun4v_cpu_stop(unsigned long cpuid); 282 #endif 283 284 /* cpu_yield() 285 * TRAP: HV_FAST_TRAP 286 * FUNCTION: HV_FAST_CPU_YIELD 287 * RET0: status 288 * ERRORS: No possible error. 289 * 290 * Suspend execution on the current CPU. Execution will resume when 291 * an interrupt (device, %stick_compare, or cross-call) is targeted to 292 * the CPU. On some CPUs, this API may be used by the hypervisor to 293 * save power by disabling hardware strands. 294 */ 295 #define HV_FAST_CPU_YIELD 0x12 296 297 #ifndef __ASSEMBLY__ 298 unsigned long sun4v_cpu_yield(void); 299 #endif 300 301 /* cpu_poke() 302 * TRAP: HV_FAST_TRAP 303 * FUNCTION: HV_FAST_CPU_POKE 304 * RET0: status 305 * ERRORS: ENOCPU cpuid refers to a CPU that does not exist 306 * EINVAL cpuid is current CPU 307 * 308 * Poke CPU cpuid. If the target CPU is currently suspended having 309 * invoked the cpu-yield service, that vCPU will be resumed. 310 * Poke interrupts may only be sent to valid, non-local CPUs. 311 * It is not legal to poke the current vCPU. 312 */ 313 #define HV_FAST_CPU_POKE 0x13 314 315 #ifndef __ASSEMBLY__ 316 unsigned long sun4v_cpu_poke(unsigned long cpuid); 317 #endif 318 319 /* cpu_qconf() 320 * TRAP: HV_FAST_TRAP 321 * FUNCTION: HV_FAST_CPU_QCONF 322 * ARG0: queue 323 * ARG1: base real address 324 * ARG2: number of entries 325 * RET0: status 326 * ERRORS: ENORADDR Invalid base real address 327 * EINVAL Invalid queue or number of entries is less 328 * than 2 or too large. 329 * EBADALIGN Base real address is not correctly aligned 330 * for size. 331 * 332 * Configure the given queue to be placed at the given base real 333 * address, with the given number of entries. The number of entries 334 * must be a power of 2. The base real address must be aligned 335 * exactly to match the queue size. Each queue entry is 64 bytes 336 * long, so for example a 32 entry queue must be aligned on a 2048 337 * byte real address boundary. 338 * 339 * The specified queue is unconfigured if the number of entries is given 340 * as zero. 341 * 342 * For the current version of this API service, the argument queue is defined 343 * as follows: 344 * 345 * queue description 346 * ----- ------------------------- 347 * 0x3c cpu mondo queue 348 * 0x3d device mondo queue 349 * 0x3e resumable error queue 350 * 0x3f non-resumable error queue 351 * 352 * Note: The maximum number of entries for each queue for a specific cpu may 353 * be determined from the machine description. 354 */ 355 #define HV_FAST_CPU_QCONF 0x14 356 #define HV_CPU_QUEUE_CPU_MONDO 0x3c 357 #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d 358 #define HV_CPU_QUEUE_RES_ERROR 0x3e 359 #define HV_CPU_QUEUE_NONRES_ERROR 0x3f 360 361 #ifndef __ASSEMBLY__ 362 unsigned long sun4v_cpu_qconf(unsigned long type, 363 unsigned long queue_paddr, 364 unsigned long num_queue_entries); 365 #endif 366 367 /* cpu_qinfo() 368 * TRAP: HV_FAST_TRAP 369 * FUNCTION: HV_FAST_CPU_QINFO 370 * ARG0: queue 371 * RET0: status 372 * RET1: base real address 373 * RET1: number of entries 374 * ERRORS: EINVAL Invalid queue 375 * 376 * Return the configuration info for the given queue. The base real 377 * address and number of entries of the defined queue are returned. 378 * The queue argument values are the same as for cpu_qconf() above. 379 * 380 * If the specified queue is a valid queue number, but no queue has 381 * been defined, the number of entries will be set to zero and the 382 * base real address returned is undefined. 383 */ 384 #define HV_FAST_CPU_QINFO 0x15 385 386 /* cpu_mondo_send() 387 * TRAP: HV_FAST_TRAP 388 * FUNCTION: HV_FAST_CPU_MONDO_SEND 389 * ARG0-1: CPU list 390 * ARG2: data real address 391 * RET0: status 392 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list 393 * is not 2-byte aligned. 394 * ENORADDR Invalid data mondo address, or invalid cpu list 395 * address. 396 * ENOCPU Invalid cpu in CPU list 397 * EWOULDBLOCK Some or all of the listed CPUs did not receive 398 * the mondo 399 * ECPUERROR One or more of the listed CPUs are in error 400 * state, use HV_FAST_CPU_STATE to see which ones 401 * EINVAL CPU list includes caller's CPU ID 402 * 403 * Send a mondo interrupt to the CPUs in the given CPU list with the 404 * 64-bytes at the given data real address. The data must be 64-byte 405 * aligned. The mondo data will be delivered to the cpu_mondo queues 406 * of the recipient CPUs. 407 * 408 * In all cases, error or not, the CPUs in the CPU list to which the 409 * mondo has been successfully delivered will be indicated by having 410 * their entry in CPU list updated with the value 0xffff. 411 */ 412 #define HV_FAST_CPU_MONDO_SEND 0x42 413 414 #ifndef __ASSEMBLY__ 415 unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, 416 unsigned long cpu_list_pa, 417 unsigned long mondo_block_pa); 418 #endif 419 420 /* cpu_myid() 421 * TRAP: HV_FAST_TRAP 422 * FUNCTION: HV_FAST_CPU_MYID 423 * RET0: status 424 * RET1: CPU ID 425 * ERRORS: No errors defined. 426 * 427 * Return the hypervisor ID handle for the current CPU. Use by a 428 * virtual CPU to discover it's own identity. 429 */ 430 #define HV_FAST_CPU_MYID 0x16 431 432 /* cpu_state() 433 * TRAP: HV_FAST_TRAP 434 * FUNCTION: HV_FAST_CPU_STATE 435 * ARG0: CPU ID 436 * RET0: status 437 * RET1: state 438 * ERRORS: ENOCPU Invalid CPU ID 439 * 440 * Retrieve the current state of the CPU with the given CPU ID. 441 */ 442 #define HV_FAST_CPU_STATE 0x17 443 #define HV_CPU_STATE_STOPPED 0x01 444 #define HV_CPU_STATE_RUNNING 0x02 445 #define HV_CPU_STATE_ERROR 0x03 446 447 #ifndef __ASSEMBLY__ 448 long sun4v_cpu_state(unsigned long cpuid); 449 #endif 450 451 /* cpu_set_rtba() 452 * TRAP: HV_FAST_TRAP 453 * FUNCTION: HV_FAST_CPU_SET_RTBA 454 * ARG0: RTBA 455 * RET0: status 456 * RET1: previous RTBA 457 * ERRORS: ENORADDR Invalid RTBA real address 458 * EBADALIGN RTBA is incorrectly aligned for a trap table 459 * 460 * Set the real trap base address of the local cpu to the given RTBA. 461 * The supplied RTBA must be aligned on a 256 byte boundary. Upon 462 * success the previous value of the RTBA is returned in RET1. 463 * 464 * Note: This service does not affect %tba 465 */ 466 #define HV_FAST_CPU_SET_RTBA 0x18 467 468 /* cpu_set_rtba() 469 * TRAP: HV_FAST_TRAP 470 * FUNCTION: HV_FAST_CPU_GET_RTBA 471 * RET0: status 472 * RET1: previous RTBA 473 * ERRORS: No possible error. 474 * 475 * Returns the current value of RTBA in RET1. 476 */ 477 #define HV_FAST_CPU_GET_RTBA 0x19 478 479 /* MMU services. 480 * 481 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls. 482 */ 483 #ifndef __ASSEMBLY__ 484 struct hv_tsb_descr { 485 unsigned short pgsz_idx; 486 unsigned short assoc; 487 unsigned int num_ttes; /* in TTEs */ 488 unsigned int ctx_idx; 489 unsigned int pgsz_mask; 490 unsigned long tsb_base; 491 unsigned long resv; 492 }; 493 #endif 494 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00 495 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02 496 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04 497 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08 498 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c 499 #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10 500 #define HV_TSB_DESCR_RESV_OFFSET 0x18 501 502 /* Page size bitmask. */ 503 #define HV_PGSZ_MASK_8K (1 << 0) 504 #define HV_PGSZ_MASK_64K (1 << 1) 505 #define HV_PGSZ_MASK_512K (1 << 2) 506 #define HV_PGSZ_MASK_4MB (1 << 3) 507 #define HV_PGSZ_MASK_32MB (1 << 4) 508 #define HV_PGSZ_MASK_256MB (1 << 5) 509 #define HV_PGSZ_MASK_2GB (1 << 6) 510 #define HV_PGSZ_MASK_16GB (1 << 7) 511 512 /* Page size index. The value given in the TSB descriptor must correspond 513 * to the smallest page size specified in the pgsz_mask page size bitmask. 514 */ 515 #define HV_PGSZ_IDX_8K 0 516 #define HV_PGSZ_IDX_64K 1 517 #define HV_PGSZ_IDX_512K 2 518 #define HV_PGSZ_IDX_4MB 3 519 #define HV_PGSZ_IDX_32MB 4 520 #define HV_PGSZ_IDX_256MB 5 521 #define HV_PGSZ_IDX_2GB 6 522 #define HV_PGSZ_IDX_16GB 7 523 524 /* MMU fault status area. 525 * 526 * MMU related faults have their status and fault address information 527 * placed into a memory region made available by privileged code. Each 528 * virtual processor must make a mmu_fault_area_conf() call to tell the 529 * hypervisor where that processor's fault status should be stored. 530 * 531 * The fault status block is a multiple of 64-bytes and must be aligned 532 * on a 64-byte boundary. 533 */ 534 #ifndef __ASSEMBLY__ 535 struct hv_fault_status { 536 unsigned long i_fault_type; 537 unsigned long i_fault_addr; 538 unsigned long i_fault_ctx; 539 unsigned long i_reserved[5]; 540 unsigned long d_fault_type; 541 unsigned long d_fault_addr; 542 unsigned long d_fault_ctx; 543 unsigned long d_reserved[5]; 544 }; 545 #endif 546 #define HV_FAULT_I_TYPE_OFFSET 0x00 547 #define HV_FAULT_I_ADDR_OFFSET 0x08 548 #define HV_FAULT_I_CTX_OFFSET 0x10 549 #define HV_FAULT_D_TYPE_OFFSET 0x40 550 #define HV_FAULT_D_ADDR_OFFSET 0x48 551 #define HV_FAULT_D_CTX_OFFSET 0x50 552 553 #define HV_FAULT_TYPE_FAST_MISS 1 554 #define HV_FAULT_TYPE_FAST_PROT 2 555 #define HV_FAULT_TYPE_MMU_MISS 3 556 #define HV_FAULT_TYPE_INV_RA 4 557 #define HV_FAULT_TYPE_PRIV_VIOL 5 558 #define HV_FAULT_TYPE_PROT_VIOL 6 559 #define HV_FAULT_TYPE_NFO 7 560 #define HV_FAULT_TYPE_NFO_SEFF 8 561 #define HV_FAULT_TYPE_INV_VA 9 562 #define HV_FAULT_TYPE_INV_ASI 10 563 #define HV_FAULT_TYPE_NC_ATOMIC 11 564 #define HV_FAULT_TYPE_PRIV_ACT 12 565 #define HV_FAULT_TYPE_RESV1 13 566 #define HV_FAULT_TYPE_UNALIGNED 14 567 #define HV_FAULT_TYPE_INV_PGSZ 15 568 /* Values 16 --> -2 are reserved. */ 569 #define HV_FAULT_TYPE_MULTIPLE -1 570 571 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(), 572 * and mmu_{map,unmap}_perm_addr(). 573 */ 574 #define HV_MMU_DMMU 0x01 575 #define HV_MMU_IMMU 0x02 576 #define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU) 577 578 /* mmu_map_addr() 579 * TRAP: HV_MMU_MAP_ADDR_TRAP 580 * ARG0: virtual address 581 * ARG1: mmu context 582 * ARG2: TTE 583 * ARG3: flags (HV_MMU_{IMMU,DMMU}) 584 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags 585 * EBADPGSZ Invalid page size value 586 * ENORADDR Invalid real address in TTE 587 * 588 * Create a non-permanent mapping using the given TTE, virtual 589 * address, and mmu context. The flags argument determines which 590 * (data, or instruction, or both) TLB the mapping gets loaded into. 591 * 592 * The behavior is undefined if the valid bit is clear in the TTE. 593 * 594 * Note: This API call is for privileged code to specify temporary translation 595 * mappings without the need to create and manage a TSB. 596 */ 597 598 /* mmu_unmap_addr() 599 * TRAP: HV_MMU_UNMAP_ADDR_TRAP 600 * ARG0: virtual address 601 * ARG1: mmu context 602 * ARG2: flags (HV_MMU_{IMMU,DMMU}) 603 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags 604 * 605 * Demaps the given virtual address in the given mmu context on this 606 * CPU. This function is intended to be used to demap pages mapped 607 * with mmu_map_addr. This service is equivalent to invoking 608 * mmu_demap_page() with only the current CPU in the CPU list. The 609 * flags argument determines which (data, or instruction, or both) TLB 610 * the mapping gets unmapped from. 611 * 612 * Attempting to perform an unmap operation for a previously defined 613 * permanent mapping will have undefined results. 614 */ 615 616 /* mmu_tsb_ctx0() 617 * TRAP: HV_FAST_TRAP 618 * FUNCTION: HV_FAST_MMU_TSB_CTX0 619 * ARG0: number of TSB descriptions 620 * ARG1: TSB descriptions pointer 621 * RET0: status 622 * ERRORS: ENORADDR Invalid TSB descriptions pointer or 623 * TSB base within a descriptor 624 * EBADALIGN TSB descriptions pointer is not aligned 625 * to an 8-byte boundary, or TSB base 626 * within a descriptor is not aligned for 627 * the given TSB size 628 * EBADPGSZ Invalid page size in a TSB descriptor 629 * EBADTSB Invalid associativity or size in a TSB 630 * descriptor 631 * EINVAL Invalid number of TSB descriptions, or 632 * invalid context index in a TSB 633 * descriptor, or index page size not 634 * equal to smallest page size in page 635 * size bitmask field. 636 * 637 * Configures the TSBs for the current CPU for virtual addresses with 638 * context zero. The TSB descriptions pointer is a pointer to an 639 * array of the given number of TSB descriptions. 640 * 641 * Note: The maximum number of TSBs available to a virtual CPU is given by the 642 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the 643 * machine description. 644 */ 645 #define HV_FAST_MMU_TSB_CTX0 0x20 646 647 #ifndef __ASSEMBLY__ 648 unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions, 649 unsigned long tsb_desc_ra); 650 #endif 651 652 /* mmu_tsb_ctxnon0() 653 * TRAP: HV_FAST_TRAP 654 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0 655 * ARG0: number of TSB descriptions 656 * ARG1: TSB descriptions pointer 657 * RET0: status 658 * ERRORS: Same as for mmu_tsb_ctx0() above. 659 * 660 * Configures the TSBs for the current CPU for virtual addresses with 661 * non-zero contexts. The TSB descriptions pointer is a pointer to an 662 * array of the given number of TSB descriptions. 663 * 664 * Note: A maximum of 16 TSBs may be specified in the TSB description list. 665 */ 666 #define HV_FAST_MMU_TSB_CTXNON0 0x21 667 668 /* mmu_demap_page() 669 * TRAP: HV_FAST_TRAP 670 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE 671 * ARG0: reserved, must be zero 672 * ARG1: reserved, must be zero 673 * ARG2: virtual address 674 * ARG3: mmu context 675 * ARG4: flags (HV_MMU_{IMMU,DMMU}) 676 * RET0: status 677 * ERRORS: EINVAL Invalid virtual address, context, or 678 * flags value 679 * ENOTSUPPORTED ARG0 or ARG1 is non-zero 680 * 681 * Demaps any page mapping of the given virtual address in the given 682 * mmu context for the current virtual CPU. Any virtually tagged 683 * caches are guaranteed to be kept consistent. The flags argument 684 * determines which TLB (instruction, or data, or both) participate in 685 * the operation. 686 * 687 * ARG0 and ARG1 are both reserved and must be set to zero. 688 */ 689 #define HV_FAST_MMU_DEMAP_PAGE 0x22 690 691 /* mmu_demap_ctx() 692 * TRAP: HV_FAST_TRAP 693 * FUNCTION: HV_FAST_MMU_DEMAP_CTX 694 * ARG0: reserved, must be zero 695 * ARG1: reserved, must be zero 696 * ARG2: mmu context 697 * ARG3: flags (HV_MMU_{IMMU,DMMU}) 698 * RET0: status 699 * ERRORS: EINVAL Invalid context or flags value 700 * ENOTSUPPORTED ARG0 or ARG1 is non-zero 701 * 702 * Demaps all non-permanent virtual page mappings previously specified 703 * for the given context for the current virtual CPU. Any virtual 704 * tagged caches are guaranteed to be kept consistent. The flags 705 * argument determines which TLB (instruction, or data, or both) 706 * participate in the operation. 707 * 708 * ARG0 and ARG1 are both reserved and must be set to zero. 709 */ 710 #define HV_FAST_MMU_DEMAP_CTX 0x23 711 712 /* mmu_demap_all() 713 * TRAP: HV_FAST_TRAP 714 * FUNCTION: HV_FAST_MMU_DEMAP_ALL 715 * ARG0: reserved, must be zero 716 * ARG1: reserved, must be zero 717 * ARG2: flags (HV_MMU_{IMMU,DMMU}) 718 * RET0: status 719 * ERRORS: EINVAL Invalid flags value 720 * ENOTSUPPORTED ARG0 or ARG1 is non-zero 721 * 722 * Demaps all non-permanent virtual page mappings previously specified 723 * for the current virtual CPU. Any virtual tagged caches are 724 * guaranteed to be kept consistent. The flags argument determines 725 * which TLB (instruction, or data, or both) participate in the 726 * operation. 727 * 728 * ARG0 and ARG1 are both reserved and must be set to zero. 729 */ 730 #define HV_FAST_MMU_DEMAP_ALL 0x24 731 732 #ifndef __ASSEMBLY__ 733 void sun4v_mmu_demap_all(void); 734 #endif 735 736 /* mmu_map_perm_addr() 737 * TRAP: HV_FAST_TRAP 738 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR 739 * ARG0: virtual address 740 * ARG1: reserved, must be zero 741 * ARG2: TTE 742 * ARG3: flags (HV_MMU_{IMMU,DMMU}) 743 * RET0: status 744 * ERRORS: EINVAL Invalid virtual address or flags value 745 * EBADPGSZ Invalid page size value 746 * ENORADDR Invalid real address in TTE 747 * ETOOMANY Too many mappings (max of 8 reached) 748 * 749 * Create a permanent mapping using the given TTE and virtual address 750 * for context 0 on the calling virtual CPU. A maximum of 8 such 751 * permanent mappings may be specified by privileged code. Mappings 752 * may be removed with mmu_unmap_perm_addr(). 753 * 754 * The behavior is undefined if a TTE with the valid bit clear is given. 755 * 756 * Note: This call is used to specify address space mappings for which 757 * privileged code does not expect to receive misses. For example, 758 * this mechanism can be used to map kernel nucleus code and data. 759 */ 760 #define HV_FAST_MMU_MAP_PERM_ADDR 0x25 761 762 #ifndef __ASSEMBLY__ 763 unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr, 764 unsigned long set_to_zero, 765 unsigned long tte, 766 unsigned long flags); 767 #endif 768 769 /* mmu_fault_area_conf() 770 * TRAP: HV_FAST_TRAP 771 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF 772 * ARG0: real address 773 * RET0: status 774 * RET1: previous mmu fault area real address 775 * ERRORS: ENORADDR Invalid real address 776 * EBADALIGN Invalid alignment for fault area 777 * 778 * Configure the MMU fault status area for the calling CPU. A 64-byte 779 * aligned real address specifies where MMU fault status information 780 * is placed. The return value is the previously specified area, or 0 781 * for the first invocation. Specifying a fault area at real address 782 * 0 is not allowed. 783 */ 784 #define HV_FAST_MMU_FAULT_AREA_CONF 0x26 785 786 /* mmu_enable() 787 * TRAP: HV_FAST_TRAP 788 * FUNCTION: HV_FAST_MMU_ENABLE 789 * ARG0: enable flag 790 * ARG1: return target address 791 * RET0: status 792 * ERRORS: ENORADDR Invalid real address when disabling 793 * translation. 794 * EBADALIGN The return target address is not 795 * aligned to an instruction. 796 * EINVAL The enable flag request the current 797 * operating mode (e.g. disable if already 798 * disabled) 799 * 800 * Enable or disable virtual address translation for the calling CPU 801 * within the virtual machine domain. If the enable flag is zero, 802 * translation is disabled, any non-zero value will enable 803 * translation. 804 * 805 * When this function returns, the newly selected translation mode 806 * will be active. If the mmu is being enabled, then the return 807 * target address is a virtual address else it is a real address. 808 * 809 * Upon successful completion, control will be returned to the given 810 * return target address (ie. the cpu will jump to that address). On 811 * failure, the previous mmu mode remains and the trap simply returns 812 * as normal with the appropriate error code in RET0. 813 */ 814 #define HV_FAST_MMU_ENABLE 0x27 815 816 /* mmu_unmap_perm_addr() 817 * TRAP: HV_FAST_TRAP 818 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR 819 * ARG0: virtual address 820 * ARG1: reserved, must be zero 821 * ARG2: flags (HV_MMU_{IMMU,DMMU}) 822 * RET0: status 823 * ERRORS: EINVAL Invalid virtual address or flags value 824 * ENOMAP Specified mapping was not found 825 * 826 * Demaps any permanent page mapping (established via 827 * mmu_map_perm_addr()) at the given virtual address for context 0 on 828 * the current virtual CPU. Any virtual tagged caches are guaranteed 829 * to be kept consistent. 830 */ 831 #define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28 832 833 /* mmu_tsb_ctx0_info() 834 * TRAP: HV_FAST_TRAP 835 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO 836 * ARG0: max TSBs 837 * ARG1: buffer pointer 838 * RET0: status 839 * RET1: number of TSBs 840 * ERRORS: EINVAL Supplied buffer is too small 841 * EBADALIGN The buffer pointer is badly aligned 842 * ENORADDR Invalid real address for buffer pointer 843 * 844 * Return the TSB configuration as previous defined by mmu_tsb_ctx0() 845 * into the provided buffer. The size of the buffer is given in ARG1 846 * in terms of the number of TSB description entries. 847 * 848 * Upon return, RET1 always contains the number of TSB descriptions 849 * previously configured. If zero TSBs were configured, EOK is 850 * returned with RET1 containing 0. 851 */ 852 #define HV_FAST_MMU_TSB_CTX0_INFO 0x29 853 854 /* mmu_tsb_ctxnon0_info() 855 * TRAP: HV_FAST_TRAP 856 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO 857 * ARG0: max TSBs 858 * ARG1: buffer pointer 859 * RET0: status 860 * RET1: number of TSBs 861 * ERRORS: EINVAL Supplied buffer is too small 862 * EBADALIGN The buffer pointer is badly aligned 863 * ENORADDR Invalid real address for buffer pointer 864 * 865 * Return the TSB configuration as previous defined by 866 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer 867 * is given in ARG1 in terms of the number of TSB description entries. 868 * 869 * Upon return, RET1 always contains the number of TSB descriptions 870 * previously configured. If zero TSBs were configured, EOK is 871 * returned with RET1 containing 0. 872 */ 873 #define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a 874 875 /* mmu_fault_area_info() 876 * TRAP: HV_FAST_TRAP 877 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO 878 * RET0: status 879 * RET1: fault area real address 880 * ERRORS: No errors defined. 881 * 882 * Return the currently defined MMU fault status area for the current 883 * CPU. The real address of the fault status area is returned in 884 * RET1, or 0 is returned in RET1 if no fault status area is defined. 885 * 886 * Note: mmu_fault_area_conf() may be called with the return value (RET1) 887 * from this service if there is a need to save and restore the fault 888 * area for a cpu. 889 */ 890 #define HV_FAST_MMU_FAULT_AREA_INFO 0x2b 891 892 /* Cache and Memory services. */ 893 894 /* mem_scrub() 895 * TRAP: HV_FAST_TRAP 896 * FUNCTION: HV_FAST_MEM_SCRUB 897 * ARG0: real address 898 * ARG1: length 899 * RET0: status 900 * RET1: length scrubbed 901 * ERRORS: ENORADDR Invalid real address 902 * EBADALIGN Start address or length are not correctly 903 * aligned 904 * EINVAL Length is zero 905 * 906 * Zero the memory contents in the range real address to real address 907 * plus length minus 1. Also, valid ECC will be generated for that 908 * memory address range. Scrubbing is started at the given real 909 * address, but may not scrub the entire given length. The actual 910 * length scrubbed will be returned in RET1. 911 * 912 * The real address and length must be aligned on an 8K boundary, or 913 * contain the start address and length from a sun4v error report. 914 * 915 * Note: There are two uses for this function. The first use is to block clear 916 * and initialize memory and the second is to scrub an u ncorrectable 917 * error reported via a resumable or non-resumable trap. The second 918 * use requires the arguments to be equal to the real address and length 919 * provided in a sun4v memory error report. 920 */ 921 #define HV_FAST_MEM_SCRUB 0x31 922 923 /* mem_sync() 924 * TRAP: HV_FAST_TRAP 925 * FUNCTION: HV_FAST_MEM_SYNC 926 * ARG0: real address 927 * ARG1: length 928 * RET0: status 929 * RET1: length synced 930 * ERRORS: ENORADDR Invalid real address 931 * EBADALIGN Start address or length are not correctly 932 * aligned 933 * EINVAL Length is zero 934 * 935 * Force the next access within the real address to real address plus 936 * length minus 1 to be fetches from main system memory. Less than 937 * the given length may be synced, the actual amount synced is 938 * returned in RET1. The real address and length must be aligned on 939 * an 8K boundary. 940 */ 941 #define HV_FAST_MEM_SYNC 0x32 942 943 /* Time of day services. 944 * 945 * The hypervisor maintains the time of day on a per-domain basis. 946 * Changing the time of day in one domain does not affect the time of 947 * day on any other domain. 948 * 949 * Time is described by a single unsigned 64-bit word which is the 950 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1, 951 * 1970). 952 */ 953 954 /* tod_get() 955 * TRAP: HV_FAST_TRAP 956 * FUNCTION: HV_FAST_TOD_GET 957 * RET0: status 958 * RET1: TOD 959 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable 960 * ENOTSUPPORTED If TOD not supported on this platform 961 * 962 * Return the current time of day. May block if TOD access is 963 * temporarily not possible. 964 */ 965 #define HV_FAST_TOD_GET 0x50 966 967 #ifndef __ASSEMBLY__ 968 unsigned long sun4v_tod_get(unsigned long *time); 969 #endif 970 971 /* tod_set() 972 * TRAP: HV_FAST_TRAP 973 * FUNCTION: HV_FAST_TOD_SET 974 * ARG0: TOD 975 * RET0: status 976 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable 977 * ENOTSUPPORTED If TOD not supported on this platform 978 * 979 * The current time of day is set to the value specified in ARG0. May 980 * block if TOD access is temporarily not possible. 981 */ 982 #define HV_FAST_TOD_SET 0x51 983 984 #ifndef __ASSEMBLY__ 985 unsigned long sun4v_tod_set(unsigned long time); 986 #endif 987 988 /* Console services */ 989 990 /* con_getchar() 991 * TRAP: HV_FAST_TRAP 992 * FUNCTION: HV_FAST_CONS_GETCHAR 993 * RET0: status 994 * RET1: character 995 * ERRORS: EWOULDBLOCK No character available. 996 * 997 * Returns a character from the console device. If no character is 998 * available then an EWOULDBLOCK error is returned. If a character is 999 * available, then the returned status is EOK and the character value 1000 * is in RET1. 1001 * 1002 * A virtual BREAK is represented by the 64-bit value -1. 1003 * 1004 * A virtual HUP signal is represented by the 64-bit value -2. 1005 */ 1006 #define HV_FAST_CONS_GETCHAR 0x60 1007 1008 /* con_putchar() 1009 * TRAP: HV_FAST_TRAP 1010 * FUNCTION: HV_FAST_CONS_PUTCHAR 1011 * ARG0: character 1012 * RET0: status 1013 * ERRORS: EINVAL Illegal character 1014 * EWOULDBLOCK Output buffer currently full, would block 1015 * 1016 * Send a character to the console device. Only character values 1017 * between 0 and 255 may be used. Values outside this range are 1018 * invalid except for the 64-bit value -1 which is used to send a 1019 * virtual BREAK. 1020 */ 1021 #define HV_FAST_CONS_PUTCHAR 0x61 1022 1023 /* con_read() 1024 * TRAP: HV_FAST_TRAP 1025 * FUNCTION: HV_FAST_CONS_READ 1026 * ARG0: buffer real address 1027 * ARG1: buffer size in bytes 1028 * RET0: status 1029 * RET1: bytes read or BREAK or HUP 1030 * ERRORS: EWOULDBLOCK No character available. 1031 * 1032 * Reads characters into a buffer from the console device. If no 1033 * character is available then an EWOULDBLOCK error is returned. 1034 * If a character is available, then the returned status is EOK 1035 * and the number of bytes read into the given buffer is provided 1036 * in RET1. 1037 * 1038 * A virtual BREAK is represented by the 64-bit RET1 value -1. 1039 * 1040 * A virtual HUP signal is represented by the 64-bit RET1 value -2. 1041 * 1042 * If BREAK or HUP are indicated, no bytes were read into buffer. 1043 */ 1044 #define HV_FAST_CONS_READ 0x62 1045 1046 /* con_write() 1047 * TRAP: HV_FAST_TRAP 1048 * FUNCTION: HV_FAST_CONS_WRITE 1049 * ARG0: buffer real address 1050 * ARG1: buffer size in bytes 1051 * RET0: status 1052 * RET1: bytes written 1053 * ERRORS: EWOULDBLOCK Output buffer currently full, would block 1054 * 1055 * Send a characters in buffer to the console device. Breaks must be 1056 * sent using con_putchar(). 1057 */ 1058 #define HV_FAST_CONS_WRITE 0x63 1059 1060 #ifndef __ASSEMBLY__ 1061 long sun4v_con_getchar(long *status); 1062 long sun4v_con_putchar(long c); 1063 long sun4v_con_read(unsigned long buffer, 1064 unsigned long size, 1065 unsigned long *bytes_read); 1066 unsigned long sun4v_con_write(unsigned long buffer, 1067 unsigned long size, 1068 unsigned long *bytes_written); 1069 #endif 1070 1071 /* mach_set_soft_state() 1072 * TRAP: HV_FAST_TRAP 1073 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE 1074 * ARG0: software state 1075 * ARG1: software state description pointer 1076 * RET0: status 1077 * ERRORS: EINVAL software state not valid or software state 1078 * description is not NULL terminated 1079 * ENORADDR software state description pointer is not a 1080 * valid real address 1081 * EBADALIGNED software state description is not correctly 1082 * aligned 1083 * 1084 * This allows the guest to report it's soft state to the hypervisor. There 1085 * are two primary components to this state. The first part states whether 1086 * the guest software is running or not. The second containts optional 1087 * details specific to the software. 1088 * 1089 * The software state argument is defined below in HV_SOFT_STATE_*, and 1090 * indicates whether the guest is operating normally or in a transitional 1091 * state. 1092 * 1093 * The software state description argument is a real address of a data buffer 1094 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL 1095 * terminated 7-bit ASCII string of up to 31 characters not including the 1096 * NULL termination. 1097 */ 1098 #define HV_FAST_MACH_SET_SOFT_STATE 0x70 1099 #define HV_SOFT_STATE_NORMAL 0x01 1100 #define HV_SOFT_STATE_TRANSITION 0x02 1101 1102 #ifndef __ASSEMBLY__ 1103 unsigned long sun4v_mach_set_soft_state(unsigned long soft_state, 1104 unsigned long msg_string_ra); 1105 #endif 1106 1107 /* mach_get_soft_state() 1108 * TRAP: HV_FAST_TRAP 1109 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE 1110 * ARG0: software state description pointer 1111 * RET0: status 1112 * RET1: software state 1113 * ERRORS: ENORADDR software state description pointer is not a 1114 * valid real address 1115 * EBADALIGNED software state description is not correctly 1116 * aligned 1117 * 1118 * Retrieve the current value of the guest's software state. The rules 1119 * for the software state pointer are the same as for mach_set_soft_state() 1120 * above. 1121 */ 1122 #define HV_FAST_MACH_GET_SOFT_STATE 0x71 1123 1124 /* svc_send() 1125 * TRAP: HV_FAST_TRAP 1126 * FUNCTION: HV_FAST_SVC_SEND 1127 * ARG0: service ID 1128 * ARG1: buffer real address 1129 * ARG2: buffer size 1130 * RET0: STATUS 1131 * RET1: sent_bytes 1132 * 1133 * Be careful, all output registers are clobbered by this operation, 1134 * so for example it is not possible to save away a value in %o4 1135 * across the trap. 1136 */ 1137 #define HV_FAST_SVC_SEND 0x80 1138 1139 /* svc_recv() 1140 * TRAP: HV_FAST_TRAP 1141 * FUNCTION: HV_FAST_SVC_RECV 1142 * ARG0: service ID 1143 * ARG1: buffer real address 1144 * ARG2: buffer size 1145 * RET0: STATUS 1146 * RET1: recv_bytes 1147 * 1148 * Be careful, all output registers are clobbered by this operation, 1149 * so for example it is not possible to save away a value in %o4 1150 * across the trap. 1151 */ 1152 #define HV_FAST_SVC_RECV 0x81 1153 1154 /* svc_getstatus() 1155 * TRAP: HV_FAST_TRAP 1156 * FUNCTION: HV_FAST_SVC_GETSTATUS 1157 * ARG0: service ID 1158 * RET0: STATUS 1159 * RET1: status bits 1160 */ 1161 #define HV_FAST_SVC_GETSTATUS 0x82 1162 1163 /* svc_setstatus() 1164 * TRAP: HV_FAST_TRAP 1165 * FUNCTION: HV_FAST_SVC_SETSTATUS 1166 * ARG0: service ID 1167 * ARG1: bits to set 1168 * RET0: STATUS 1169 */ 1170 #define HV_FAST_SVC_SETSTATUS 0x83 1171 1172 /* svc_clrstatus() 1173 * TRAP: HV_FAST_TRAP 1174 * FUNCTION: HV_FAST_SVC_CLRSTATUS 1175 * ARG0: service ID 1176 * ARG1: bits to clear 1177 * RET0: STATUS 1178 */ 1179 #define HV_FAST_SVC_CLRSTATUS 0x84 1180 1181 #ifndef __ASSEMBLY__ 1182 unsigned long sun4v_svc_send(unsigned long svc_id, 1183 unsigned long buffer, 1184 unsigned long buffer_size, 1185 unsigned long *sent_bytes); 1186 unsigned long sun4v_svc_recv(unsigned long svc_id, 1187 unsigned long buffer, 1188 unsigned long buffer_size, 1189 unsigned long *recv_bytes); 1190 unsigned long sun4v_svc_getstatus(unsigned long svc_id, 1191 unsigned long *status_bits); 1192 unsigned long sun4v_svc_setstatus(unsigned long svc_id, 1193 unsigned long status_bits); 1194 unsigned long sun4v_svc_clrstatus(unsigned long svc_id, 1195 unsigned long status_bits); 1196 #endif 1197 1198 /* Trap trace services. 1199 * 1200 * The hypervisor provides a trap tracing capability for privileged 1201 * code running on each virtual CPU. Privileged code provides a 1202 * round-robin trap trace queue within which the hypervisor writes 1203 * 64-byte entries detailing hyperprivileged traps taken n behalf of 1204 * privileged code. This is provided as a debugging capability for 1205 * privileged code. 1206 * 1207 * The trap trace control structure is 64-bytes long and placed at the 1208 * start (offset 0) of the trap trace buffer, and is described as 1209 * follows: 1210 */ 1211 #ifndef __ASSEMBLY__ 1212 struct hv_trap_trace_control { 1213 unsigned long head_offset; 1214 unsigned long tail_offset; 1215 unsigned long __reserved[0x30 / sizeof(unsigned long)]; 1216 }; 1217 #endif 1218 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00 1219 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08 1220 1221 /* The head offset is the offset of the most recently completed entry 1222 * in the trap-trace buffer. The tail offset is the offset of the 1223 * next entry to be written. The control structure is owned and 1224 * modified by the hypervisor. A guest may not modify the control 1225 * structure contents. Attempts to do so will result in undefined 1226 * behavior for the guest. 1227 * 1228 * Each trap trace buffer entry is laid out as follows: 1229 */ 1230 #ifndef __ASSEMBLY__ 1231 struct hv_trap_trace_entry { 1232 unsigned char type; /* Hypervisor or guest entry? */ 1233 unsigned char hpstate; /* Hyper-privileged state */ 1234 unsigned char tl; /* Trap level */ 1235 unsigned char gl; /* Global register level */ 1236 unsigned short tt; /* Trap type */ 1237 unsigned short tag; /* Extended trap identifier */ 1238 unsigned long tstate; /* Trap state */ 1239 unsigned long tick; /* Tick */ 1240 unsigned long tpc; /* Trap PC */ 1241 unsigned long f1; /* Entry specific */ 1242 unsigned long f2; /* Entry specific */ 1243 unsigned long f3; /* Entry specific */ 1244 unsigned long f4; /* Entry specific */ 1245 }; 1246 #endif 1247 #define HV_TRAP_TRACE_ENTRY_TYPE 0x00 1248 #define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01 1249 #define HV_TRAP_TRACE_ENTRY_TL 0x02 1250 #define HV_TRAP_TRACE_ENTRY_GL 0x03 1251 #define HV_TRAP_TRACE_ENTRY_TT 0x04 1252 #define HV_TRAP_TRACE_ENTRY_TAG 0x06 1253 #define HV_TRAP_TRACE_ENTRY_TSTATE 0x08 1254 #define HV_TRAP_TRACE_ENTRY_TICK 0x10 1255 #define HV_TRAP_TRACE_ENTRY_TPC 0x18 1256 #define HV_TRAP_TRACE_ENTRY_F1 0x20 1257 #define HV_TRAP_TRACE_ENTRY_F2 0x28 1258 #define HV_TRAP_TRACE_ENTRY_F3 0x30 1259 #define HV_TRAP_TRACE_ENTRY_F4 0x38 1260 1261 /* The type field is encoded as follows. */ 1262 #define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */ 1263 #define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */ 1264 #define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */ 1265 1266 /* ttrace_buf_conf() 1267 * TRAP: HV_FAST_TRAP 1268 * FUNCTION: HV_FAST_TTRACE_BUF_CONF 1269 * ARG0: real address 1270 * ARG1: number of entries 1271 * RET0: status 1272 * RET1: number of entries 1273 * ERRORS: ENORADDR Invalid real address 1274 * EINVAL Size is too small 1275 * EBADALIGN Real address not aligned on 64-byte boundary 1276 * 1277 * Requests hypervisor trap tracing and declares a virtual CPU's trap 1278 * trace buffer to the hypervisor. The real address supplies the real 1279 * base address of the trap trace queue and must be 64-byte aligned. 1280 * Specifying a value of 0 for the number of entries disables trap 1281 * tracing for the calling virtual CPU. The buffer allocated must be 1282 * sized for a power of two number of 64-byte trap trace entries plus 1283 * an initial 64-byte control structure. 1284 * 1285 * This may be invoked any number of times so that a virtual CPU may 1286 * relocate a trap trace buffer or create "snapshots" of information. 1287 * 1288 * If the real address is illegal or badly aligned, then trap tracing 1289 * is disabled and an error is returned. 1290 * 1291 * Upon failure with EINVAL, this service call returns in RET1 the 1292 * minimum number of buffer entries required. Upon other failures 1293 * RET1 is undefined. 1294 */ 1295 #define HV_FAST_TTRACE_BUF_CONF 0x90 1296 1297 /* ttrace_buf_info() 1298 * TRAP: HV_FAST_TRAP 1299 * FUNCTION: HV_FAST_TTRACE_BUF_INFO 1300 * RET0: status 1301 * RET1: real address 1302 * RET2: size 1303 * ERRORS: None defined. 1304 * 1305 * Returns the size and location of the previously declared trap-trace 1306 * buffer. In the event that no buffer was previously defined, or the 1307 * buffer is disabled, this call will return a size of zero bytes. 1308 */ 1309 #define HV_FAST_TTRACE_BUF_INFO 0x91 1310 1311 /* ttrace_enable() 1312 * TRAP: HV_FAST_TRAP 1313 * FUNCTION: HV_FAST_TTRACE_ENABLE 1314 * ARG0: enable 1315 * RET0: status 1316 * RET1: previous enable state 1317 * ERRORS: EINVAL No trap trace buffer currently defined 1318 * 1319 * Enable or disable trap tracing, and return the previous enabled 1320 * state in RET1. Future systems may define various flags for the 1321 * enable argument (ARG0), for the moment a guest should pass 1322 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all 1323 * tracing - which will ensure future compatibility. 1324 */ 1325 #define HV_FAST_TTRACE_ENABLE 0x92 1326 1327 /* ttrace_freeze() 1328 * TRAP: HV_FAST_TRAP 1329 * FUNCTION: HV_FAST_TTRACE_FREEZE 1330 * ARG0: freeze 1331 * RET0: status 1332 * RET1: previous freeze state 1333 * ERRORS: EINVAL No trap trace buffer currently defined 1334 * 1335 * Freeze or unfreeze trap tracing, returning the previous freeze 1336 * state in RET1. A guest should pass a non-zero value to freeze and 1337 * a zero value to unfreeze all tracing. The returned previous state 1338 * is 0 for not frozen and 1 for frozen. 1339 */ 1340 #define HV_FAST_TTRACE_FREEZE 0x93 1341 1342 /* ttrace_addentry() 1343 * TRAP: HV_TTRACE_ADDENTRY_TRAP 1344 * ARG0: tag (16-bits) 1345 * ARG1: data word 0 1346 * ARG2: data word 1 1347 * ARG3: data word 2 1348 * ARG4: data word 3 1349 * RET0: status 1350 * ERRORS: EINVAL No trap trace buffer currently defined 1351 * 1352 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0 1353 * is modified - none of the other registers holding arguments are 1354 * volatile across this hypervisor service. 1355 */ 1356 1357 /* Core dump services. 1358 * 1359 * Since the hypervisor viraulizes and thus obscures a lot of the 1360 * physical machine layout and state, traditional OS crash dumps can 1361 * be difficult to diagnose especially when the problem is a 1362 * configuration error of some sort. 1363 * 1364 * The dump services provide an opaque buffer into which the 1365 * hypervisor can place it's internal state in order to assist in 1366 * debugging such situations. The contents are opaque and extremely 1367 * platform and hypervisor implementation specific. The guest, during 1368 * a core dump, requests that the hypervisor update any information in 1369 * the dump buffer in preparation to being dumped as part of the 1370 * domain's memory image. 1371 */ 1372 1373 /* dump_buf_update() 1374 * TRAP: HV_FAST_TRAP 1375 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE 1376 * ARG0: real address 1377 * ARG1: size 1378 * RET0: status 1379 * RET1: required size of dump buffer 1380 * ERRORS: ENORADDR Invalid real address 1381 * EBADALIGN Real address is not aligned on a 64-byte 1382 * boundary 1383 * EINVAL Size is non-zero but less than minimum size 1384 * required 1385 * ENOTSUPPORTED Operation not supported on current logical 1386 * domain 1387 * 1388 * Declare a domain dump buffer to the hypervisor. The real address 1389 * provided for the domain dump buffer must be 64-byte aligned. The 1390 * size specifies the size of the dump buffer and may be larger than 1391 * the minimum size specified in the machine description. The 1392 * hypervisor will fill the dump buffer with opaque data. 1393 * 1394 * Note: A guest may elect to include dump buffer contents as part of a crash 1395 * dump to assist with debugging. This function may be called any number 1396 * of times so that a guest may relocate a dump buffer, or create 1397 * "snapshots" of any dump-buffer information. Each call to 1398 * dump_buf_update() atomically declares the new dump buffer to the 1399 * hypervisor. 1400 * 1401 * A specified size of 0 unconfigures the dump buffer. If the real 1402 * address is illegal or badly aligned, then any currently active dump 1403 * buffer is disabled and an error is returned. 1404 * 1405 * In the event that the call fails with EINVAL, RET1 contains the 1406 * minimum size requires by the hypervisor for a valid dump buffer. 1407 */ 1408 #define HV_FAST_DUMP_BUF_UPDATE 0x94 1409 1410 /* dump_buf_info() 1411 * TRAP: HV_FAST_TRAP 1412 * FUNCTION: HV_FAST_DUMP_BUF_INFO 1413 * RET0: status 1414 * RET1: real address of current dump buffer 1415 * RET2: size of current dump buffer 1416 * ERRORS: No errors defined. 1417 * 1418 * Return the currently configures dump buffer description. A 1419 * returned size of 0 bytes indicates an undefined dump buffer. In 1420 * this case the return address in RET1 is undefined. 1421 */ 1422 #define HV_FAST_DUMP_BUF_INFO 0x95 1423 1424 /* Device interrupt services. 1425 * 1426 * Device interrupts are allocated to system bus bridges by the hypervisor, 1427 * and described to OBP in the machine description. OBP then describes 1428 * these interrupts to the OS via properties in the device tree. 1429 * 1430 * Terminology: 1431 * 1432 * cpuid Unique opaque value which represents a target cpu. 1433 * 1434 * devhandle Device handle. It uniquely identifies a device, and 1435 * consistes of the lower 28-bits of the hi-cell of the 1436 * first entry of the device's "reg" property in the 1437 * OBP device tree. 1438 * 1439 * devino Device interrupt number. Specifies the relative 1440 * interrupt number within the device. The unique 1441 * combination of devhandle and devino are used to 1442 * identify a specific device interrupt. 1443 * 1444 * Note: The devino value is the same as the values in the 1445 * "interrupts" property or "interrupt-map" property 1446 * in the OBP device tree for that device. 1447 * 1448 * sysino System interrupt number. A 64-bit unsigned interger 1449 * representing a unique interrupt within a virtual 1450 * machine. 1451 * 1452 * intr_state A flag representing the interrupt state for a given 1453 * sysino. The state values are defined below. 1454 * 1455 * intr_enabled A flag representing the 'enabled' state for a given 1456 * sysino. The enable values are defined below. 1457 */ 1458 1459 #define HV_INTR_STATE_IDLE 0 /* Nothing pending */ 1460 #define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */ 1461 #define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */ 1462 1463 #define HV_INTR_DISABLED 0 /* sysino not enabled */ 1464 #define HV_INTR_ENABLED 1 /* sysino enabled */ 1465 1466 /* intr_devino_to_sysino() 1467 * TRAP: HV_FAST_TRAP 1468 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO 1469 * ARG0: devhandle 1470 * ARG1: devino 1471 * RET0: status 1472 * RET1: sysino 1473 * ERRORS: EINVAL Invalid devhandle/devino 1474 * 1475 * Converts a device specific interrupt number of the given 1476 * devhandle/devino into a system specific ino (sysino). 1477 */ 1478 #define HV_FAST_INTR_DEVINO2SYSINO 0xa0 1479 1480 #ifndef __ASSEMBLY__ 1481 unsigned long sun4v_devino_to_sysino(unsigned long devhandle, 1482 unsigned long devino); 1483 #endif 1484 1485 /* intr_getenabled() 1486 * TRAP: HV_FAST_TRAP 1487 * FUNCTION: HV_FAST_INTR_GETENABLED 1488 * ARG0: sysino 1489 * RET0: status 1490 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED}) 1491 * ERRORS: EINVAL Invalid sysino 1492 * 1493 * Returns interrupt enabled state in RET1 for the interrupt defined 1494 * by the given sysino. 1495 */ 1496 #define HV_FAST_INTR_GETENABLED 0xa1 1497 1498 #ifndef __ASSEMBLY__ 1499 unsigned long sun4v_intr_getenabled(unsigned long sysino); 1500 #endif 1501 1502 /* intr_setenabled() 1503 * TRAP: HV_FAST_TRAP 1504 * FUNCTION: HV_FAST_INTR_SETENABLED 1505 * ARG0: sysino 1506 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED}) 1507 * RET0: status 1508 * ERRORS: EINVAL Invalid sysino or intr_enabled value 1509 * 1510 * Set the 'enabled' state of the interrupt sysino. 1511 */ 1512 #define HV_FAST_INTR_SETENABLED 0xa2 1513 1514 #ifndef __ASSEMBLY__ 1515 unsigned long sun4v_intr_setenabled(unsigned long sysino, 1516 unsigned long intr_enabled); 1517 #endif 1518 1519 /* intr_getstate() 1520 * TRAP: HV_FAST_TRAP 1521 * FUNCTION: HV_FAST_INTR_GETSTATE 1522 * ARG0: sysino 1523 * RET0: status 1524 * RET1: intr_state (HV_INTR_STATE_*) 1525 * ERRORS: EINVAL Invalid sysino 1526 * 1527 * Returns current state of the interrupt defined by the given sysino. 1528 */ 1529 #define HV_FAST_INTR_GETSTATE 0xa3 1530 1531 #ifndef __ASSEMBLY__ 1532 unsigned long sun4v_intr_getstate(unsigned long sysino); 1533 #endif 1534 1535 /* intr_setstate() 1536 * TRAP: HV_FAST_TRAP 1537 * FUNCTION: HV_FAST_INTR_SETSTATE 1538 * ARG0: sysino 1539 * ARG1: intr_state (HV_INTR_STATE_*) 1540 * RET0: status 1541 * ERRORS: EINVAL Invalid sysino or intr_state value 1542 * 1543 * Sets the current state of the interrupt described by the given sysino 1544 * value. 1545 * 1546 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending 1547 * interrupt for sysino. 1548 */ 1549 #define HV_FAST_INTR_SETSTATE 0xa4 1550 1551 #ifndef __ASSEMBLY__ 1552 unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state); 1553 #endif 1554 1555 /* intr_gettarget() 1556 * TRAP: HV_FAST_TRAP 1557 * FUNCTION: HV_FAST_INTR_GETTARGET 1558 * ARG0: sysino 1559 * RET0: status 1560 * RET1: cpuid 1561 * ERRORS: EINVAL Invalid sysino 1562 * 1563 * Returns CPU that is the current target of the interrupt defined by 1564 * the given sysino. The CPU value returned is undefined if the target 1565 * has not been set via intr_settarget(). 1566 */ 1567 #define HV_FAST_INTR_GETTARGET 0xa5 1568 1569 #ifndef __ASSEMBLY__ 1570 unsigned long sun4v_intr_gettarget(unsigned long sysino); 1571 #endif 1572 1573 /* intr_settarget() 1574 * TRAP: HV_FAST_TRAP 1575 * FUNCTION: HV_FAST_INTR_SETTARGET 1576 * ARG0: sysino 1577 * ARG1: cpuid 1578 * RET0: status 1579 * ERRORS: EINVAL Invalid sysino 1580 * ENOCPU Invalid cpuid 1581 * 1582 * Set the target CPU for the interrupt defined by the given sysino. 1583 */ 1584 #define HV_FAST_INTR_SETTARGET 0xa6 1585 1586 #ifndef __ASSEMBLY__ 1587 unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid); 1588 #endif 1589 1590 /* vintr_get_cookie() 1591 * TRAP: HV_FAST_TRAP 1592 * FUNCTION: HV_FAST_VINTR_GET_COOKIE 1593 * ARG0: device handle 1594 * ARG1: device ino 1595 * RET0: status 1596 * RET1: cookie 1597 */ 1598 #define HV_FAST_VINTR_GET_COOKIE 0xa7 1599 1600 /* vintr_set_cookie() 1601 * TRAP: HV_FAST_TRAP 1602 * FUNCTION: HV_FAST_VINTR_SET_COOKIE 1603 * ARG0: device handle 1604 * ARG1: device ino 1605 * ARG2: cookie 1606 * RET0: status 1607 */ 1608 #define HV_FAST_VINTR_SET_COOKIE 0xa8 1609 1610 /* vintr_get_valid() 1611 * TRAP: HV_FAST_TRAP 1612 * FUNCTION: HV_FAST_VINTR_GET_VALID 1613 * ARG0: device handle 1614 * ARG1: device ino 1615 * RET0: status 1616 * RET1: valid state 1617 */ 1618 #define HV_FAST_VINTR_GET_VALID 0xa9 1619 1620 /* vintr_set_valid() 1621 * TRAP: HV_FAST_TRAP 1622 * FUNCTION: HV_FAST_VINTR_SET_VALID 1623 * ARG0: device handle 1624 * ARG1: device ino 1625 * ARG2: valid state 1626 * RET0: status 1627 */ 1628 #define HV_FAST_VINTR_SET_VALID 0xaa 1629 1630 /* vintr_get_state() 1631 * TRAP: HV_FAST_TRAP 1632 * FUNCTION: HV_FAST_VINTR_GET_STATE 1633 * ARG0: device handle 1634 * ARG1: device ino 1635 * RET0: status 1636 * RET1: state 1637 */ 1638 #define HV_FAST_VINTR_GET_STATE 0xab 1639 1640 /* vintr_set_state() 1641 * TRAP: HV_FAST_TRAP 1642 * FUNCTION: HV_FAST_VINTR_SET_STATE 1643 * ARG0: device handle 1644 * ARG1: device ino 1645 * ARG2: state 1646 * RET0: status 1647 */ 1648 #define HV_FAST_VINTR_SET_STATE 0xac 1649 1650 /* vintr_get_target() 1651 * TRAP: HV_FAST_TRAP 1652 * FUNCTION: HV_FAST_VINTR_GET_TARGET 1653 * ARG0: device handle 1654 * ARG1: device ino 1655 * RET0: status 1656 * RET1: cpuid 1657 */ 1658 #define HV_FAST_VINTR_GET_TARGET 0xad 1659 1660 /* vintr_set_target() 1661 * TRAP: HV_FAST_TRAP 1662 * FUNCTION: HV_FAST_VINTR_SET_TARGET 1663 * ARG0: device handle 1664 * ARG1: device ino 1665 * ARG2: cpuid 1666 * RET0: status 1667 */ 1668 #define HV_FAST_VINTR_SET_TARGET 0xae 1669 1670 #ifndef __ASSEMBLY__ 1671 unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle, 1672 unsigned long dev_ino, 1673 unsigned long *cookie); 1674 unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle, 1675 unsigned long dev_ino, 1676 unsigned long cookie); 1677 unsigned long sun4v_vintr_get_valid(unsigned long dev_handle, 1678 unsigned long dev_ino, 1679 unsigned long *valid); 1680 unsigned long sun4v_vintr_set_valid(unsigned long dev_handle, 1681 unsigned long dev_ino, 1682 unsigned long valid); 1683 unsigned long sun4v_vintr_get_state(unsigned long dev_handle, 1684 unsigned long dev_ino, 1685 unsigned long *state); 1686 unsigned long sun4v_vintr_set_state(unsigned long dev_handle, 1687 unsigned long dev_ino, 1688 unsigned long state); 1689 unsigned long sun4v_vintr_get_target(unsigned long dev_handle, 1690 unsigned long dev_ino, 1691 unsigned long *cpuid); 1692 unsigned long sun4v_vintr_set_target(unsigned long dev_handle, 1693 unsigned long dev_ino, 1694 unsigned long cpuid); 1695 #endif 1696 1697 /* PCI IO services. 1698 * 1699 * See the terminology descriptions in the device interrupt services 1700 * section above as those apply here too. Here are terminology 1701 * definitions specific to these PCI IO services: 1702 * 1703 * tsbnum TSB number. Indentifies which io-tsb is used. 1704 * For this version of the specification, tsbnum 1705 * must be zero. 1706 * 1707 * tsbindex TSB index. Identifies which entry in the TSB 1708 * is used. The first entry is zero. 1709 * 1710 * tsbid A 64-bit aligned data structure which contains 1711 * a tsbnum and a tsbindex. Bits 63:32 contain the 1712 * tsbnum and bits 31:00 contain the tsbindex. 1713 * 1714 * Use the HV_PCI_TSBID() macro to construct such 1715 * values. 1716 * 1717 * io_attributes IO attributes for IOMMU mappings. One of more 1718 * of the attritbute bits are stores in a 64-bit 1719 * value. The values are defined below. 1720 * 1721 * r_addr 64-bit real address 1722 * 1723 * pci_device PCI device address. A PCI device address identifies 1724 * a specific device on a specific PCI bus segment. 1725 * A PCI device address ia a 32-bit unsigned integer 1726 * with the following format: 1727 * 1728 * 00000000.bbbbbbbb.dddddfff.00000000 1729 * 1730 * Use the HV_PCI_DEVICE_BUILD() macro to construct 1731 * such values. 1732 * 1733 * pci_config_offset 1734 * PCI configureation space offset. For conventional 1735 * PCI a value between 0 and 255. For extended 1736 * configuration space, a value between 0 and 4095. 1737 * 1738 * Note: For PCI configuration space accesses, the offset 1739 * must be aligned to the access size. 1740 * 1741 * error_flag A return value which specifies if the action succeeded 1742 * or failed. 0 means no error, non-0 means some error 1743 * occurred while performing the service. 1744 * 1745 * io_sync_direction 1746 * Direction definition for pci_dma_sync(), defined 1747 * below in HV_PCI_SYNC_*. 1748 * 1749 * io_page_list A list of io_page_addresses, an io_page_address is 1750 * a real address. 1751 * 1752 * io_page_list_p A pointer to an io_page_list. 1753 * 1754 * "size based byte swap" - Some functions do size based byte swapping 1755 * which allows sw to access pointers and 1756 * counters in native form when the processor 1757 * operates in a different endianness than the 1758 * IO bus. Size-based byte swapping converts a 1759 * multi-byte field between big-endian and 1760 * little-endian format. 1761 */ 1762 1763 #define HV_PCI_MAP_ATTR_READ 0x01 1764 #define HV_PCI_MAP_ATTR_WRITE 0x02 1765 #define HV_PCI_MAP_ATTR_RELAXED_ORDER 0x04 1766 1767 #define HV_PCI_DEVICE_BUILD(b,d,f) \ 1768 ((((b) & 0xff) << 16) | \ 1769 (((d) & 0x1f) << 11) | \ 1770 (((f) & 0x07) << 8)) 1771 1772 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \ 1773 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index))) 1774 1775 #define HV_PCI_SYNC_FOR_DEVICE 0x01 1776 #define HV_PCI_SYNC_FOR_CPU 0x02 1777 1778 /* pci_iommu_map() 1779 * TRAP: HV_FAST_TRAP 1780 * FUNCTION: HV_FAST_PCI_IOMMU_MAP 1781 * ARG0: devhandle 1782 * ARG1: tsbid 1783 * ARG2: #ttes 1784 * ARG3: io_attributes 1785 * ARG4: io_page_list_p 1786 * RET0: status 1787 * RET1: #ttes mapped 1788 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes 1789 * EBADALIGN Improperly aligned real address 1790 * ENORADDR Invalid real address 1791 * 1792 * Create IOMMU mappings in the sun4v device defined by the given 1793 * devhandle. The mappings are created in the TSB defined by the 1794 * tsbnum component of the given tsbid. The first mapping is created 1795 * in the TSB i ndex defined by the tsbindex component of the given tsbid. 1796 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex, 1797 * the second at tsbnum, tsbindex + 1, etc. 1798 * 1799 * All mappings are created with the attributes defined by the io_attributes 1800 * argument. The page mapping addresses are described in the io_page_list 1801 * defined by the given io_page_list_p, which is a pointer to the io_page_list. 1802 * The first entry in the io_page_list is the address for the first iotte, the 1803 * 2nd for the 2nd iotte, and so on. 1804 * 1805 * Each io_page_address in the io_page_list must be appropriately aligned. 1806 * #ttes must be greater than zero. For this version of the spec, the tsbnum 1807 * component of the given tsbid must be zero. 1808 * 1809 * Returns the actual number of mappings creates, which may be less than 1810 * or equal to the argument #ttes. If the function returns a value which 1811 * is less than the #ttes, the caller may continus to call the function with 1812 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are 1813 * mapped. 1814 * 1815 * Note: This function does not imply an iotte cache flush. The guest must 1816 * demap an entry before re-mapping it. 1817 */ 1818 #define HV_FAST_PCI_IOMMU_MAP 0xb0 1819 1820 /* pci_iommu_demap() 1821 * TRAP: HV_FAST_TRAP 1822 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP 1823 * ARG0: devhandle 1824 * ARG1: tsbid 1825 * ARG2: #ttes 1826 * RET0: status 1827 * RET1: #ttes demapped 1828 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex 1829 * 1830 * Demap and flush IOMMU mappings in the device defined by the given 1831 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum 1832 * component of the given tsbid, starting at the TSB index defined by the 1833 * tsbindex component of the given tsbid. 1834 * 1835 * For this version of the spec, the tsbnum of the given tsbid must be zero. 1836 * #ttes must be greater than zero. 1837 * 1838 * Returns the actual number of ttes demapped, which may be less than or equal 1839 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller 1840 * may continue to call this function with updated tsbid and #ttes arguments 1841 * until all pages are demapped. 1842 * 1843 * Note: Entries do not have to be mapped to be demapped. A demap of an 1844 * unmapped page will flush the entry from the tte cache. 1845 */ 1846 #define HV_FAST_PCI_IOMMU_DEMAP 0xb1 1847 1848 /* pci_iommu_getmap() 1849 * TRAP: HV_FAST_TRAP 1850 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP 1851 * ARG0: devhandle 1852 * ARG1: tsbid 1853 * RET0: status 1854 * RET1: io_attributes 1855 * RET2: real address 1856 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex 1857 * ENOMAP Mapping is not valid, no translation exists 1858 * 1859 * Read and return the mapping in the device described by the given devhandle 1860 * and tsbid. If successful, the io_attributes shall be returned in RET1 1861 * and the page address of the mapping shall be returned in RET2. 1862 * 1863 * For this version of the spec, the tsbnum component of the given tsbid 1864 * must be zero. 1865 */ 1866 #define HV_FAST_PCI_IOMMU_GETMAP 0xb2 1867 1868 /* pci_iommu_getbypass() 1869 * TRAP: HV_FAST_TRAP 1870 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS 1871 * ARG0: devhandle 1872 * ARG1: real address 1873 * ARG2: io_attributes 1874 * RET0: status 1875 * RET1: io_addr 1876 * ERRORS: EINVAL Invalid devhandle/io_attributes 1877 * ENORADDR Invalid real address 1878 * ENOTSUPPORTED Function not supported in this implementation. 1879 * 1880 * Create a "special" mapping in the device described by the given devhandle, 1881 * for the given real address and attributes. Return the IO address in RET1 1882 * if successful. 1883 */ 1884 #define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3 1885 1886 /* pci_config_get() 1887 * TRAP: HV_FAST_TRAP 1888 * FUNCTION: HV_FAST_PCI_CONFIG_GET 1889 * ARG0: devhandle 1890 * ARG1: pci_device 1891 * ARG2: pci_config_offset 1892 * ARG3: size 1893 * RET0: status 1894 * RET1: error_flag 1895 * RET2: data 1896 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size 1897 * EBADALIGN pci_config_offset not size aligned 1898 * ENOACCESS Access to this offset is not permitted 1899 * 1900 * Read PCI configuration space for the adapter described by the given 1901 * devhandle. Read size (1, 2, or 4) bytes of data from the given 1902 * pci_device, at pci_config_offset from the beginning of the device's 1903 * configuration space. If there was no error, RET1 is set to zero and 1904 * RET2 is set to the data read. Insignificant bits in RET2 are not 1905 * guaranteed to have any specific value and therefore must be ignored. 1906 * 1907 * The data returned in RET2 is size based byte swapped. 1908 * 1909 * If an error occurs during the read, set RET1 to a non-zero value. The 1910 * given pci_config_offset must be 'size' aligned. 1911 */ 1912 #define HV_FAST_PCI_CONFIG_GET 0xb4 1913 1914 /* pci_config_put() 1915 * TRAP: HV_FAST_TRAP 1916 * FUNCTION: HV_FAST_PCI_CONFIG_PUT 1917 * ARG0: devhandle 1918 * ARG1: pci_device 1919 * ARG2: pci_config_offset 1920 * ARG3: size 1921 * ARG4: data 1922 * RET0: status 1923 * RET1: error_flag 1924 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size 1925 * EBADALIGN pci_config_offset not size aligned 1926 * ENOACCESS Access to this offset is not permitted 1927 * 1928 * Write PCI configuration space for the adapter described by the given 1929 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation, 1930 * at pci_config_offset from the beginning of the device's configuration 1931 * space. The data argument contains the data to be written to configuration 1932 * space. Prior to writing, the data is size based byte swapped. 1933 * 1934 * If an error occurs during the write access, do not generate an error 1935 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero. 1936 * The given pci_config_offset must be 'size' aligned. 1937 * 1938 * This function is permitted to read from offset zero in the configuration 1939 * space described by the given pci_device if necessary to ensure that the 1940 * write access to config space completes. 1941 */ 1942 #define HV_FAST_PCI_CONFIG_PUT 0xb5 1943 1944 /* pci_peek() 1945 * TRAP: HV_FAST_TRAP 1946 * FUNCTION: HV_FAST_PCI_PEEK 1947 * ARG0: devhandle 1948 * ARG1: real address 1949 * ARG2: size 1950 * RET0: status 1951 * RET1: error_flag 1952 * RET2: data 1953 * ERRORS: EINVAL Invalid devhandle or size 1954 * EBADALIGN Improperly aligned real address 1955 * ENORADDR Bad real address 1956 * ENOACCESS Guest access prohibited 1957 * 1958 * Attempt to read the IO address given by the given devhandle, real address, 1959 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single 1960 * access operation using the given size. If an error occurs when reading 1961 * from the given location, do not generate an error report, but return a 1962 * non-zero value in RET1. If the read was successful, return zero in RET1 1963 * and return the actual data read in RET2. The data returned is size based 1964 * byte swapped. 1965 * 1966 * Non-significant bits in RET2 are not guaranteed to have any specific value 1967 * and therefore must be ignored. If RET1 is returned as non-zero, the data 1968 * value is not guaranteed to have any specific value and should be ignored. 1969 * 1970 * The caller must have permission to read from the given devhandle, real 1971 * address, which must be an IO address. The argument real address must be a 1972 * size aligned address. 1973 * 1974 * The hypervisor implementation of this function must block access to any 1975 * IO address that the guest does not have explicit permission to access. 1976 */ 1977 #define HV_FAST_PCI_PEEK 0xb6 1978 1979 /* pci_poke() 1980 * TRAP: HV_FAST_TRAP 1981 * FUNCTION: HV_FAST_PCI_POKE 1982 * ARG0: devhandle 1983 * ARG1: real address 1984 * ARG2: size 1985 * ARG3: data 1986 * ARG4: pci_device 1987 * RET0: status 1988 * RET1: error_flag 1989 * ERRORS: EINVAL Invalid devhandle, size, or pci_device 1990 * EBADALIGN Improperly aligned real address 1991 * ENORADDR Bad real address 1992 * ENOACCESS Guest access prohibited 1993 * ENOTSUPPORTED Function is not supported by implementation 1994 * 1995 * Attempt to write data to the IO address given by the given devhandle, 1996 * real address, and size. Size must be 1, 2, 4, or 8. The write is 1997 * performed as a single access operation using the given size. Prior to 1998 * writing the data is size based swapped. 1999 * 2000 * If an error occurs when writing to the given location, do not generate an 2001 * error report, but return a non-zero value in RET1. If the write was 2002 * successful, return zero in RET1. 2003 * 2004 * pci_device describes the configuration address of the device being 2005 * written to. The implementation may safely read from offset 0 with 2006 * the configuration space of the device described by devhandle and 2007 * pci_device in order to guarantee that the write portion of the operation 2008 * completes 2009 * 2010 * Any error that occurs due to the read shall be reported using the normal 2011 * error reporting mechanisms .. the read error is not suppressed. 2012 * 2013 * The caller must have permission to write to the given devhandle, real 2014 * address, which must be an IO address. The argument real address must be a 2015 * size aligned address. The caller must have permission to read from 2016 * the given devhandle, pci_device cofiguration space offset 0. 2017 * 2018 * The hypervisor implementation of this function must block access to any 2019 * IO address that the guest does not have explicit permission to access. 2020 */ 2021 #define HV_FAST_PCI_POKE 0xb7 2022 2023 /* pci_dma_sync() 2024 * TRAP: HV_FAST_TRAP 2025 * FUNCTION: HV_FAST_PCI_DMA_SYNC 2026 * ARG0: devhandle 2027 * ARG1: real address 2028 * ARG2: size 2029 * ARG3: io_sync_direction 2030 * RET0: status 2031 * RET1: #synced 2032 * ERRORS: EINVAL Invalid devhandle or io_sync_direction 2033 * ENORADDR Bad real address 2034 * 2035 * Synchronize a memory region described by the given real address and size, 2036 * for the device defined by the given devhandle using the direction(s) 2037 * defined by the given io_sync_direction. The argument size is the size of 2038 * the memory region in bytes. 2039 * 2040 * Return the actual number of bytes synchronized in the return value #synced, 2041 * which may be less than or equal to the argument size. If the return 2042 * value #synced is less than size, the caller must continue to call this 2043 * function with updated real address and size arguments until the entire 2044 * memory region is synchronized. 2045 */ 2046 #define HV_FAST_PCI_DMA_SYNC 0xb8 2047 2048 /* PCI MSI services. */ 2049 2050 #define HV_MSITYPE_MSI32 0x00 2051 #define HV_MSITYPE_MSI64 0x01 2052 2053 #define HV_MSIQSTATE_IDLE 0x00 2054 #define HV_MSIQSTATE_ERROR 0x01 2055 2056 #define HV_MSIQ_INVALID 0x00 2057 #define HV_MSIQ_VALID 0x01 2058 2059 #define HV_MSISTATE_IDLE 0x00 2060 #define HV_MSISTATE_DELIVERED 0x01 2061 2062 #define HV_MSIVALID_INVALID 0x00 2063 #define HV_MSIVALID_VALID 0x01 2064 2065 #define HV_PCIE_MSGTYPE_PME_MSG 0x18 2066 #define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b 2067 #define HV_PCIE_MSGTYPE_CORR_MSG 0x30 2068 #define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31 2069 #define HV_PCIE_MSGTYPE_FATAL_MSG 0x33 2070 2071 #define HV_MSG_INVALID 0x00 2072 #define HV_MSG_VALID 0x01 2073 2074 /* pci_msiq_conf() 2075 * TRAP: HV_FAST_TRAP 2076 * FUNCTION: HV_FAST_PCI_MSIQ_CONF 2077 * ARG0: devhandle 2078 * ARG1: msiqid 2079 * ARG2: real address 2080 * ARG3: number of entries 2081 * RET0: status 2082 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries 2083 * EBADALIGN Improperly aligned real address 2084 * ENORADDR Bad real address 2085 * 2086 * Configure the MSI queue given by the devhandle and msiqid arguments, 2087 * and to be placed at the given real address and be of the given 2088 * number of entries. The real address must be aligned exactly to match 2089 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry 2090 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ 2091 * Head and Tail are initialized so that the MSI-EQ is 'empty'. 2092 * 2093 * Implementation Note: Certain implementations have fixed sized queues. In 2094 * that case, number of entries must contain the correct 2095 * value. 2096 */ 2097 #define HV_FAST_PCI_MSIQ_CONF 0xc0 2098 2099 /* pci_msiq_info() 2100 * TRAP: HV_FAST_TRAP 2101 * FUNCTION: HV_FAST_PCI_MSIQ_INFO 2102 * ARG0: devhandle 2103 * ARG1: msiqid 2104 * RET0: status 2105 * RET1: real address 2106 * RET2: number of entries 2107 * ERRORS: EINVAL Invalid devhandle or msiqid 2108 * 2109 * Return the configuration information for the MSI queue described 2110 * by the given devhandle and msiqid. The base address of the queue 2111 * is returned in ARG1 and the number of entries is returned in ARG2. 2112 * If the queue is unconfigured, the real address is undefined and the 2113 * number of entries will be returned as zero. 2114 */ 2115 #define HV_FAST_PCI_MSIQ_INFO 0xc1 2116 2117 /* pci_msiq_getvalid() 2118 * TRAP: HV_FAST_TRAP 2119 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID 2120 * ARG0: devhandle 2121 * ARG1: msiqid 2122 * RET0: status 2123 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID) 2124 * ERRORS: EINVAL Invalid devhandle or msiqid 2125 * 2126 * Get the valid state of the MSI-EQ described by the given devhandle and 2127 * msiqid. 2128 */ 2129 #define HV_FAST_PCI_MSIQ_GETVALID 0xc2 2130 2131 /* pci_msiq_setvalid() 2132 * TRAP: HV_FAST_TRAP 2133 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID 2134 * ARG0: devhandle 2135 * ARG1: msiqid 2136 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID) 2137 * RET0: status 2138 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid 2139 * value or MSI EQ is uninitialized 2140 * 2141 * Set the valid state of the MSI-EQ described by the given devhandle and 2142 * msiqid to the given msiqvalid. 2143 */ 2144 #define HV_FAST_PCI_MSIQ_SETVALID 0xc3 2145 2146 /* pci_msiq_getstate() 2147 * TRAP: HV_FAST_TRAP 2148 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE 2149 * ARG0: devhandle 2150 * ARG1: msiqid 2151 * RET0: status 2152 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR) 2153 * ERRORS: EINVAL Invalid devhandle or msiqid 2154 * 2155 * Get the state of the MSI-EQ described by the given devhandle and 2156 * msiqid. 2157 */ 2158 #define HV_FAST_PCI_MSIQ_GETSTATE 0xc4 2159 2160 /* pci_msiq_getvalid() 2161 * TRAP: HV_FAST_TRAP 2162 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID 2163 * ARG0: devhandle 2164 * ARG1: msiqid 2165 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR) 2166 * RET0: status 2167 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate 2168 * value or MSI EQ is uninitialized 2169 * 2170 * Set the state of the MSI-EQ described by the given devhandle and 2171 * msiqid to the given msiqvalid. 2172 */ 2173 #define HV_FAST_PCI_MSIQ_SETSTATE 0xc5 2174 2175 /* pci_msiq_gethead() 2176 * TRAP: HV_FAST_TRAP 2177 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD 2178 * ARG0: devhandle 2179 * ARG1: msiqid 2180 * RET0: status 2181 * RET1: msiqhead 2182 * ERRORS: EINVAL Invalid devhandle or msiqid 2183 * 2184 * Get the current MSI EQ queue head for the MSI-EQ described by the 2185 * given devhandle and msiqid. 2186 */ 2187 #define HV_FAST_PCI_MSIQ_GETHEAD 0xc6 2188 2189 /* pci_msiq_sethead() 2190 * TRAP: HV_FAST_TRAP 2191 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD 2192 * ARG0: devhandle 2193 * ARG1: msiqid 2194 * ARG2: msiqhead 2195 * RET0: status 2196 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead, 2197 * or MSI EQ is uninitialized 2198 * 2199 * Set the current MSI EQ queue head for the MSI-EQ described by the 2200 * given devhandle and msiqid. 2201 */ 2202 #define HV_FAST_PCI_MSIQ_SETHEAD 0xc7 2203 2204 /* pci_msiq_gettail() 2205 * TRAP: HV_FAST_TRAP 2206 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL 2207 * ARG0: devhandle 2208 * ARG1: msiqid 2209 * RET0: status 2210 * RET1: msiqtail 2211 * ERRORS: EINVAL Invalid devhandle or msiqid 2212 * 2213 * Get the current MSI EQ queue tail for the MSI-EQ described by the 2214 * given devhandle and msiqid. 2215 */ 2216 #define HV_FAST_PCI_MSIQ_GETTAIL 0xc8 2217 2218 /* pci_msi_getvalid() 2219 * TRAP: HV_FAST_TRAP 2220 * FUNCTION: HV_FAST_PCI_MSI_GETVALID 2221 * ARG0: devhandle 2222 * ARG1: msinum 2223 * RET0: status 2224 * RET1: msivalidstate 2225 * ERRORS: EINVAL Invalid devhandle or msinum 2226 * 2227 * Get the current valid/enabled state for the MSI defined by the 2228 * given devhandle and msinum. 2229 */ 2230 #define HV_FAST_PCI_MSI_GETVALID 0xc9 2231 2232 /* pci_msi_setvalid() 2233 * TRAP: HV_FAST_TRAP 2234 * FUNCTION: HV_FAST_PCI_MSI_SETVALID 2235 * ARG0: devhandle 2236 * ARG1: msinum 2237 * ARG2: msivalidstate 2238 * RET0: status 2239 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate 2240 * 2241 * Set the current valid/enabled state for the MSI defined by the 2242 * given devhandle and msinum. 2243 */ 2244 #define HV_FAST_PCI_MSI_SETVALID 0xca 2245 2246 /* pci_msi_getmsiq() 2247 * TRAP: HV_FAST_TRAP 2248 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ 2249 * ARG0: devhandle 2250 * ARG1: msinum 2251 * RET0: status 2252 * RET1: msiqid 2253 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound 2254 * 2255 * Get the MSI EQ that the MSI defined by the given devhandle and 2256 * msinum is bound to. 2257 */ 2258 #define HV_FAST_PCI_MSI_GETMSIQ 0xcb 2259 2260 /* pci_msi_setmsiq() 2261 * TRAP: HV_FAST_TRAP 2262 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ 2263 * ARG0: devhandle 2264 * ARG1: msinum 2265 * ARG2: msitype 2266 * ARG3: msiqid 2267 * RET0: status 2268 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid 2269 * 2270 * Set the MSI EQ that the MSI defined by the given devhandle and 2271 * msinum is bound to. 2272 */ 2273 #define HV_FAST_PCI_MSI_SETMSIQ 0xcc 2274 2275 /* pci_msi_getstate() 2276 * TRAP: HV_FAST_TRAP 2277 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE 2278 * ARG0: devhandle 2279 * ARG1: msinum 2280 * RET0: status 2281 * RET1: msistate 2282 * ERRORS: EINVAL Invalid devhandle or msinum 2283 * 2284 * Get the state of the MSI defined by the given devhandle and msinum. 2285 * If not initialized, return HV_MSISTATE_IDLE. 2286 */ 2287 #define HV_FAST_PCI_MSI_GETSTATE 0xcd 2288 2289 /* pci_msi_setstate() 2290 * TRAP: HV_FAST_TRAP 2291 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE 2292 * ARG0: devhandle 2293 * ARG1: msinum 2294 * ARG2: msistate 2295 * RET0: status 2296 * ERRORS: EINVAL Invalid devhandle or msinum or msistate 2297 * 2298 * Set the state of the MSI defined by the given devhandle and msinum. 2299 */ 2300 #define HV_FAST_PCI_MSI_SETSTATE 0xce 2301 2302 /* pci_msg_getmsiq() 2303 * TRAP: HV_FAST_TRAP 2304 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ 2305 * ARG0: devhandle 2306 * ARG1: msgtype 2307 * RET0: status 2308 * RET1: msiqid 2309 * ERRORS: EINVAL Invalid devhandle or msgtype 2310 * 2311 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype. 2312 */ 2313 #define HV_FAST_PCI_MSG_GETMSIQ 0xd0 2314 2315 /* pci_msg_setmsiq() 2316 * TRAP: HV_FAST_TRAP 2317 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ 2318 * ARG0: devhandle 2319 * ARG1: msgtype 2320 * ARG2: msiqid 2321 * RET0: status 2322 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid 2323 * 2324 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype. 2325 */ 2326 #define HV_FAST_PCI_MSG_SETMSIQ 0xd1 2327 2328 /* pci_msg_getvalid() 2329 * TRAP: HV_FAST_TRAP 2330 * FUNCTION: HV_FAST_PCI_MSG_GETVALID 2331 * ARG0: devhandle 2332 * ARG1: msgtype 2333 * RET0: status 2334 * RET1: msgvalidstate 2335 * ERRORS: EINVAL Invalid devhandle or msgtype 2336 * 2337 * Get the valid/enabled state of the MSG defined by the given 2338 * devhandle and msgtype. 2339 */ 2340 #define HV_FAST_PCI_MSG_GETVALID 0xd2 2341 2342 /* pci_msg_setvalid() 2343 * TRAP: HV_FAST_TRAP 2344 * FUNCTION: HV_FAST_PCI_MSG_SETVALID 2345 * ARG0: devhandle 2346 * ARG1: msgtype 2347 * ARG2: msgvalidstate 2348 * RET0: status 2349 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate 2350 * 2351 * Set the valid/enabled state of the MSG defined by the given 2352 * devhandle and msgtype. 2353 */ 2354 #define HV_FAST_PCI_MSG_SETVALID 0xd3 2355 2356 /* PCI IOMMU v2 definitions and services 2357 * 2358 * While the PCI IO definitions above is valid IOMMU v2 adds new PCI IO 2359 * definitions and services. 2360 * 2361 * CTE Clump Table Entry. First level table entry in the ATU. 2362 * 2363 * pci_device_list 2364 * A 32-bit aligned list of pci_devices. 2365 * 2366 * pci_device_listp 2367 * real address of a pci_device_list. 32-bit aligned. 2368 * 2369 * iotte IOMMU translation table entry. 2370 * 2371 * iotte_attributes 2372 * IO Attributes for IOMMU v2 mappings. In addition to 2373 * read, write IOMMU v2 supports relax ordering 2374 * 2375 * io_page_list A 64-bit aligned list of real addresses. Each real 2376 * address in an io_page_list must be properly aligned 2377 * to the pagesize of the given IOTSB. 2378 * 2379 * io_page_list_p Real address of an io_page_list, 64-bit aligned. 2380 * 2381 * IOTSB IO Translation Storage Buffer. An aligned table of 2382 * IOTTEs. Each IOTSB has a pagesize, table size, and 2383 * virtual address associated with it that must match 2384 * a pagesize and table size supported by the un-derlying 2385 * hardware implementation. The alignment requirements 2386 * for an IOTSB depend on the pagesize used for that IOTSB. 2387 * Each IOTTE in an IOTSB maps one pagesize-sized page. 2388 * The size of the IOTSB dictates how large of a virtual 2389 * address space the IOTSB is capable of mapping. 2390 * 2391 * iotsb_handle An opaque identifier for an IOTSB. A devhandle plus 2392 * iotsb_handle represents a binding of an IOTSB to a 2393 * PCI root complex. 2394 * 2395 * iotsb_index Zero-based IOTTE number within an IOTSB. 2396 */ 2397 2398 /* The index_count argument consists of two fields: 2399 * bits 63:48 #iottes and bits 47:0 iotsb_index 2400 */ 2401 #define HV_PCI_IOTSB_INDEX_COUNT(__iottes, __iotsb_index) \ 2402 (((u64)(__iottes) << 48UL) | ((u64)(__iotsb_index))) 2403 2404 /* pci_iotsb_conf() 2405 * TRAP: HV_FAST_TRAP 2406 * FUNCTION: HV_FAST_PCI_IOTSB_CONF 2407 * ARG0: devhandle 2408 * ARG1: r_addr 2409 * ARG2: size 2410 * ARG3: pagesize 2411 * ARG4: iova 2412 * RET0: status 2413 * RET1: iotsb_handle 2414 * ERRORS: EINVAL Invalid devhandle, size, iova, or pagesize 2415 * EBADALIGN r_addr is not properly aligned 2416 * ENORADDR r_addr is not a valid real address 2417 * ETOOMANY No further IOTSBs may be configured 2418 * EBUSY Duplicate devhandle, raddir, iova combination 2419 * 2420 * Create an IOTSB suitable for the PCI root complex identified by devhandle, 2421 * for the DMA virtual address defined by the argument iova. 2422 * 2423 * r_addr is the properly aligned base address of the IOTSB and size is the 2424 * IOTSB (table) size in bytes.The IOTSB is required to be zeroed prior to 2425 * being configured. If it contains any values other than zeros then the 2426 * behavior is undefined. 2427 * 2428 * pagesize is the size of each page in the IOTSB. Note that the combination of 2429 * size (table size) and pagesize must be valid. 2430 * 2431 * virt is the DMA virtual address this IOTSB will map. 2432 * 2433 * If successful, the opaque 64-bit handle iotsb_handle is returned in ret1. 2434 * Once configured, privileged access to the IOTSB memory is prohibited and 2435 * creates undefined behavior. The only permitted access is indirect via these 2436 * services. 2437 */ 2438 #define HV_FAST_PCI_IOTSB_CONF 0x190 2439 2440 /* pci_iotsb_info() 2441 * TRAP: HV_FAST_TRAP 2442 * FUNCTION: HV_FAST_PCI_IOTSB_INFO 2443 * ARG0: devhandle 2444 * ARG1: iotsb_handle 2445 * RET0: status 2446 * RET1: r_addr 2447 * RET2: size 2448 * RET3: pagesize 2449 * RET4: iova 2450 * RET5: #bound 2451 * ERRORS: EINVAL Invalid devhandle or iotsb_handle 2452 * 2453 * This service returns configuration information about an IOTSB previously 2454 * created with pci_iotsb_conf. 2455 * 2456 * iotsb_handle value 0 may be used with this service to inquire about the 2457 * legacy IOTSB that may or may not exist. If the service succeeds, the return 2458 * values describe the legacy IOTSB and I/O virtual addresses mapped by that 2459 * table. However, the table base address r_addr may contain the value -1 which 2460 * indicates a memory range that cannot be accessed or be reclaimed. 2461 * 2462 * The return value #bound contains the number of PCI devices that iotsb_handle 2463 * is currently bound to. 2464 */ 2465 #define HV_FAST_PCI_IOTSB_INFO 0x191 2466 2467 /* pci_iotsb_unconf() 2468 * TRAP: HV_FAST_TRAP 2469 * FUNCTION: HV_FAST_PCI_IOTSB_UNCONF 2470 * ARG0: devhandle 2471 * ARG1: iotsb_handle 2472 * RET0: status 2473 * ERRORS: EINVAL Invalid devhandle or iotsb_handle 2474 * EBUSY The IOTSB is bound and may not be unconfigured 2475 * 2476 * This service unconfigures the IOTSB identified by the devhandle and 2477 * iotsb_handle arguments, previously created with pci_iotsb_conf. 2478 * The IOTSB must not be currently bound to any device or the service will fail 2479 * 2480 * If the call succeeds, iotsb_handle is no longer valid. 2481 */ 2482 #define HV_FAST_PCI_IOTSB_UNCONF 0x192 2483 2484 /* pci_iotsb_bind() 2485 * TRAP: HV_FAST_TRAP 2486 * FUNCTION: HV_FAST_PCI_IOTSB_BIND 2487 * ARG0: devhandle 2488 * ARG1: iotsb_handle 2489 * ARG2: pci_device 2490 * RET0: status 2491 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or pci_device 2492 * EBUSY A PCI function is already bound to an IOTSB at the same 2493 * address range as specified by devhandle, iotsb_handle. 2494 * 2495 * This service binds the PCI function specified by the argument pci_device to 2496 * the IOTSB specified by the arguments devhandle and iotsb_handle. 2497 * 2498 * The PCI device function is bound to the specified IOTSB with the IOVA range 2499 * specified when the IOTSB was configured via pci_iotsb_conf. If the function 2500 * is already bound then it is unbound first. 2501 */ 2502 #define HV_FAST_PCI_IOTSB_BIND 0x193 2503 2504 /* pci_iotsb_unbind() 2505 * TRAP: HV_FAST_TRAP 2506 * FUNCTION: HV_FAST_PCI_IOTSB_UNBIND 2507 * ARG0: devhandle 2508 * ARG1: iotsb_handle 2509 * ARG2: pci_device 2510 * RET0: status 2511 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or pci_device 2512 * ENOMAP The PCI function was not bound to the specified IOTSB 2513 * 2514 * This service unbinds the PCI device specified by the argument pci_device 2515 * from the IOTSB identified * by the arguments devhandle and iotsb_handle. 2516 * 2517 * If the PCI device is not bound to the specified IOTSB then this service will 2518 * fail with status ENOMAP 2519 */ 2520 #define HV_FAST_PCI_IOTSB_UNBIND 0x194 2521 2522 /* pci_iotsb_get_binding() 2523 * TRAP: HV_FAST_TRAP 2524 * FUNCTION: HV_FAST_PCI_IOTSB_GET_BINDING 2525 * ARG0: devhandle 2526 * ARG1: iotsb_handle 2527 * ARG2: iova 2528 * RET0: status 2529 * RET1: iotsb_handle 2530 * ERRORS: EINVAL Invalid devhandle, pci_device, or iova 2531 * ENOMAP The PCI function is not bound to an IOTSB at iova 2532 * 2533 * This service returns the IOTSB binding, iotsb_handle, for a given pci_device 2534 * and DMA virtual address, iova. 2535 * 2536 * iova must be the base address of a DMA virtual address range as defined by 2537 * the iommu-address-ranges property in the root complex device node defined 2538 * by the argument devhandle. 2539 */ 2540 #define HV_FAST_PCI_IOTSB_GET_BINDING 0x195 2541 2542 /* pci_iotsb_map() 2543 * TRAP: HV_FAST_TRAP 2544 * FUNCTION: HV_FAST_PCI_IOTSB_MAP 2545 * ARG0: devhandle 2546 * ARG1: iotsb_handle 2547 * ARG2: index_count 2548 * ARG3: iotte_attributes 2549 * ARG4: io_page_list_p 2550 * RET0: status 2551 * RET1: #mapped 2552 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, #iottes, 2553 * iotsb_index or iotte_attributes 2554 * EBADALIGN Improperly aligned io_page_list_p or I/O page 2555 * address in the I/O page list. 2556 * ENORADDR Invalid io_page_list_p or I/O page address in 2557 * the I/O page list. 2558 * 2559 * This service creates and flushes mappings in the IOTSB defined by the 2560 * arguments devhandle, iotsb. 2561 * 2562 * The index_count argument consists of two fields. Bits 63:48 contain #iotte 2563 * and bits 47:0 contain iotsb_index 2564 * 2565 * The first mapping is created in the IOTSB index specified by iotsb_index. 2566 * Subsequent mappings are created at iotsb_index+1 and so on. 2567 * 2568 * The attributes of each mapping are defined by the argument iotte_attributes. 2569 * 2570 * The io_page_list_p specifies the real address of the 64-bit-aligned list of 2571 * #iottes I/O page addresses. Each page address must be a properly aligned 2572 * real address of a page to be mapped in the IOTSB. The first entry in the I/O 2573 * page list contains the real address of the first page, the 2nd entry for the 2574 * 2nd page, and so on. 2575 * 2576 * #iottes must be greater than zero. 2577 * 2578 * The return value #mapped is the actual number of mappings created, which may 2579 * be less than or equal to the argument #iottes. If the function returns 2580 * successfully with a #mapped value less than the requested #iottes then the 2581 * caller should continue to invoke the service with updated iotsb_index, 2582 * #iottes, and io_page_list_p arguments until all pages are mapped. 2583 * 2584 * This service must not be used to demap a mapping. In other words, all 2585 * mappings must be valid and have one or both of the RW attribute bits set. 2586 * 2587 * Note: 2588 * It is implementation-defined whether I/O page real address validity checking 2589 * is done at time mappings are established or deferred until they are 2590 * accessed. 2591 */ 2592 #define HV_FAST_PCI_IOTSB_MAP 0x196 2593 2594 /* pci_iotsb_map_one() 2595 * TRAP: HV_FAST_TRAP 2596 * FUNCTION: HV_FAST_PCI_IOTSB_MAP_ONE 2597 * ARG0: devhandle 2598 * ARG1: iotsb_handle 2599 * ARG2: iotsb_index 2600 * ARG3: iotte_attributes 2601 * ARG4: r_addr 2602 * RET0: status 2603 * ERRORS: EINVAL Invalid devhandle,iotsb_handle, iotsb_index 2604 * or iotte_attributes 2605 * EBADALIGN Improperly aligned r_addr 2606 * ENORADDR Invalid r_addr 2607 * 2608 * This service creates and flushes a single mapping in the IOTSB defined by the 2609 * arguments devhandle, iotsb. 2610 * 2611 * The mapping for the page at r_addr is created at the IOTSB index specified by 2612 * iotsb_index with the attributes iotte_attributes. 2613 * 2614 * This service must not be used to demap a mapping. In other words, the mapping 2615 * must be valid and have one or both of the RW attribute bits set. 2616 * 2617 * Note: 2618 * It is implementation-defined whether I/O page real address validity checking 2619 * is done at time mappings are established or deferred until they are 2620 * accessed. 2621 */ 2622 #define HV_FAST_PCI_IOTSB_MAP_ONE 0x197 2623 2624 /* pci_iotsb_demap() 2625 * TRAP: HV_FAST_TRAP 2626 * FUNCTION: HV_FAST_PCI_IOTSB_DEMAP 2627 * ARG0: devhandle 2628 * ARG1: iotsb_handle 2629 * ARG2: iotsb_index 2630 * ARG3: #iottes 2631 * RET0: status 2632 * RET1: #unmapped 2633 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, iotsb_index or #iottes 2634 * 2635 * This service unmaps and flushes up to #iottes mappings starting at index 2636 * iotsb_index from the IOTSB defined by the arguments devhandle, iotsb. 2637 * 2638 * #iottes must be greater than zero. 2639 * 2640 * The actual number of IOTTEs unmapped is returned in #unmapped and may be less 2641 * than or equal to the requested number of IOTTEs, #iottes. 2642 * 2643 * If #unmapped is less than #iottes, the caller should continue to invoke this 2644 * service with updated iotsb_index and #iottes arguments until all pages are 2645 * demapped. 2646 */ 2647 #define HV_FAST_PCI_IOTSB_DEMAP 0x198 2648 2649 /* pci_iotsb_getmap() 2650 * TRAP: HV_FAST_TRAP 2651 * FUNCTION: HV_FAST_PCI_IOTSB_GETMAP 2652 * ARG0: devhandle 2653 * ARG1: iotsb_handle 2654 * ARG2: iotsb_index 2655 * RET0: status 2656 * RET1: r_addr 2657 * RET2: iotte_attributes 2658 * ERRORS: EINVAL Invalid devhandle, iotsb_handle, or iotsb_index 2659 * ENOMAP No mapping was found 2660 * 2661 * This service returns the mapping specified by index iotsb_index from the 2662 * IOTSB defined by the arguments devhandle, iotsb. 2663 * 2664 * Upon success, the real address of the mapping shall be returned in 2665 * r_addr and thethe IOTTE mapping attributes shall be returned in 2666 * iotte_attributes. 2667 * 2668 * The return value iotte_attributes may not include optional features used in 2669 * the call to create the mapping. 2670 */ 2671 #define HV_FAST_PCI_IOTSB_GETMAP 0x199 2672 2673 /* pci_iotsb_sync_mappings() 2674 * TRAP: HV_FAST_TRAP 2675 * FUNCTION: HV_FAST_PCI_IOTSB_SYNC_MAPPINGS 2676 * ARG0: devhandle 2677 * ARG1: iotsb_handle 2678 * ARG2: iotsb_index 2679 * ARG3: #iottes 2680 * RET0: status 2681 * RET1: #synced 2682 * ERROS: EINVAL Invalid devhandle, iotsb_handle, iotsb_index, or #iottes 2683 * 2684 * This service synchronizes #iottes mappings starting at index iotsb_index in 2685 * the IOTSB defined by the arguments devhandle, iotsb. 2686 * 2687 * #iottes must be greater than zero. 2688 * 2689 * The actual number of IOTTEs synchronized is returned in #synced, which may 2690 * be less than or equal to the requested number, #iottes. 2691 * 2692 * Upon a successful return, #synced is less than #iottes, the caller should 2693 * continue to invoke this service with updated iotsb_index and #iottes 2694 * arguments until all pages are synchronized. 2695 */ 2696 #define HV_FAST_PCI_IOTSB_SYNC_MAPPINGS 0x19a 2697 2698 /* Logical Domain Channel services. */ 2699 2700 #define LDC_CHANNEL_DOWN 0 2701 #define LDC_CHANNEL_UP 1 2702 #define LDC_CHANNEL_RESETTING 2 2703 2704 /* ldc_tx_qconf() 2705 * TRAP: HV_FAST_TRAP 2706 * FUNCTION: HV_FAST_LDC_TX_QCONF 2707 * ARG0: channel ID 2708 * ARG1: real address base of queue 2709 * ARG2: num entries in queue 2710 * RET0: status 2711 * 2712 * Configure transmit queue for the LDC endpoint specified by the 2713 * given channel ID, to be placed at the given real address, and 2714 * be of the given num entries. Num entries must be a power of two. 2715 * The real address base of the queue must be aligned on the queue 2716 * size. Each queue entry is 64-bytes, so for example, a 32 entry 2717 * queue must be aligned on a 2048 byte real address boundary. 2718 * 2719 * Upon configuration of a valid transmit queue the head and tail 2720 * pointers are set to a hypervisor specific identical value indicating 2721 * that the queue initially is empty. 2722 * 2723 * The endpoint's transmit queue is un-configured if num entries is zero. 2724 * 2725 * The maximum number of entries for each queue for a specific cpu may be 2726 * determined from the machine description. A transmit queue may be 2727 * specified even in the event that the LDC is down (peer endpoint has no 2728 * receive queue specified). Transmission will begin as soon as the peer 2729 * endpoint defines a receive queue. 2730 * 2731 * It is recommended that a guest wait for a transmit queue to empty prior 2732 * to reconfiguring it, or un-configuring it. Re or un-configuring of a 2733 * non-empty transmit queue behaves exactly as defined above, however it 2734 * is undefined as to how many of the pending entries in the original queue 2735 * will be delivered prior to the re-configuration taking effect. 2736 * Furthermore, as the queue configuration causes a reset of the head and 2737 * tail pointers there is no way for a guest to determine how many entries 2738 * have been sent after the configuration operation. 2739 */ 2740 #define HV_FAST_LDC_TX_QCONF 0xe0 2741 2742 /* ldc_tx_qinfo() 2743 * TRAP: HV_FAST_TRAP 2744 * FUNCTION: HV_FAST_LDC_TX_QINFO 2745 * ARG0: channel ID 2746 * RET0: status 2747 * RET1: real address base of queue 2748 * RET2: num entries in queue 2749 * 2750 * Return the configuration info for the transmit queue of LDC endpoint 2751 * defined by the given channel ID. The real address is the currently 2752 * defined real address base of the defined queue, and num entries is the 2753 * size of the queue in terms of number of entries. 2754 * 2755 * If the specified channel ID is a valid endpoint number, but no transmit 2756 * queue has been defined this service will return success, but with num 2757 * entries set to zero and the real address will have an undefined value. 2758 */ 2759 #define HV_FAST_LDC_TX_QINFO 0xe1 2760 2761 /* ldc_tx_get_state() 2762 * TRAP: HV_FAST_TRAP 2763 * FUNCTION: HV_FAST_LDC_TX_GET_STATE 2764 * ARG0: channel ID 2765 * RET0: status 2766 * RET1: head offset 2767 * RET2: tail offset 2768 * RET3: channel state 2769 * 2770 * Return the transmit state, and the head and tail queue pointers, for 2771 * the transmit queue of the LDC endpoint defined by the given channel ID. 2772 * The head and tail values are the byte offset of the head and tail 2773 * positions of the transmit queue for the specified endpoint. 2774 */ 2775 #define HV_FAST_LDC_TX_GET_STATE 0xe2 2776 2777 /* ldc_tx_set_qtail() 2778 * TRAP: HV_FAST_TRAP 2779 * FUNCTION: HV_FAST_LDC_TX_SET_QTAIL 2780 * ARG0: channel ID 2781 * ARG1: tail offset 2782 * RET0: status 2783 * 2784 * Update the tail pointer for the transmit queue associated with the LDC 2785 * endpoint defined by the given channel ID. The tail offset specified 2786 * must be aligned on a 64 byte boundary, and calculated so as to increase 2787 * the number of pending entries on the transmit queue. Any attempt to 2788 * decrease the number of pending transmit queue entires is considered 2789 * an invalid tail offset and will result in an EINVAL error. 2790 * 2791 * Since the tail of the transmit queue may not be moved backwards, the 2792 * transmit queue may be flushed by configuring a new transmit queue, 2793 * whereupon the hypervisor will configure the initial transmit head and 2794 * tail pointers to be equal. 2795 */ 2796 #define HV_FAST_LDC_TX_SET_QTAIL 0xe3 2797 2798 /* ldc_rx_qconf() 2799 * TRAP: HV_FAST_TRAP 2800 * FUNCTION: HV_FAST_LDC_RX_QCONF 2801 * ARG0: channel ID 2802 * ARG1: real address base of queue 2803 * ARG2: num entries in queue 2804 * RET0: status 2805 * 2806 * Configure receive queue for the LDC endpoint specified by the 2807 * given channel ID, to be placed at the given real address, and 2808 * be of the given num entries. Num entries must be a power of two. 2809 * The real address base of the queue must be aligned on the queue 2810 * size. Each queue entry is 64-bytes, so for example, a 32 entry 2811 * queue must be aligned on a 2048 byte real address boundary. 2812 * 2813 * The endpoint's transmit queue is un-configured if num entries is zero. 2814 * 2815 * If a valid receive queue is specified for a local endpoint the LDC is 2816 * in the up state for the purpose of transmission to this endpoint. 2817 * 2818 * The maximum number of entries for each queue for a specific cpu may be 2819 * determined from the machine description. 2820 * 2821 * As receive queue configuration causes a reset of the queue's head and 2822 * tail pointers there is no way for a gues to determine how many entries 2823 * have been received between a preceding ldc_get_rx_state() API call 2824 * and the completion of the configuration operation. It should be noted 2825 * that datagram delivery is not guaranteed via domain channels anyway, 2826 * and therefore any higher protocol should be resilient to datagram 2827 * loss if necessary. However, to overcome this specific race potential 2828 * it is recommended, for example, that a higher level protocol be employed 2829 * to ensure either retransmission, or ensure that no datagrams are pending 2830 * on the peer endpoint's transmit queue prior to the configuration process. 2831 */ 2832 #define HV_FAST_LDC_RX_QCONF 0xe4 2833 2834 /* ldc_rx_qinfo() 2835 * TRAP: HV_FAST_TRAP 2836 * FUNCTION: HV_FAST_LDC_RX_QINFO 2837 * ARG0: channel ID 2838 * RET0: status 2839 * RET1: real address base of queue 2840 * RET2: num entries in queue 2841 * 2842 * Return the configuration info for the receive queue of LDC endpoint 2843 * defined by the given channel ID. The real address is the currently 2844 * defined real address base of the defined queue, and num entries is the 2845 * size of the queue in terms of number of entries. 2846 * 2847 * If the specified channel ID is a valid endpoint number, but no receive 2848 * queue has been defined this service will return success, but with num 2849 * entries set to zero and the real address will have an undefined value. 2850 */ 2851 #define HV_FAST_LDC_RX_QINFO 0xe5 2852 2853 /* ldc_rx_get_state() 2854 * TRAP: HV_FAST_TRAP 2855 * FUNCTION: HV_FAST_LDC_RX_GET_STATE 2856 * ARG0: channel ID 2857 * RET0: status 2858 * RET1: head offset 2859 * RET2: tail offset 2860 * RET3: channel state 2861 * 2862 * Return the receive state, and the head and tail queue pointers, for 2863 * the receive queue of the LDC endpoint defined by the given channel ID. 2864 * The head and tail values are the byte offset of the head and tail 2865 * positions of the receive queue for the specified endpoint. 2866 */ 2867 #define HV_FAST_LDC_RX_GET_STATE 0xe6 2868 2869 /* ldc_rx_set_qhead() 2870 * TRAP: HV_FAST_TRAP 2871 * FUNCTION: HV_FAST_LDC_RX_SET_QHEAD 2872 * ARG0: channel ID 2873 * ARG1: head offset 2874 * RET0: status 2875 * 2876 * Update the head pointer for the receive queue associated with the LDC 2877 * endpoint defined by the given channel ID. The head offset specified 2878 * must be aligned on a 64 byte boundary, and calculated so as to decrease 2879 * the number of pending entries on the receive queue. Any attempt to 2880 * increase the number of pending receive queue entires is considered 2881 * an invalid head offset and will result in an EINVAL error. 2882 * 2883 * The receive queue may be flushed by setting the head offset equal 2884 * to the current tail offset. 2885 */ 2886 #define HV_FAST_LDC_RX_SET_QHEAD 0xe7 2887 2888 /* LDC Map Table Entry. Each slot is defined by a translation table 2889 * entry, as specified by the LDC_MTE_* bits below, and a 64-bit 2890 * hypervisor invalidation cookie. 2891 */ 2892 #define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */ 2893 #define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */ 2894 #define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */ 2895 #define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */ 2896 #define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */ 2897 #define LDC_MTE_EXEC 0x0000000000000040 /* execute */ 2898 #define LDC_MTE_WRITE 0x0000000000000020 /* read */ 2899 #define LDC_MTE_READ 0x0000000000000010 /* write */ 2900 #define LDC_MTE_SZALL 0x000000000000000f /* page size bits */ 2901 #define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */ 2902 #define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */ 2903 #define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */ 2904 #define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */ 2905 #define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */ 2906 #define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */ 2907 #define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */ 2908 #define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */ 2909 2910 #ifndef __ASSEMBLY__ 2911 struct ldc_mtable_entry { 2912 unsigned long mte; 2913 unsigned long cookie; 2914 }; 2915 #endif 2916 2917 /* ldc_set_map_table() 2918 * TRAP: HV_FAST_TRAP 2919 * FUNCTION: HV_FAST_LDC_SET_MAP_TABLE 2920 * ARG0: channel ID 2921 * ARG1: table real address 2922 * ARG2: num entries 2923 * RET0: status 2924 * 2925 * Register the MTE table at the given table real address, with the 2926 * specified num entries, for the LDC indicated by the given channel 2927 * ID. 2928 */ 2929 #define HV_FAST_LDC_SET_MAP_TABLE 0xea 2930 2931 /* ldc_get_map_table() 2932 * TRAP: HV_FAST_TRAP 2933 * FUNCTION: HV_FAST_LDC_GET_MAP_TABLE 2934 * ARG0: channel ID 2935 * RET0: status 2936 * RET1: table real address 2937 * RET2: num entries 2938 * 2939 * Return the configuration of the current mapping table registered 2940 * for the given channel ID. 2941 */ 2942 #define HV_FAST_LDC_GET_MAP_TABLE 0xeb 2943 2944 #define LDC_COPY_IN 0 2945 #define LDC_COPY_OUT 1 2946 2947 /* ldc_copy() 2948 * TRAP: HV_FAST_TRAP 2949 * FUNCTION: HV_FAST_LDC_COPY 2950 * ARG0: channel ID 2951 * ARG1: LDC_COPY_* direction code 2952 * ARG2: target real address 2953 * ARG3: local real address 2954 * ARG4: length in bytes 2955 * RET0: status 2956 * RET1: actual length in bytes 2957 */ 2958 #define HV_FAST_LDC_COPY 0xec 2959 2960 #define LDC_MEM_READ 1 2961 #define LDC_MEM_WRITE 2 2962 #define LDC_MEM_EXEC 4 2963 2964 /* ldc_mapin() 2965 * TRAP: HV_FAST_TRAP 2966 * FUNCTION: HV_FAST_LDC_MAPIN 2967 * ARG0: channel ID 2968 * ARG1: cookie 2969 * RET0: status 2970 * RET1: real address 2971 * RET2: LDC_MEM_* permissions 2972 */ 2973 #define HV_FAST_LDC_MAPIN 0xed 2974 2975 /* ldc_unmap() 2976 * TRAP: HV_FAST_TRAP 2977 * FUNCTION: HV_FAST_LDC_UNMAP 2978 * ARG0: real address 2979 * RET0: status 2980 */ 2981 #define HV_FAST_LDC_UNMAP 0xee 2982 2983 /* ldc_revoke() 2984 * TRAP: HV_FAST_TRAP 2985 * FUNCTION: HV_FAST_LDC_REVOKE 2986 * ARG0: channel ID 2987 * ARG1: cookie 2988 * ARG2: ldc_mtable_entry cookie 2989 * RET0: status 2990 */ 2991 #define HV_FAST_LDC_REVOKE 0xef 2992 2993 #ifndef __ASSEMBLY__ 2994 unsigned long sun4v_ldc_tx_qconf(unsigned long channel, 2995 unsigned long ra, 2996 unsigned long num_entries); 2997 unsigned long sun4v_ldc_tx_qinfo(unsigned long channel, 2998 unsigned long *ra, 2999 unsigned long *num_entries); 3000 unsigned long sun4v_ldc_tx_get_state(unsigned long channel, 3001 unsigned long *head_off, 3002 unsigned long *tail_off, 3003 unsigned long *chan_state); 3004 unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel, 3005 unsigned long tail_off); 3006 unsigned long sun4v_ldc_rx_qconf(unsigned long channel, 3007 unsigned long ra, 3008 unsigned long num_entries); 3009 unsigned long sun4v_ldc_rx_qinfo(unsigned long channel, 3010 unsigned long *ra, 3011 unsigned long *num_entries); 3012 unsigned long sun4v_ldc_rx_get_state(unsigned long channel, 3013 unsigned long *head_off, 3014 unsigned long *tail_off, 3015 unsigned long *chan_state); 3016 unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel, 3017 unsigned long head_off); 3018 unsigned long sun4v_ldc_set_map_table(unsigned long channel, 3019 unsigned long ra, 3020 unsigned long num_entries); 3021 unsigned long sun4v_ldc_get_map_table(unsigned long channel, 3022 unsigned long *ra, 3023 unsigned long *num_entries); 3024 unsigned long sun4v_ldc_copy(unsigned long channel, 3025 unsigned long dir_code, 3026 unsigned long tgt_raddr, 3027 unsigned long lcl_raddr, 3028 unsigned long len, 3029 unsigned long *actual_len); 3030 unsigned long sun4v_ldc_mapin(unsigned long channel, 3031 unsigned long cookie, 3032 unsigned long *ra, 3033 unsigned long *perm); 3034 unsigned long sun4v_ldc_unmap(unsigned long ra); 3035 unsigned long sun4v_ldc_revoke(unsigned long channel, 3036 unsigned long cookie, 3037 unsigned long mte_cookie); 3038 #endif 3039 3040 /* Performance counter services. */ 3041 3042 #define HV_PERF_JBUS_PERF_CTRL_REG 0x00 3043 #define HV_PERF_JBUS_PERF_CNT_REG 0x01 3044 #define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02 3045 #define HV_PERF_DRAM_PERF_CNT_REG_0 0x03 3046 #define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04 3047 #define HV_PERF_DRAM_PERF_CNT_REG_1 0x05 3048 #define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06 3049 #define HV_PERF_DRAM_PERF_CNT_REG_2 0x07 3050 #define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08 3051 #define HV_PERF_DRAM_PERF_CNT_REG_3 0x09 3052 3053 /* get_perfreg() 3054 * TRAP: HV_FAST_TRAP 3055 * FUNCTION: HV_FAST_GET_PERFREG 3056 * ARG0: performance reg number 3057 * RET0: status 3058 * RET1: performance reg value 3059 * ERRORS: EINVAL Invalid performance register number 3060 * ENOACCESS No access allowed to performance counters 3061 * 3062 * Read the value of the given DRAM/JBUS performance counter/control register. 3063 */ 3064 #define HV_FAST_GET_PERFREG 0x100 3065 3066 /* set_perfreg() 3067 * TRAP: HV_FAST_TRAP 3068 * FUNCTION: HV_FAST_SET_PERFREG 3069 * ARG0: performance reg number 3070 * ARG1: performance reg value 3071 * RET0: status 3072 * ERRORS: EINVAL Invalid performance register number 3073 * ENOACCESS No access allowed to performance counters 3074 * 3075 * Write the given performance reg value to the given DRAM/JBUS 3076 * performance counter/control register. 3077 */ 3078 #define HV_FAST_SET_PERFREG 0x101 3079 3080 #define HV_N2_PERF_SPARC_CTL 0x0 3081 #define HV_N2_PERF_DRAM_CTL0 0x1 3082 #define HV_N2_PERF_DRAM_CNT0 0x2 3083 #define HV_N2_PERF_DRAM_CTL1 0x3 3084 #define HV_N2_PERF_DRAM_CNT1 0x4 3085 #define HV_N2_PERF_DRAM_CTL2 0x5 3086 #define HV_N2_PERF_DRAM_CNT2 0x6 3087 #define HV_N2_PERF_DRAM_CTL3 0x7 3088 #define HV_N2_PERF_DRAM_CNT3 0x8 3089 3090 #define HV_FAST_N2_GET_PERFREG 0x104 3091 #define HV_FAST_N2_SET_PERFREG 0x105 3092 3093 #ifndef __ASSEMBLY__ 3094 unsigned long sun4v_niagara_getperf(unsigned long reg, 3095 unsigned long *val); 3096 unsigned long sun4v_niagara_setperf(unsigned long reg, 3097 unsigned long val); 3098 unsigned long sun4v_niagara2_getperf(unsigned long reg, 3099 unsigned long *val); 3100 unsigned long sun4v_niagara2_setperf(unsigned long reg, 3101 unsigned long val); 3102 #endif 3103 3104 /* MMU statistics services. 3105 * 3106 * The hypervisor maintains MMU statistics and privileged code provides 3107 * a buffer where these statistics can be collected. It is continually 3108 * updated once configured. The layout is as follows: 3109 */ 3110 #ifndef __ASSEMBLY__ 3111 struct hv_mmu_statistics { 3112 unsigned long immu_tsb_hits_ctx0_8k_tte; 3113 unsigned long immu_tsb_ticks_ctx0_8k_tte; 3114 unsigned long immu_tsb_hits_ctx0_64k_tte; 3115 unsigned long immu_tsb_ticks_ctx0_64k_tte; 3116 unsigned long __reserved1[2]; 3117 unsigned long immu_tsb_hits_ctx0_4mb_tte; 3118 unsigned long immu_tsb_ticks_ctx0_4mb_tte; 3119 unsigned long __reserved2[2]; 3120 unsigned long immu_tsb_hits_ctx0_256mb_tte; 3121 unsigned long immu_tsb_ticks_ctx0_256mb_tte; 3122 unsigned long __reserved3[4]; 3123 unsigned long immu_tsb_hits_ctxnon0_8k_tte; 3124 unsigned long immu_tsb_ticks_ctxnon0_8k_tte; 3125 unsigned long immu_tsb_hits_ctxnon0_64k_tte; 3126 unsigned long immu_tsb_ticks_ctxnon0_64k_tte; 3127 unsigned long __reserved4[2]; 3128 unsigned long immu_tsb_hits_ctxnon0_4mb_tte; 3129 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte; 3130 unsigned long __reserved5[2]; 3131 unsigned long immu_tsb_hits_ctxnon0_256mb_tte; 3132 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte; 3133 unsigned long __reserved6[4]; 3134 unsigned long dmmu_tsb_hits_ctx0_8k_tte; 3135 unsigned long dmmu_tsb_ticks_ctx0_8k_tte; 3136 unsigned long dmmu_tsb_hits_ctx0_64k_tte; 3137 unsigned long dmmu_tsb_ticks_ctx0_64k_tte; 3138 unsigned long __reserved7[2]; 3139 unsigned long dmmu_tsb_hits_ctx0_4mb_tte; 3140 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte; 3141 unsigned long __reserved8[2]; 3142 unsigned long dmmu_tsb_hits_ctx0_256mb_tte; 3143 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte; 3144 unsigned long __reserved9[4]; 3145 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte; 3146 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte; 3147 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte; 3148 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte; 3149 unsigned long __reserved10[2]; 3150 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte; 3151 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte; 3152 unsigned long __reserved11[2]; 3153 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte; 3154 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte; 3155 unsigned long __reserved12[4]; 3156 }; 3157 #endif 3158 3159 /* mmustat_conf() 3160 * TRAP: HV_FAST_TRAP 3161 * FUNCTION: HV_FAST_MMUSTAT_CONF 3162 * ARG0: real address 3163 * RET0: status 3164 * RET1: real address 3165 * ERRORS: ENORADDR Invalid real address 3166 * EBADALIGN Real address not aligned on 64-byte boundary 3167 * EBADTRAP API not supported on this processor 3168 * 3169 * Enable MMU statistic gathering using the buffer at the given real 3170 * address on the current virtual CPU. The new buffer real address 3171 * is given in ARG1, and the previously specified buffer real address 3172 * is returned in RET1, or is returned as zero for the first invocation. 3173 * 3174 * If the passed in real address argument is zero, this will disable 3175 * MMU statistic collection on the current virtual CPU. If an error is 3176 * returned then no statistics are collected. 3177 * 3178 * The buffer contents should be initialized to all zeros before being 3179 * given to the hypervisor or else the statistics will be meaningless. 3180 */ 3181 #define HV_FAST_MMUSTAT_CONF 0x102 3182 3183 /* mmustat_info() 3184 * TRAP: HV_FAST_TRAP 3185 * FUNCTION: HV_FAST_MMUSTAT_INFO 3186 * RET0: status 3187 * RET1: real address 3188 * ERRORS: EBADTRAP API not supported on this processor 3189 * 3190 * Return the current state and real address of the currently configured 3191 * MMU statistics buffer on the current virtual CPU. 3192 */ 3193 #define HV_FAST_MMUSTAT_INFO 0x103 3194 3195 #ifndef __ASSEMBLY__ 3196 unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra); 3197 unsigned long sun4v_mmustat_info(unsigned long *ra); 3198 #endif 3199 3200 /* NCS crypto services */ 3201 3202 /* ncs_request() sub-function numbers */ 3203 #define HV_NCS_QCONF 0x01 3204 #define HV_NCS_QTAIL_UPDATE 0x02 3205 3206 #ifndef __ASSEMBLY__ 3207 struct hv_ncs_queue_entry { 3208 /* MAU Control Register */ 3209 unsigned long mau_control; 3210 #define MAU_CONTROL_INV_PARITY 0x0000000000002000 3211 #define MAU_CONTROL_STRAND 0x0000000000001800 3212 #define MAU_CONTROL_BUSY 0x0000000000000400 3213 #define MAU_CONTROL_INT 0x0000000000000200 3214 #define MAU_CONTROL_OP 0x00000000000001c0 3215 #define MAU_CONTROL_OP_SHIFT 6 3216 #define MAU_OP_LOAD_MA_MEMORY 0x0 3217 #define MAU_OP_STORE_MA_MEMORY 0x1 3218 #define MAU_OP_MODULAR_MULT 0x2 3219 #define MAU_OP_MODULAR_REDUCE 0x3 3220 #define MAU_OP_MODULAR_EXP_LOOP 0x4 3221 #define MAU_CONTROL_LEN 0x000000000000003f 3222 #define MAU_CONTROL_LEN_SHIFT 0 3223 3224 /* Real address of bytes to load or store bytes 3225 * into/out-of the MAU. 3226 */ 3227 unsigned long mau_mpa; 3228 3229 /* Modular Arithmetic MA Offset Register. */ 3230 unsigned long mau_ma; 3231 3232 /* Modular Arithmetic N Prime Register. */ 3233 unsigned long mau_np; 3234 }; 3235 3236 struct hv_ncs_qconf_arg { 3237 unsigned long mid; /* MAU ID, 1 per core on Niagara */ 3238 unsigned long base; /* Real address base of queue */ 3239 unsigned long end; /* Real address end of queue */ 3240 unsigned long num_ents; /* Number of entries in queue */ 3241 }; 3242 3243 struct hv_ncs_qtail_update_arg { 3244 unsigned long mid; /* MAU ID, 1 per core on Niagara */ 3245 unsigned long tail; /* New tail index to use */ 3246 unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */ 3247 #define HV_NCS_SYNCFLAG_SYNC 0x00 3248 #define HV_NCS_SYNCFLAG_ASYNC 0x01 3249 }; 3250 #endif 3251 3252 /* ncs_request() 3253 * TRAP: HV_FAST_TRAP 3254 * FUNCTION: HV_FAST_NCS_REQUEST 3255 * ARG0: NCS sub-function 3256 * ARG1: sub-function argument real address 3257 * ARG2: size in bytes of sub-function argument 3258 * RET0: status 3259 * 3260 * The MAU chip of the Niagara processor is not directly accessible 3261 * to privileged code, instead it is programmed indirectly via this 3262 * hypervisor API. 3263 * 3264 * The interfaces defines a queue of MAU operations to perform. 3265 * Privileged code registers a queue with the hypervisor by invoking 3266 * this HVAPI with the HV_NCS_QCONF sub-function, which defines the 3267 * base, end, and number of entries of the queue. Each queue entry 3268 * contains a MAU register struct block. 3269 * 3270 * The privileged code then proceeds to add entries to the queue and 3271 * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only 3272 * synchronous operations are supported by the current hypervisor, 3273 * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to 3274 * completion and return HV_EOK, or return an error code. 3275 * 3276 * The real address of the sub-function argument must be aligned on at 3277 * least an 8-byte boundary. 3278 * 3279 * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte 3280 * offset, into the queue and must be less than or equal the 'num_ents' 3281 * argument given in the HV_NCS_QCONF call. 3282 */ 3283 #define HV_FAST_NCS_REQUEST 0x110 3284 3285 #ifndef __ASSEMBLY__ 3286 unsigned long sun4v_ncs_request(unsigned long request, 3287 unsigned long arg_ra, 3288 unsigned long arg_size); 3289 #endif 3290 3291 #define HV_FAST_FIRE_GET_PERFREG 0x120 3292 #define HV_FAST_FIRE_SET_PERFREG 0x121 3293 3294 #define HV_FAST_REBOOT_DATA_SET 0x172 3295 3296 #ifndef __ASSEMBLY__ 3297 unsigned long sun4v_reboot_data_set(unsigned long ra, 3298 unsigned long len); 3299 #endif 3300 3301 #define HV_FAST_VT_GET_PERFREG 0x184 3302 #define HV_FAST_VT_SET_PERFREG 0x185 3303 3304 #ifndef __ASSEMBLY__ 3305 unsigned long sun4v_vt_get_perfreg(unsigned long reg_num, 3306 unsigned long *reg_val); 3307 unsigned long sun4v_vt_set_perfreg(unsigned long reg_num, 3308 unsigned long reg_val); 3309 #endif 3310 3311 #define HV_FAST_T5_GET_PERFREG 0x1a8 3312 #define HV_FAST_T5_SET_PERFREG 0x1a9 3313 3314 #ifndef __ASSEMBLY__ 3315 unsigned long sun4v_t5_get_perfreg(unsigned long reg_num, 3316 unsigned long *reg_val); 3317 unsigned long sun4v_t5_set_perfreg(unsigned long reg_num, 3318 unsigned long reg_val); 3319 #endif 3320 3321 3322 #define HV_FAST_M7_GET_PERFREG 0x43 3323 #define HV_FAST_M7_SET_PERFREG 0x44 3324 3325 #ifndef __ASSEMBLY__ 3326 unsigned long sun4v_m7_get_perfreg(unsigned long reg_num, 3327 unsigned long *reg_val); 3328 unsigned long sun4v_m7_set_perfreg(unsigned long reg_num, 3329 unsigned long reg_val); 3330 #endif 3331 3332 /* Function numbers for HV_CORE_TRAP. */ 3333 #define HV_CORE_SET_VER 0x00 3334 #define HV_CORE_PUTCHAR 0x01 3335 #define HV_CORE_EXIT 0x02 3336 #define HV_CORE_GET_VER 0x03 3337 3338 /* Hypervisor API groups for use with HV_CORE_SET_VER and 3339 * HV_CORE_GET_VER. 3340 */ 3341 #define HV_GRP_SUN4V 0x0000 3342 #define HV_GRP_CORE 0x0001 3343 #define HV_GRP_INTR 0x0002 3344 #define HV_GRP_SOFT_STATE 0x0003 3345 #define HV_GRP_TM 0x0080 3346 #define HV_GRP_PCI 0x0100 3347 #define HV_GRP_LDOM 0x0101 3348 #define HV_GRP_SVC_CHAN 0x0102 3349 #define HV_GRP_NCS 0x0103 3350 #define HV_GRP_RNG 0x0104 3351 #define HV_GRP_PBOOT 0x0105 3352 #define HV_GRP_TPM 0x0107 3353 #define HV_GRP_SDIO 0x0108 3354 #define HV_GRP_SDIO_ERR 0x0109 3355 #define HV_GRP_REBOOT_DATA 0x0110 3356 #define HV_GRP_ATU 0x0111 3357 #define HV_GRP_M7_PERF 0x0114 3358 #define HV_GRP_NIAG_PERF 0x0200 3359 #define HV_GRP_FIRE_PERF 0x0201 3360 #define HV_GRP_N2_CPU 0x0202 3361 #define HV_GRP_NIU 0x0204 3362 #define HV_GRP_VF_CPU 0x0205 3363 #define HV_GRP_KT_CPU 0x0209 3364 #define HV_GRP_VT_CPU 0x020c 3365 #define HV_GRP_T5_CPU 0x0211 3366 #define HV_GRP_DIAG 0x0300 3367 3368 #ifndef __ASSEMBLY__ 3369 unsigned long sun4v_get_version(unsigned long group, 3370 unsigned long *major, 3371 unsigned long *minor); 3372 unsigned long sun4v_set_version(unsigned long group, 3373 unsigned long major, 3374 unsigned long minor, 3375 unsigned long *actual_minor); 3376 3377 int sun4v_hvapi_register(unsigned long group, unsigned long major, 3378 unsigned long *minor); 3379 void sun4v_hvapi_unregister(unsigned long group); 3380 int sun4v_hvapi_get(unsigned long group, 3381 unsigned long *major, 3382 unsigned long *minor); 3383 void sun4v_hvapi_init(void); 3384 #endif 3385 3386 #endif /* !(_SPARC64_HYPERVISOR_H) */ 3387