1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg #ifndef _SPARC64_ESTATE_H 3a439fe51SSam Ravnborg #define _SPARC64_ESTATE_H 4a439fe51SSam Ravnborg 5a439fe51SSam Ravnborg /* UltraSPARC-III E-cache Error Enable */ 6a439fe51SSam Ravnborg #define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */ 7a439fe51SSam Ravnborg #define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */ 8a439fe51SSam Ravnborg #define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */ 9a439fe51SSam Ravnborg #define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */ 10a439fe51SSam Ravnborg #define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */ 11a439fe51SSam Ravnborg #define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */ 12a439fe51SSam Ravnborg #define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */ 13a439fe51SSam Ravnborg 14a439fe51SSam Ravnborg /* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache 15a439fe51SSam Ravnborg * errors 2) uncorrectable E-cache errors. Such events only occur on reads 16a439fe51SSam Ravnborg * of the E-cache by the local processor for: 1) data loads 2) instruction 17a439fe51SSam Ravnborg * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge 18a439fe51SSam Ravnborg * 2) writeback 2) copyout. The AFSR bits associated with these traps are 19a439fe51SSam Ravnborg * UCC and UCU. 20a439fe51SSam Ravnborg */ 21a439fe51SSam Ravnborg 22a439fe51SSam Ravnborg /* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps 23a439fe51SSam Ravnborg * for uncorrectable ECC errors and system errors. 24a439fe51SSam Ravnborg * 25a439fe51SSam Ravnborg * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT, 26a439fe51SSam Ravnborg * or system bus BusERR: 27a439fe51SSam Ravnborg * 1) As the result of an instruction fetch, will generate instruction_access_error 28a439fe51SSam Ravnborg * 2) As the result of a load etc. will generate data_access_error. 29a439fe51SSam Ravnborg * 3) As the result of store merge completion, writeback, or copyout will 30a439fe51SSam Ravnborg * generate a disrupting ECC_error trap. 31a439fe51SSam Ravnborg * 4) As the result of such errors on instruction vector fetch can generate any 32a439fe51SSam Ravnborg * of the 3 trap types. 33a439fe51SSam Ravnborg * 34a439fe51SSam Ravnborg * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE, 35a439fe51SSam Ravnborg * BERR, and TO. 36a439fe51SSam Ravnborg */ 37a439fe51SSam Ravnborg 38a439fe51SSam Ravnborg /* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus 39a439fe51SSam Ravnborg * reads resulting in a hardware corrected data or MTAG ECC error will generate an 40a439fe51SSam Ravnborg * ECC_error disrupting trap with this bit enabled. 41a439fe51SSam Ravnborg * 42a439fe51SSam Ravnborg * This same trap will also be generated when a hardware corrected ECC error results 43a439fe51SSam Ravnborg * during store merge, writeback, and copyout operations. 44a439fe51SSam Ravnborg */ 45a439fe51SSam Ravnborg 46a439fe51SSam Ravnborg /* In general, if the trap enable bits above are disabled the AFSR bits will still 47a439fe51SSam Ravnborg * log the events even though the trap will not be generated by the processor. 48a439fe51SSam Ravnborg */ 49a439fe51SSam Ravnborg 50a439fe51SSam Ravnborg #endif /* _SPARC64_ESTATE_H */ 51