1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg #ifndef _SPARC64_DCU_H 3a439fe51SSam Ravnborg #define _SPARC64_DCU_H 4a439fe51SSam Ravnborg 5a439fe51SSam Ravnborg #include <linux/const.h> 6a439fe51SSam Ravnborg 7a439fe51SSam Ravnborg /* UltraSparc-III Data Cache Unit Control Register */ 8a439fe51SSam Ravnborg #define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */ 9a439fe51SSam Ravnborg #define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */ 10a439fe51SSam Ravnborg #define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */ 11a439fe51SSam Ravnborg #define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */ 12a439fe51SSam Ravnborg #define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */ 13a439fe51SSam Ravnborg #define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */ 14a439fe51SSam Ravnborg #define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */ 15a439fe51SSam Ravnborg #define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/ 16a439fe51SSam Ravnborg #define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */ 17a439fe51SSam Ravnborg #define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */ 18a439fe51SSam Ravnborg #define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */ 19a439fe51SSam Ravnborg #define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */ 20a439fe51SSam Ravnborg #define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/ 21a439fe51SSam Ravnborg #define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */ 22a439fe51SSam Ravnborg #define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/ 23a439fe51SSam Ravnborg #define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */ 24a439fe51SSam Ravnborg #define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */ 25a439fe51SSam Ravnborg #define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */ 26a439fe51SSam Ravnborg #define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */ 27a439fe51SSam Ravnborg 28a439fe51SSam Ravnborg #endif /* _SPARC64_DCU_H */ 29